* [PATCH] drm/i915/vdsc: intel_display conversions
@ 2025-02-27 11:22 Suraj Kandpal
2025-02-27 12:17 ` Jani Nikula
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Suraj Kandpal @ 2025-02-27 11:22 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: jani.nikula, Suraj Kandpal
intel_display conversions for vdsc in an effort to move away
from drm_i915_private.
While at it use display->platform.xx.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 180 +++++++++++-----------
1 file changed, 87 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 6e7151346382..35d558ca98db 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -22,14 +22,13 @@
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
- const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (!HAS_DSC(i915))
+ if (!HAS_DSC(display))
return false;
- if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
+ if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)
return false;
return true;
@@ -37,9 +36,9 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
- if (DISPLAY_VER(i915) >= 12)
+ if (DISPLAY_VER(display) >= 12)
return true;
if (cpu_transcoder == TRANSCODER_EDP ||
@@ -48,7 +47,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
return false;
/* There's no pipe A DSC engine on ICL */
- drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
+ drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
return true;
}
@@ -262,8 +261,7 @@ static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config
int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(pipe_config);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
int err;
@@ -276,7 +274,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
if (err) {
- drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
+ drm_dbg_kms(display->drm, "Slice dimension requirements not met\n");
return err;
}
@@ -287,7 +285,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
- if (DISPLAY_VER(dev_priv) >= 14 &&
+ if (DISPLAY_VER(display) >= 14 &&
pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
vdsc_cfg->native_420 = true;
/* We do not support YcBCr422 as of now */
@@ -308,7 +306,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
if (vdsc_cfg->bits_per_component < 8) {
- drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not met bpc: %d\n",
+ drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",
vdsc_cfg->bits_per_component);
return -EINVAL;
}
@@ -320,7 +318,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
* upto uncompressed bpp-1, hence add calculations for all the rc
* parameters
*/
- if (DISPLAY_VER(dev_priv) >= 13) {
+ if (DISPLAY_VER(display) >= 13) {
calculate_rc_params(vdsc_cfg);
} else {
if ((compressed_bpp == 8 ||
@@ -356,7 +354,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
enum intel_display_power_domain
intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
/*
@@ -370,7 +368,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
* the pipe in use. Hence another reference on the pipe power domain
* will suffice. (Except no VDSC/joining on ICL pipe A.)
*/
- if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
+ if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&
+ pipe == PIPE_A)
return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
else if (is_pipe_dsc(crtc, cpu_transcoder))
return POWER_DOMAIN_PIPE(pipe);
@@ -416,26 +415,25 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
int pps, u32 pps_val)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
i915_reg_t dsc_reg[3];
int i, vdsc_per_pipe, dsc_reg_num;
vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
- drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
+ drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
for (i = 0; i < dsc_reg_num; i++)
- intel_de_write(i915, dsc_reg[i], pps_val);
+ intel_de_write(display, dsc_reg[i], pps_val);
}
static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
@@ -529,7 +527,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
vdsc_cfg->slice_height);
intel_dsc_pps_write(crtc_state, 16, pps_val);
- if (DISPLAY_VER(dev_priv) >= 14) {
+ if (DISPLAY_VER(display) >= 14) {
/* PPS 17 */
pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
intel_dsc_pps_write(crtc_state, 17, pps_val);
@@ -547,44 +545,44 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
(u32)(vdsc_cfg->rc_buf_thresh[i] <<
BITS_PER_BYTE * (i % 4));
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
+ intel_de_write(display, DSCA_RC_BUF_THRESH_0,
rc_buf_thresh_dword[0]);
- intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
+ intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,
rc_buf_thresh_dword[1]);
- intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
+ intel_de_write(display, DSCA_RC_BUF_THRESH_1,
rc_buf_thresh_dword[2]);
- intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
+ intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,
rc_buf_thresh_dword[3]);
if (vdsc_instances_per_pipe > 1) {
- intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
+ intel_de_write(display, DSCC_RC_BUF_THRESH_0,
rc_buf_thresh_dword[0]);
- intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
+ intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW,
rc_buf_thresh_dword[1]);
- intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
+ intel_de_write(display, DSCC_RC_BUF_THRESH_1,
rc_buf_thresh_dword[2]);
- intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
+ intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW,
rc_buf_thresh_dword[3]);
}
} else {
- intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
+ intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),
rc_buf_thresh_dword[0]);
- intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
+ intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
rc_buf_thresh_dword[1]);
- intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
+ intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),
rc_buf_thresh_dword[2]);
- intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
+ intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
rc_buf_thresh_dword[3]);
if (vdsc_instances_per_pipe > 1) {
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_BUF_THRESH_0(pipe),
rc_buf_thresh_dword[0]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
rc_buf_thresh_dword[1]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_BUF_THRESH_1(pipe),
rc_buf_thresh_dword[2]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
rc_buf_thresh_dword[3]);
}
@@ -601,88 +599,88 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
(vdsc_cfg->rc_range_params[i].range_min_qp <<
RC_MIN_QP_SHIFT)) << 16 * (i % 2));
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
+ intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,
rc_range_params_dword[0]);
- intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
+ intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW,
rc_range_params_dword[1]);
- intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
+ intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,
rc_range_params_dword[2]);
- intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
+ intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW,
rc_range_params_dword[3]);
- intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
+ intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,
rc_range_params_dword[4]);
- intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
+ intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW,
rc_range_params_dword[5]);
- intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
+ intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,
rc_range_params_dword[6]);
- intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
+ intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW,
rc_range_params_dword[7]);
if (vdsc_instances_per_pipe > 1) {
- intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
+ intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0,
rc_range_params_dword[0]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
DSCC_RC_RANGE_PARAMETERS_0_UDW,
rc_range_params_dword[1]);
- intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
+ intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1,
rc_range_params_dword[2]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
DSCC_RC_RANGE_PARAMETERS_1_UDW,
rc_range_params_dword[3]);
- intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
+ intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2,
rc_range_params_dword[4]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
DSCC_RC_RANGE_PARAMETERS_2_UDW,
rc_range_params_dword[5]);
- intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
+ intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3,
rc_range_params_dword[6]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
DSCC_RC_RANGE_PARAMETERS_3_UDW,
rc_range_params_dword[7]);
}
} else {
- intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
+ intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
rc_range_params_dword[0]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
rc_range_params_dword[1]);
- intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
+ intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
rc_range_params_dword[2]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
rc_range_params_dword[3]);
- intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
+ intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
rc_range_params_dword[4]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
rc_range_params_dword[5]);
- intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
+ intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
rc_range_params_dword[6]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
rc_range_params_dword[7]);
if (vdsc_instances_per_pipe > 1) {
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
rc_range_params_dword[0]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
rc_range_params_dword[1]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
rc_range_params_dword[2]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
rc_range_params_dword[3]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
rc_range_params_dword[4]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
rc_range_params_dword[5]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
rc_range_params_dword[6]);
- intel_de_write(dev_priv,
+ intel_de_write(display,
ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
rc_range_params_dword[7]);
}
@@ -746,8 +744,8 @@ static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_tran
void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dss_ctl1_val = 0;
if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
@@ -756,14 +754,15 @@ void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
else
dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
- intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
+ intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
+ dss_ctl1_val);
}
}
void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dss_ctl1_val = 0;
u32 dss_ctl2_val = 0;
int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
@@ -796,28 +795,27 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
if (intel_crtc_is_bigjoiner_primary(crtc_state))
dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
}
- intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
- intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
+ intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
+ intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
}
void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
{
+ struct intel_display *display = to_intel_display(old_crtc_state);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/* Disable only if either of them is enabled */
if (old_crtc_state->dsc.compression_enable ||
old_crtc_state->joiner_pipes) {
- intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
- intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
+ intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
+ intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
}
}
static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
bool *all_equal)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
i915_reg_t dsc_reg[3];
int i, vdsc_per_pipe, dsc_reg_num;
u32 val;
@@ -825,16 +823,16 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
- drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
+ drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
*all_equal = true;
- val = intel_de_read(i915, dsc_reg[0]);
+ val = intel_de_read(display, dsc_reg[0]);
for (i = 1; i < dsc_reg_num; i++) {
- if (intel_de_read(i915, dsc_reg[i]) != val) {
+ if (intel_de_read(display, dsc_reg[i]) != val) {
*all_equal = false;
break;
}
@@ -845,22 +843,20 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
u32 val;
bool all_equal;
val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
- drm_WARN_ON(&i915->drm, !all_equal);
+ drm_WARN_ON(display->drm, !all_equal);
return val;
}
static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
u32 pps_temp;
@@ -946,7 +942,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
- if (DISPLAY_VER(i915) >= 14) {
+ if (DISPLAY_VER(display) >= 14) {
/* PPS 17 */
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
@@ -964,7 +960,6 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
@@ -979,8 +974,8 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
if (!wakeref)
return;
- dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
- dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
+ dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
+ dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));
crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
if (!crtc_state->dsc.compression_enable)
@@ -1020,8 +1015,7 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_display *display = to_intel_display(crtc);
+ struct intel_display *display = to_intel_display(crtc_state);
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
int min_cdclk;
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915/vdsc: intel_display conversions
2025-02-27 11:22 [PATCH] drm/i915/vdsc: intel_display conversions Suraj Kandpal
@ 2025-02-27 12:17 ` Jani Nikula
2025-02-27 16:03 ` Kandpal, Suraj
2025-02-27 12:57 ` ✓ i915.CI.BAT: success for " Patchwork
2025-02-27 23:25 ` ✗ i915.CI.Full: failure " Patchwork
2 siblings, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2025-02-27 12:17 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: Suraj Kandpal
On Thu, 27 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> intel_display conversions for vdsc in an effort to move away
> from drm_i915_private.
> While at it use display->platform.xx.
Please update with
-#include "i915_drv.h"
+#include "i915_utils.h"
and you get
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
BR,
Jani.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 180 +++++++++++-----------
> 1 file changed, 87 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 6e7151346382..35d558ca98db 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -22,14 +22,13 @@
>
> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
> {
> - const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> - if (!HAS_DSC(i915))
> + if (!HAS_DSC(display))
> return false;
>
> - if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
> + if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)
> return false;
>
> return true;
> @@ -37,9 +36,9 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
>
> static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
>
> - if (DISPLAY_VER(i915) >= 12)
> + if (DISPLAY_VER(display) >= 12)
> return true;
>
> if (cpu_transcoder == TRANSCODER_EDP ||
> @@ -48,7 +47,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
> return false;
>
> /* There's no pipe A DSC engine on ICL */
> - drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
> + drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
>
> return true;
> }
> @@ -262,8 +261,7 @@ static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config
>
> int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(pipe_config);
> struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
> int err;
> @@ -276,7 +274,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
>
> if (err) {
> - drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
> + drm_dbg_kms(display->drm, "Slice dimension requirements not met\n");
> return err;
> }
>
> @@ -287,7 +285,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
> pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
>
> - if (DISPLAY_VER(dev_priv) >= 14 &&
> + if (DISPLAY_VER(display) >= 14 &&
> pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> vdsc_cfg->native_420 = true;
> /* We do not support YcBCr422 as of now */
> @@ -308,7 +306,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>
> if (vdsc_cfg->bits_per_component < 8) {
> - drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not met bpc: %d\n",
> + drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",
> vdsc_cfg->bits_per_component);
> return -EINVAL;
> }
> @@ -320,7 +318,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> * upto uncompressed bpp-1, hence add calculations for all the rc
> * parameters
> */
> - if (DISPLAY_VER(dev_priv) >= 13) {
> + if (DISPLAY_VER(display) >= 13) {
> calculate_rc_params(vdsc_cfg);
> } else {
> if ((compressed_bpp == 8 ||
> @@ -356,7 +354,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> enum intel_display_power_domain
> intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> enum pipe pipe = crtc->pipe;
>
> /*
> @@ -370,7 +368,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
> * the pipe in use. Hence another reference on the pipe power domain
> * will suffice. (Except no VDSC/joining on ICL pipe A.)
> */
> - if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
> + if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&
> + pipe == PIPE_A)
> return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> else if (is_pipe_dsc(crtc, cpu_transcoder))
> return POWER_DOMAIN_PIPE(pipe);
> @@ -416,26 +415,25 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
> static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
> int pps, u32 pps_val)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> i915_reg_t dsc_reg[3];
> int i, vdsc_per_pipe, dsc_reg_num;
>
> vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
>
> - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
> + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
>
> intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
>
> for (i = 0; i < dsc_reg_num; i++)
> - intel_de_write(i915, dsc_reg[i], pps_val);
> + intel_de_write(display, dsc_reg[i], pps_val);
> }
>
> static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
> @@ -529,7 +527,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> vdsc_cfg->slice_height);
> intel_dsc_pps_write(crtc_state, 16, pps_val);
>
> - if (DISPLAY_VER(dev_priv) >= 14) {
> + if (DISPLAY_VER(display) >= 14) {
> /* PPS 17 */
> pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
> intel_dsc_pps_write(crtc_state, 17, pps_val);
> @@ -547,44 +545,44 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> (u32)(vdsc_cfg->rc_buf_thresh[i] <<
> BITS_PER_BYTE * (i % 4));
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
> + intel_de_write(display, DSCA_RC_BUF_THRESH_0,
> rc_buf_thresh_dword[0]);
> - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
> + intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,
> rc_buf_thresh_dword[1]);
> - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
> + intel_de_write(display, DSCA_RC_BUF_THRESH_1,
> rc_buf_thresh_dword[2]);
> - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
> + intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,
> rc_buf_thresh_dword[3]);
> if (vdsc_instances_per_pipe > 1) {
> - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
> + intel_de_write(display, DSCC_RC_BUF_THRESH_0,
> rc_buf_thresh_dword[0]);
> - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
> + intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW,
> rc_buf_thresh_dword[1]);
> - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
> + intel_de_write(display, DSCC_RC_BUF_THRESH_1,
> rc_buf_thresh_dword[2]);
> - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
> + intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW,
> rc_buf_thresh_dword[3]);
> }
> } else {
> - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
> + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),
> rc_buf_thresh_dword[0]);
> - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> rc_buf_thresh_dword[1]);
> - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
> + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),
> rc_buf_thresh_dword[2]);
> - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> rc_buf_thresh_dword[3]);
> if (vdsc_instances_per_pipe > 1) {
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_BUF_THRESH_0(pipe),
> rc_buf_thresh_dword[0]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
> rc_buf_thresh_dword[1]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_BUF_THRESH_1(pipe),
> rc_buf_thresh_dword[2]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
> rc_buf_thresh_dword[3]);
> }
> @@ -601,88 +599,88 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> (vdsc_cfg->rc_range_params[i].range_min_qp <<
> RC_MIN_QP_SHIFT)) << 16 * (i % 2));
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
> + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,
> rc_range_params_dword[0]);
> - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
> + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW,
> rc_range_params_dword[1]);
> - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
> + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,
> rc_range_params_dword[2]);
> - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
> + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW,
> rc_range_params_dword[3]);
> - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
> + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,
> rc_range_params_dword[4]);
> - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
> + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW,
> rc_range_params_dword[5]);
> - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
> + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,
> rc_range_params_dword[6]);
> - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
> + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW,
> rc_range_params_dword[7]);
> if (vdsc_instances_per_pipe > 1) {
> - intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
> + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0,
> rc_range_params_dword[0]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> DSCC_RC_RANGE_PARAMETERS_0_UDW,
> rc_range_params_dword[1]);
> - intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
> + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1,
> rc_range_params_dword[2]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> DSCC_RC_RANGE_PARAMETERS_1_UDW,
> rc_range_params_dword[3]);
> - intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
> + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2,
> rc_range_params_dword[4]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> DSCC_RC_RANGE_PARAMETERS_2_UDW,
> rc_range_params_dword[5]);
> - intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
> + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3,
> rc_range_params_dword[6]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> DSCC_RC_RANGE_PARAMETERS_3_UDW,
> rc_range_params_dword[7]);
> }
> } else {
> - intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> rc_range_params_dword[0]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
> rc_range_params_dword[1]);
> - intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> rc_range_params_dword[2]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
> rc_range_params_dword[3]);
> - intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> rc_range_params_dword[4]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
> rc_range_params_dword[5]);
> - intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> rc_range_params_dword[6]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
> rc_range_params_dword[7]);
> if (vdsc_instances_per_pipe > 1) {
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
> rc_range_params_dword[0]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
> rc_range_params_dword[1]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
> rc_range_params_dword[2]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
> rc_range_params_dword[3]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
> rc_range_params_dword[4]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
> rc_range_params_dword[5]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
> rc_range_params_dword[6]);
> - intel_de_write(dev_priv,
> + intel_de_write(display,
> ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
> rc_range_params_dword[7]);
> }
> @@ -746,8 +744,8 @@ static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_tran
>
> void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dss_ctl1_val = 0;
>
> if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
> @@ -756,14 +754,15 @@ void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
> else
> dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
>
> - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
> + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
> + dss_ctl1_val);
> }
> }
>
> void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dss_ctl1_val = 0;
> u32 dss_ctl2_val = 0;
> int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> @@ -796,28 +795,27 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
> if (intel_crtc_is_bigjoiner_primary(crtc_state))
> dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
> }
> - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
> - intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
> + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
> + intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
> }
>
> void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> {
> + struct intel_display *display = to_intel_display(old_crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /* Disable only if either of them is enabled */
> if (old_crtc_state->dsc.compression_enable ||
> old_crtc_state->joiner_pipes) {
> - intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
> - intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
> + intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
> + intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
> }
> }
>
> static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
> bool *all_equal)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> i915_reg_t dsc_reg[3];
> int i, vdsc_per_pipe, dsc_reg_num;
> u32 val;
> @@ -825,16 +823,16 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
> vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
>
> - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
> + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
>
> intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
>
> *all_equal = true;
>
> - val = intel_de_read(i915, dsc_reg[0]);
> + val = intel_de_read(display, dsc_reg[0]);
>
> for (i = 1; i < dsc_reg_num; i++) {
> - if (intel_de_read(i915, dsc_reg[i]) != val) {
> + if (intel_de_read(display, dsc_reg[i]) != val) {
> *all_equal = false;
> break;
> }
> @@ -845,22 +843,20 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
>
> static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> u32 val;
> bool all_equal;
>
> val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
> - drm_WARN_ON(&i915->drm, !all_equal);
> + drm_WARN_ON(display->drm, !all_equal);
>
> return val;
> }
>
> static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> u32 pps_temp;
>
> @@ -946,7 +942,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
>
> vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
>
> - if (DISPLAY_VER(i915) >= 14) {
> + if (DISPLAY_VER(display) >= 14) {
> /* PPS 17 */
> pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
>
> @@ -964,7 +960,6 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
> @@ -979,8 +974,8 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> if (!wakeref)
> return;
>
> - dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
> - dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
> + dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
> + dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));
>
> crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
> if (!crtc_state->dsc.compression_enable)
> @@ -1020,8 +1015,7 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
>
> int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_display *display = to_intel_display(crtc);
> + struct intel_display *display = to_intel_display(crtc_state);
> int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> int min_cdclk;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ i915.CI.BAT: success for drm/i915/vdsc: intel_display conversions
2025-02-27 11:22 [PATCH] drm/i915/vdsc: intel_display conversions Suraj Kandpal
2025-02-27 12:17 ` Jani Nikula
@ 2025-02-27 12:57 ` Patchwork
2025-02-27 23:25 ` ✗ i915.CI.Full: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2025-02-27 12:57 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4493 bytes --]
== Series Details ==
Series: drm/i915/vdsc: intel_display conversions
URL : https://patchwork.freedesktop.org/series/145570/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16193 -> Patchwork_145570v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/index.html
Participating hosts (44 -> 42)
------------------------------
Missing (2): fi-snb-2520m bat-jsl-3
Known issues
------------
Here are the changes found in Patchwork_145570v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- bat-rpls-4: [PASS][1] -> [FAIL][2] ([i915#13633])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@memory_region:
- bat-twl-2: NOTRUN -> [INCOMPLETE][3] ([i915#12445])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/bat-twl-2/igt@i915_selftest@live@memory_region.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][4] -> [SKIP][5] ([i915#9197]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-twl-1: [INCOMPLETE][6] ([i915#13776]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/bat-twl-1/igt@i915_selftest@live.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/bat-twl-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@reset:
- bat-twl-2: [INCOMPLETE][8] ([i915#12445]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/bat-twl-2/igt@i915_selftest@live@reset.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/bat-twl-2/igt@i915_selftest@live@reset.html
* igt@i915_selftest@live@ring_submission:
- bat-twl-1: [INCOMPLETE][10] -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/bat-twl-1/igt@i915_selftest@live@ring_submission.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/bat-twl-1/igt@i915_selftest@live@ring_submission.html
* igt@i915_selftest@live@workarounds:
- bat-arls-6: [DMESG-FAIL][12] ([i915#12061]) -> [PASS][13] +1 other test pass
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/bat-arls-6/igt@i915_selftest@live@workarounds.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/bat-arls-6/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_selftest@live:
- bat-twl-2: [INCOMPLETE][14] ([i915#12445] / [i915#13776]) -> [INCOMPLETE][15] ([i915#12435] / [i915#12445] / [i915#13761] / [i915#13776])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/bat-twl-2/igt@i915_selftest@live.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/bat-twl-2/igt@i915_selftest@live.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
[i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445
[i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633
[i915#13761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13761
[i915#13776]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13776
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
Build changes
-------------
* Linux: CI_DRM_16193 -> Patchwork_145570v1
CI-20190529: 20190529
CI_DRM_16193: 1a52d296ec3278de76f33064361b059a152c3fc3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8250: 43a53635da9a5ecb1a9ca189cb15df2c0b78bd38 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_145570v1: 1a52d296ec3278de76f33064361b059a152c3fc3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/index.html
[-- Attachment #2: Type: text/html, Size: 5648 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/i915/vdsc: intel_display conversions
2025-02-27 12:17 ` Jani Nikula
@ 2025-02-27 16:03 ` Kandpal, Suraj
2025-02-27 18:47 ` Jani Nikula
0 siblings, 1 reply; 7+ messages in thread
From: Kandpal, Suraj @ 2025-02-27 16:03 UTC (permalink / raw)
To: Nikula, Jani, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, February 27, 2025 5:47 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH] drm/i915/vdsc: intel_display conversions
>
> On Thu, 27 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > intel_display conversions for vdsc in an effort to move away from
> > drm_i915_private.
> > While at it use display->platform.xx.
>
> Please update with
>
> -#include "i915_drv.h"
> +#include "i915_utils.h"
>
> and you get
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Thanks for the reviews pushed to drm-intel-next with the above mentioned changes
Regards,
Suraj Kandpal
>
>
> BR,
> Jani.
>
>
>
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 180
> > +++++++++++-----------
> > 1 file changed, 87 insertions(+), 93 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 6e7151346382..35d558ca98db 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -22,14 +22,13 @@
> >
> > bool intel_dsc_source_support(const struct intel_crtc_state
> > *crtc_state) {
> > - const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + struct intel_display *display = to_intel_display(crtc_state);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >
> > - if (!HAS_DSC(i915))
> > + if (!HAS_DSC(display))
> > return false;
> >
> > - if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
> > + if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)
> > return false;
> >
> > return true;
> > @@ -37,9 +36,9 @@ bool intel_dsc_source_support(const struct
> > intel_crtc_state *crtc_state)
> >
> > static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder
> > cpu_transcoder) {
> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + struct intel_display *display = to_intel_display(crtc);
> >
> > - if (DISPLAY_VER(i915) >= 12)
> > + if (DISPLAY_VER(display) >= 12)
> > return true;
> >
> > if (cpu_transcoder == TRANSCODER_EDP || @@ -48,7 +47,7 @@ static
> > bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
> > return false;
> >
> > /* There's no pipe A DSC engine on ICL */
> > - drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
> > + drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
> >
> > return true;
> > }
> > @@ -262,8 +261,7 @@ static int intel_dsc_slice_dimensions_valid(struct
> > intel_crtc_state *pipe_config
> >
> > int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + struct intel_display *display = to_intel_display(pipe_config);
> > struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> > u16 compressed_bpp = fxp_q4_to_int(pipe_config-
> >dsc.compressed_bpp_x16);
> > int err;
> > @@ -276,7 +274,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
> > err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
> >
> > if (err) {
> > - drm_dbg_kms(&dev_priv->drm, "Slice dimension
> requirements not met\n");
> > + drm_dbg_kms(display->drm, "Slice dimension requirements
> not
> > +met\n");
> > return err;
> > }
> >
> > @@ -287,7 +285,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
> > vdsc_cfg->convert_rgb = pipe_config->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR420 &&
> > pipe_config->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR444;
> >
> > - if (DISPLAY_VER(dev_priv) >= 14 &&
> > + if (DISPLAY_VER(display) >= 14 &&
> > pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> > vdsc_cfg->native_420 = true;
> > /* We do not support YcBCr422 as of now */ @@ -308,7 +306,7 @@ int
> > intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> >
> > if (vdsc_cfg->bits_per_component < 8) {
> > - drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not
> met bpc: %d\n",
> > + drm_dbg_kms(display->drm, "DSC bpc requirements not met
> bpc: %d\n",
> > vdsc_cfg->bits_per_component);
> > return -EINVAL;
> > }
> > @@ -320,7 +318,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
> > * upto uncompressed bpp-1, hence add calculations for all the rc
> > * parameters
> > */
> > - if (DISPLAY_VER(dev_priv) >= 13) {
> > + if (DISPLAY_VER(display) >= 13) {
> > calculate_rc_params(vdsc_cfg);
> > } else {
> > if ((compressed_bpp == 8 ||
> > @@ -356,7 +354,7 @@ int intel_dsc_compute_params(struct
> > intel_crtc_state *pipe_config) enum intel_display_power_domain
> > intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
> > cpu_transcoder) {
> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + struct intel_display *display = to_intel_display(crtc);
> > enum pipe pipe = crtc->pipe;
> >
> > /*
> > @@ -370,7 +368,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc,
> enum transcoder cpu_transcoder)
> > * the pipe in use. Hence another reference on the pipe power domain
> > * will suffice. (Except no VDSC/joining on ICL pipe A.)
> > */
> > - if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe ==
> PIPE_A)
> > + if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&
> > + pipe == PIPE_A)
> > return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> > else if (is_pipe_dsc(crtc, cpu_transcoder))
> > return POWER_DOMAIN_PIPE(pipe);
> > @@ -416,26 +415,25 @@ static void intel_dsc_get_pps_reg(const struct
> > intel_crtc_state *crtc_state, int static void intel_dsc_pps_write(const struct
> intel_crtc_state *crtc_state,
> > int pps, u32 pps_val)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + struct intel_display *display = to_intel_display(crtc_state);
> > i915_reg_t dsc_reg[3];
> > int i, vdsc_per_pipe, dsc_reg_num;
> >
> > vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> > dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
> >
> > - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
> > + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
> >
> > intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
> >
> > for (i = 0; i < dsc_reg_num; i++)
> > - intel_de_write(i915, dsc_reg[i], pps_val);
> > + intel_de_write(display, dsc_reg[i], pps_val);
> > }
> >
> > static void intel_dsc_pps_configure(const struct intel_crtc_state
> > *crtc_state) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > enum pipe pipe = crtc->pipe;
> > @@ -529,7 +527,7 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
> > vdsc_cfg->slice_height);
> > intel_dsc_pps_write(crtc_state, 16, pps_val);
> >
> > - if (DISPLAY_VER(dev_priv) >= 14) {
> > + if (DISPLAY_VER(display) >= 14) {
> > /* PPS 17 */
> > pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
> > intel_dsc_pps_write(crtc_state, 17, pps_val); @@ -547,44
> +545,44 @@
> > static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> > (u32)(vdsc_cfg->rc_buf_thresh[i] <<
> > BITS_PER_BYTE * (i % 4));
> > if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
> > + intel_de_write(display, DSCA_RC_BUF_THRESH_0,
> > rc_buf_thresh_dword[0]);
> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
> > + intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,
> > rc_buf_thresh_dword[1]);
> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
> > + intel_de_write(display, DSCA_RC_BUF_THRESH_1,
> > rc_buf_thresh_dword[2]);
> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
> > + intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,
> > rc_buf_thresh_dword[3]);
> > if (vdsc_instances_per_pipe > 1) {
> > - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
> > + intel_de_write(display, DSCC_RC_BUF_THRESH_0,
> > rc_buf_thresh_dword[0]);
> > - intel_de_write(dev_priv,
> DSCC_RC_BUF_THRESH_0_UDW,
> > + intel_de_write(display,
> DSCC_RC_BUF_THRESH_0_UDW,
> > rc_buf_thresh_dword[1]);
> > - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
> > + intel_de_write(display, DSCC_RC_BUF_THRESH_1,
> > rc_buf_thresh_dword[2]);
> > - intel_de_write(dev_priv,
> DSCC_RC_BUF_THRESH_1_UDW,
> > + intel_de_write(display,
> DSCC_RC_BUF_THRESH_1_UDW,
> > rc_buf_thresh_dword[3]);
> > }
> > } else {
> > - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
> > + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),
> > rc_buf_thresh_dword[0]);
> > - intel_de_write(dev_priv,
> ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> > + intel_de_write(display,
> ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> > rc_buf_thresh_dword[1]);
> > - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
> > + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),
> > rc_buf_thresh_dword[2]);
> > - intel_de_write(dev_priv,
> ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> > + intel_de_write(display,
> ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> > rc_buf_thresh_dword[3]);
> > if (vdsc_instances_per_pipe > 1) {
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> > ICL_DSC1_RC_BUF_THRESH_0(pipe),
> > rc_buf_thresh_dword[0]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> > ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
> > rc_buf_thresh_dword[1]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> > ICL_DSC1_RC_BUF_THRESH_1(pipe),
> > rc_buf_thresh_dword[2]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> > ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
> > rc_buf_thresh_dword[3]);
> > }
> > @@ -601,88 +599,88 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
> > (vdsc_cfg->rc_range_params[i].range_min_qp <<
> > RC_MIN_QP_SHIFT)) << 16 * (i % 2));
> > if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,
> > rc_range_params_dword[0]);
> > - intel_de_write(dev_priv,
> DSCA_RC_RANGE_PARAMETERS_0_UDW,
> > + intel_de_write(display,
> DSCA_RC_RANGE_PARAMETERS_0_UDW,
> > rc_range_params_dword[1]);
> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,
> > rc_range_params_dword[2]);
> > - intel_de_write(dev_priv,
> DSCA_RC_RANGE_PARAMETERS_1_UDW,
> > + intel_de_write(display,
> DSCA_RC_RANGE_PARAMETERS_1_UDW,
> > rc_range_params_dword[3]);
> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,
> > rc_range_params_dword[4]);
> > - intel_de_write(dev_priv,
> DSCA_RC_RANGE_PARAMETERS_2_UDW,
> > + intel_de_write(display,
> DSCA_RC_RANGE_PARAMETERS_2_UDW,
> > rc_range_params_dword[5]);
> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,
> > rc_range_params_dword[6]);
> > - intel_de_write(dev_priv,
> DSCA_RC_RANGE_PARAMETERS_3_UDW,
> > + intel_de_write(display,
> DSCA_RC_RANGE_PARAMETERS_3_UDW,
> > rc_range_params_dword[7]);
> > if (vdsc_instances_per_pipe > 1) {
> > - intel_de_write(dev_priv,
> DSCC_RC_RANGE_PARAMETERS_0,
> > + intel_de_write(display,
> DSCC_RC_RANGE_PARAMETERS_0,
> > rc_range_params_dword[0]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> > DSCC_RC_RANGE_PARAMETERS_0_UDW,
> > rc_range_params_dword[1]);
> > - intel_de_write(dev_priv,
> DSCC_RC_RANGE_PARAMETERS_1,
> > + intel_de_write(display,
> DSCC_RC_RANGE_PARAMETERS_1,
> > rc_range_params_dword[2]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> > DSCC_RC_RANGE_PARAMETERS_1_UDW,
> > rc_range_params_dword[3]);
> > - intel_de_write(dev_priv,
> DSCC_RC_RANGE_PARAMETERS_2,
> > + intel_de_write(display,
> DSCC_RC_RANGE_PARAMETERS_2,
> > rc_range_params_dword[4]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> > DSCC_RC_RANGE_PARAMETERS_2_UDW,
> > rc_range_params_dword[5]);
> > - intel_de_write(dev_priv,
> DSCC_RC_RANGE_PARAMETERS_3,
> > + intel_de_write(display,
> DSCC_RC_RANGE_PARAMETERS_3,
> > rc_range_params_dword[6]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> > DSCC_RC_RANGE_PARAMETERS_3_UDW,
> > rc_range_params_dword[7]);
> > }
> > } else {
> > - intel_de_write(dev_priv,
> ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> > + intel_de_write(display,
> ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> > rc_range_params_dword[0]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
> > rc_range_params_dword[1]);
> > - intel_de_write(dev_priv,
> ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> > + intel_de_write(display,
> ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> > rc_range_params_dword[2]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
> > rc_range_params_dword[3]);
> > - intel_de_write(dev_priv,
> ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> > + intel_de_write(display,
> ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> > rc_range_params_dword[4]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
> > rc_range_params_dword[5]);
> > - intel_de_write(dev_priv,
> ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> > + intel_de_write(display,
> ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> > rc_range_params_dword[6]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
> > rc_range_params_dword[7]);
> > if (vdsc_instances_per_pipe > 1) {
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
> > rc_range_params_dword[0]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
> > rc_range_params_dword[1]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
> > rc_range_params_dword[2]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
> > rc_range_params_dword[3]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
> > rc_range_params_dword[4]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
> > rc_range_params_dword[5]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
> > rc_range_params_dword[6]);
> > - intel_de_write(dev_priv,
> > + intel_de_write(display,
> >
> ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
> > rc_range_params_dword[7]);
> > }
> > @@ -746,8 +744,8 @@ static i915_reg_t dss_ctl2_reg(struct intel_crtc
> > *crtc, enum transcoder cpu_tran
> >
> > void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> > *crtc_state) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > u32 dss_ctl1_val = 0;
> >
> > if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable)
> > { @@ -756,14 +754,15 @@ void intel_uncompressed_joiner_enable(const
> struct intel_crtc_state *crtc_state)
> > else
> > dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
> >
> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state-
> >cpu_transcoder), dss_ctl1_val);
> > + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state-
> >cpu_transcoder),
> > + dss_ctl1_val);
> > }
> > }
> >
> > void intel_dsc_enable(const struct intel_crtc_state *crtc_state) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > u32 dss_ctl1_val = 0;
> > u32 dss_ctl2_val = 0;
> > int vdsc_instances_per_pipe =
> > intel_dsc_get_vdsc_per_pipe(crtc_state);
> > @@ -796,28 +795,27 @@ void intel_dsc_enable(const struct intel_crtc_state
> *crtc_state)
> > if (intel_crtc_is_bigjoiner_primary(crtc_state))
> > dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
> > }
> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state-
> >cpu_transcoder), dss_ctl1_val);
> > - intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state-
> >cpu_transcoder), dss_ctl2_val);
> > + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
> dss_ctl1_val);
> > + intel_de_write(display, dss_ctl2_reg(crtc,
> > +crtc_state->cpu_transcoder), dss_ctl2_val);
> > }
> >
> > void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> > {
> > + struct intel_display *display = to_intel_display(old_crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > /* Disable only if either of them is enabled */
> > if (old_crtc_state->dsc.compression_enable ||
> > old_crtc_state->joiner_pipes) {
> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state-
> >cpu_transcoder), 0);
> > - intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state-
> >cpu_transcoder), 0);
> > + intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state-
> >cpu_transcoder), 0);
> > + intel_de_write(display, dss_ctl2_reg(crtc,
> > +old_crtc_state->cpu_transcoder), 0);
> > }
> > }
> >
> > static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
> > bool *all_equal)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + struct intel_display *display = to_intel_display(crtc_state);
> > i915_reg_t dsc_reg[3];
> > int i, vdsc_per_pipe, dsc_reg_num;
> > u32 val;
> > @@ -825,16 +823,16 @@ static u32 intel_dsc_pps_read(struct
> intel_crtc_state *crtc_state, int pps,
> > vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> > dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
> >
> > - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
> > + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
> >
> > intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
> >
> > *all_equal = true;
> >
> > - val = intel_de_read(i915, dsc_reg[0]);
> > + val = intel_de_read(display, dsc_reg[0]);
> >
> > for (i = 1; i < dsc_reg_num; i++) {
> > - if (intel_de_read(i915, dsc_reg[i]) != val) {
> > + if (intel_de_read(display, dsc_reg[i]) != val) {
> > *all_equal = false;
> > break;
> > }
> > @@ -845,22 +843,20 @@ static u32 intel_dsc_pps_read(struct
> > intel_crtc_state *crtc_state, int pps,
> >
> > static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state
> > *crtc_state, int pps) {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + struct intel_display *display = to_intel_display(crtc_state);
> > u32 val;
> > bool all_equal;
> >
> > val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
> > - drm_WARN_ON(&i915->drm, !all_equal);
> > + drm_WARN_ON(display->drm, !all_equal);
> >
> > return val;
> > }
> >
> > static void intel_dsc_get_pps_config(struct intel_crtc_state
> > *crtc_state) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > int num_vdsc_instances =
> intel_dsc_get_num_vdsc_instances(crtc_state);
> > u32 pps_temp;
> >
> > @@ -946,7 +942,7 @@ static void intel_dsc_get_pps_config(struct
> > intel_crtc_state *crtc_state)
> >
> > vdsc_cfg->slice_chunk_size =
> > REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
> >
> > - if (DISPLAY_VER(i915) >= 14) {
> > + if (DISPLAY_VER(display) >= 14) {
> > /* PPS 17 */
> > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
> >
> > @@ -964,7 +960,6 @@ void intel_dsc_get_config(struct intel_crtc_state
> > *crtc_state) {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > enum intel_display_power_domain power_domain;
> > intel_wakeref_t wakeref;
> > @@ -979,8 +974,8 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state)
> > if (!wakeref)
> > return;
> >
> > - dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
> > - dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
> > + dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
> > + dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc,
> > +cpu_transcoder));
> >
> > crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
> > if (!crtc_state->dsc.compression_enable)
> > @@ -1020,8 +1015,7 @@ void intel_vdsc_state_dump(struct drm_printer
> > *p, int indent,
> >
> > int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct intel_display *display = to_intel_display(crtc);
> > + struct intel_display *display = to_intel_display(crtc_state);
> > int num_vdsc_instances =
> intel_dsc_get_num_vdsc_instances(crtc_state);
> > int min_cdclk;
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/i915/vdsc: intel_display conversions
2025-02-27 16:03 ` Kandpal, Suraj
@ 2025-02-27 18:47 ` Jani Nikula
2025-02-28 1:30 ` Kandpal, Suraj
0 siblings, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2025-02-27 18:47 UTC (permalink / raw)
To: Kandpal, Suraj, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
On Thu, 27 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Thursday, February 27, 2025 5:47 PM
>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
>> intel-gfx@lists.freedesktop.org
>> Cc: Kandpal, Suraj <suraj.kandpal@intel.com>
>> Subject: Re: [PATCH] drm/i915/vdsc: intel_display conversions
>>
>> On Thu, 27 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> > intel_display conversions for vdsc in an effort to move away from
>> > drm_i915_private.
>> > While at it use display->platform.xx.
>>
>> Please update with
>>
>> -#include "i915_drv.h"
>> +#include "i915_utils.h"
>>
>> and you get
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Thanks for the reviews pushed to drm-intel-next with the above
> mentioned changes
I didn't really mean you should make the changes while applying.
BR,
Jani.
>
> Regards,
> Suraj Kandpal
>
>>
>>
>> BR,
>> Jani.
>>
>>
>>
>> >
>> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_vdsc.c | 180
>> > +++++++++++-----------
>> > 1 file changed, 87 insertions(+), 93 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index 6e7151346382..35d558ca98db 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -22,14 +22,13 @@
>> >
>> > bool intel_dsc_source_support(const struct intel_crtc_state
>> > *crtc_state) {
>> > - const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> >
>> > - if (!HAS_DSC(i915))
>> > + if (!HAS_DSC(display))
>> > return false;
>> >
>> > - if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
>> > + if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)
>> > return false;
>> >
>> > return true;
>> > @@ -37,9 +36,9 @@ bool intel_dsc_source_support(const struct
>> > intel_crtc_state *crtc_state)
>> >
>> > static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder
>> > cpu_transcoder) {
>> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > + struct intel_display *display = to_intel_display(crtc);
>> >
>> > - if (DISPLAY_VER(i915) >= 12)
>> > + if (DISPLAY_VER(display) >= 12)
>> > return true;
>> >
>> > if (cpu_transcoder == TRANSCODER_EDP || @@ -48,7 +47,7 @@ static
>> > bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>> > return false;
>> >
>> > /* There's no pipe A DSC engine on ICL */
>> > - drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
>> > + drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
>> >
>> > return true;
>> > }
>> > @@ -262,8 +261,7 @@ static int intel_dsc_slice_dimensions_valid(struct
>> > intel_crtc_state *pipe_config
>> >
>> > int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) {
>> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > + struct intel_display *display = to_intel_display(pipe_config);
>> > struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
>> > u16 compressed_bpp = fxp_q4_to_int(pipe_config-
>> >dsc.compressed_bpp_x16);
>> > int err;
>> > @@ -276,7 +274,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
>> *pipe_config)
>> > err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
>> >
>> > if (err) {
>> > - drm_dbg_kms(&dev_priv->drm, "Slice dimension
>> requirements not met\n");
>> > + drm_dbg_kms(display->drm, "Slice dimension requirements
>> not
>> > +met\n");
>> > return err;
>> > }
>> >
>> > @@ -287,7 +285,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
>> *pipe_config)
>> > vdsc_cfg->convert_rgb = pipe_config->output_format !=
>> INTEL_OUTPUT_FORMAT_YCBCR420 &&
>> > pipe_config->output_format !=
>> INTEL_OUTPUT_FORMAT_YCBCR444;
>> >
>> > - if (DISPLAY_VER(dev_priv) >= 14 &&
>> > + if (DISPLAY_VER(display) >= 14 &&
>> > pipe_config->output_format ==
>> INTEL_OUTPUT_FORMAT_YCBCR420)
>> > vdsc_cfg->native_420 = true;
>> > /* We do not support YcBCr422 as of now */ @@ -308,7 +306,7 @@ int
>> > intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>> >
>> > if (vdsc_cfg->bits_per_component < 8) {
>> > - drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not
>> met bpc: %d\n",
>> > + drm_dbg_kms(display->drm, "DSC bpc requirements not met
>> bpc: %d\n",
>> > vdsc_cfg->bits_per_component);
>> > return -EINVAL;
>> > }
>> > @@ -320,7 +318,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
>> *pipe_config)
>> > * upto uncompressed bpp-1, hence add calculations for all the rc
>> > * parameters
>> > */
>> > - if (DISPLAY_VER(dev_priv) >= 13) {
>> > + if (DISPLAY_VER(display) >= 13) {
>> > calculate_rc_params(vdsc_cfg);
>> > } else {
>> > if ((compressed_bpp == 8 ||
>> > @@ -356,7 +354,7 @@ int intel_dsc_compute_params(struct
>> > intel_crtc_state *pipe_config) enum intel_display_power_domain
>> > intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
>> > cpu_transcoder) {
>> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > + struct intel_display *display = to_intel_display(crtc);
>> > enum pipe pipe = crtc->pipe;
>> >
>> > /*
>> > @@ -370,7 +368,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc,
>> enum transcoder cpu_transcoder)
>> > * the pipe in use. Hence another reference on the pipe power domain
>> > * will suffice. (Except no VDSC/joining on ICL pipe A.)
>> > */
>> > - if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe ==
>> PIPE_A)
>> > + if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&
>> > + pipe == PIPE_A)
>> > return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
>> > else if (is_pipe_dsc(crtc, cpu_transcoder))
>> > return POWER_DOMAIN_PIPE(pipe);
>> > @@ -416,26 +415,25 @@ static void intel_dsc_get_pps_reg(const struct
>> > intel_crtc_state *crtc_state, int static void intel_dsc_pps_write(const struct
>> intel_crtc_state *crtc_state,
>> > int pps, u32 pps_val)
>> > {
>> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > i915_reg_t dsc_reg[3];
>> > int i, vdsc_per_pipe, dsc_reg_num;
>> >
>> > vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
>> > dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
>> >
>> > - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
>> > + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
>> >
>> > intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
>> >
>> > for (i = 0; i < dsc_reg_num; i++)
>> > - intel_de_write(i915, dsc_reg[i], pps_val);
>> > + intel_de_write(display, dsc_reg[i], pps_val);
>> > }
>> >
>> > static void intel_dsc_pps_configure(const struct intel_crtc_state
>> > *crtc_state) {
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> > enum pipe pipe = crtc->pipe;
>> > @@ -529,7 +527,7 @@ static void intel_dsc_pps_configure(const struct
>> intel_crtc_state *crtc_state)
>> > vdsc_cfg->slice_height);
>> > intel_dsc_pps_write(crtc_state, 16, pps_val);
>> >
>> > - if (DISPLAY_VER(dev_priv) >= 14) {
>> > + if (DISPLAY_VER(display) >= 14) {
>> > /* PPS 17 */
>> > pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg-
>> >second_line_bpg_offset);
>> > intel_dsc_pps_write(crtc_state, 17, pps_val); @@ -547,44
>> +545,44 @@
>> > static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> > (u32)(vdsc_cfg->rc_buf_thresh[i] <<
>> > BITS_PER_BYTE * (i % 4));
>> > if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
>> > + intel_de_write(display, DSCA_RC_BUF_THRESH_0,
>> > rc_buf_thresh_dword[0]);
>> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
>> > + intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,
>> > rc_buf_thresh_dword[1]);
>> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
>> > + intel_de_write(display, DSCA_RC_BUF_THRESH_1,
>> > rc_buf_thresh_dword[2]);
>> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
>> > + intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,
>> > rc_buf_thresh_dword[3]);
>> > if (vdsc_instances_per_pipe > 1) {
>> > - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
>> > + intel_de_write(display, DSCC_RC_BUF_THRESH_0,
>> > rc_buf_thresh_dword[0]);
>> > - intel_de_write(dev_priv,
>> DSCC_RC_BUF_THRESH_0_UDW,
>> > + intel_de_write(display,
>> DSCC_RC_BUF_THRESH_0_UDW,
>> > rc_buf_thresh_dword[1]);
>> > - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
>> > + intel_de_write(display, DSCC_RC_BUF_THRESH_1,
>> > rc_buf_thresh_dword[2]);
>> > - intel_de_write(dev_priv,
>> DSCC_RC_BUF_THRESH_1_UDW,
>> > + intel_de_write(display,
>> DSCC_RC_BUF_THRESH_1_UDW,
>> > rc_buf_thresh_dword[3]);
>> > }
>> > } else {
>> > - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
>> > + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),
>> > rc_buf_thresh_dword[0]);
>> > - intel_de_write(dev_priv,
>> ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
>> > + intel_de_write(display,
>> ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
>> > rc_buf_thresh_dword[1]);
>> > - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
>> > + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),
>> > rc_buf_thresh_dword[2]);
>> > - intel_de_write(dev_priv,
>> ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
>> > + intel_de_write(display,
>> ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
>> > rc_buf_thresh_dword[3]);
>> > if (vdsc_instances_per_pipe > 1) {
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> > ICL_DSC1_RC_BUF_THRESH_0(pipe),
>> > rc_buf_thresh_dword[0]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> > ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
>> > rc_buf_thresh_dword[1]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> > ICL_DSC1_RC_BUF_THRESH_1(pipe),
>> > rc_buf_thresh_dword[2]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> > ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
>> > rc_buf_thresh_dword[3]);
>> > }
>> > @@ -601,88 +599,88 @@ static void intel_dsc_pps_configure(const struct
>> intel_crtc_state *crtc_state)
>> > (vdsc_cfg->rc_range_params[i].range_min_qp <<
>> > RC_MIN_QP_SHIFT)) << 16 * (i % 2));
>> > if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
>> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,
>> > rc_range_params_dword[0]);
>> > - intel_de_write(dev_priv,
>> DSCA_RC_RANGE_PARAMETERS_0_UDW,
>> > + intel_de_write(display,
>> DSCA_RC_RANGE_PARAMETERS_0_UDW,
>> > rc_range_params_dword[1]);
>> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
>> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,
>> > rc_range_params_dword[2]);
>> > - intel_de_write(dev_priv,
>> DSCA_RC_RANGE_PARAMETERS_1_UDW,
>> > + intel_de_write(display,
>> DSCA_RC_RANGE_PARAMETERS_1_UDW,
>> > rc_range_params_dword[3]);
>> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
>> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,
>> > rc_range_params_dword[4]);
>> > - intel_de_write(dev_priv,
>> DSCA_RC_RANGE_PARAMETERS_2_UDW,
>> > + intel_de_write(display,
>> DSCA_RC_RANGE_PARAMETERS_2_UDW,
>> > rc_range_params_dword[5]);
>> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
>> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,
>> > rc_range_params_dword[6]);
>> > - intel_de_write(dev_priv,
>> DSCA_RC_RANGE_PARAMETERS_3_UDW,
>> > + intel_de_write(display,
>> DSCA_RC_RANGE_PARAMETERS_3_UDW,
>> > rc_range_params_dword[7]);
>> > if (vdsc_instances_per_pipe > 1) {
>> > - intel_de_write(dev_priv,
>> DSCC_RC_RANGE_PARAMETERS_0,
>> > + intel_de_write(display,
>> DSCC_RC_RANGE_PARAMETERS_0,
>> > rc_range_params_dword[0]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> > DSCC_RC_RANGE_PARAMETERS_0_UDW,
>> > rc_range_params_dword[1]);
>> > - intel_de_write(dev_priv,
>> DSCC_RC_RANGE_PARAMETERS_1,
>> > + intel_de_write(display,
>> DSCC_RC_RANGE_PARAMETERS_1,
>> > rc_range_params_dword[2]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> > DSCC_RC_RANGE_PARAMETERS_1_UDW,
>> > rc_range_params_dword[3]);
>> > - intel_de_write(dev_priv,
>> DSCC_RC_RANGE_PARAMETERS_2,
>> > + intel_de_write(display,
>> DSCC_RC_RANGE_PARAMETERS_2,
>> > rc_range_params_dword[4]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> > DSCC_RC_RANGE_PARAMETERS_2_UDW,
>> > rc_range_params_dword[5]);
>> > - intel_de_write(dev_priv,
>> DSCC_RC_RANGE_PARAMETERS_3,
>> > + intel_de_write(display,
>> DSCC_RC_RANGE_PARAMETERS_3,
>> > rc_range_params_dword[6]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> > DSCC_RC_RANGE_PARAMETERS_3_UDW,
>> > rc_range_params_dword[7]);
>> > }
>> > } else {
>> > - intel_de_write(dev_priv,
>> ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
>> > + intel_de_write(display,
>> ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
>> > rc_range_params_dword[0]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
>> > rc_range_params_dword[1]);
>> > - intel_de_write(dev_priv,
>> ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
>> > + intel_de_write(display,
>> ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
>> > rc_range_params_dword[2]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
>> > rc_range_params_dword[3]);
>> > - intel_de_write(dev_priv,
>> ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
>> > + intel_de_write(display,
>> ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
>> > rc_range_params_dword[4]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
>> > rc_range_params_dword[5]);
>> > - intel_de_write(dev_priv,
>> ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
>> > + intel_de_write(display,
>> ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
>> > rc_range_params_dword[6]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
>> > rc_range_params_dword[7]);
>> > if (vdsc_instances_per_pipe > 1) {
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
>> > rc_range_params_dword[0]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
>> > rc_range_params_dword[1]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
>> > rc_range_params_dword[2]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
>> > rc_range_params_dword[3]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
>> > rc_range_params_dword[4]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
>> > rc_range_params_dword[5]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
>> > rc_range_params_dword[6]);
>> > - intel_de_write(dev_priv,
>> > + intel_de_write(display,
>> >
>> ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
>> > rc_range_params_dword[7]);
>> > }
>> > @@ -746,8 +744,8 @@ static i915_reg_t dss_ctl2_reg(struct intel_crtc
>> > *crtc, enum transcoder cpu_tran
>> >
>> > void intel_uncompressed_joiner_enable(const struct intel_crtc_state
>> > *crtc_state) {
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > u32 dss_ctl1_val = 0;
>> >
>> > if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable)
>> > { @@ -756,14 +754,15 @@ void intel_uncompressed_joiner_enable(const
>> struct intel_crtc_state *crtc_state)
>> > else
>> > dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
>> >
>> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state-
>> >cpu_transcoder), dss_ctl1_val);
>> > + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state-
>> >cpu_transcoder),
>> > + dss_ctl1_val);
>> > }
>> > }
>> >
>> > void intel_dsc_enable(const struct intel_crtc_state *crtc_state) {
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > u32 dss_ctl1_val = 0;
>> > u32 dss_ctl2_val = 0;
>> > int vdsc_instances_per_pipe =
>> > intel_dsc_get_vdsc_per_pipe(crtc_state);
>> > @@ -796,28 +795,27 @@ void intel_dsc_enable(const struct intel_crtc_state
>> *crtc_state)
>> > if (intel_crtc_is_bigjoiner_primary(crtc_state))
>> > dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
>> > }
>> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state-
>> >cpu_transcoder), dss_ctl1_val);
>> > - intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state-
>> >cpu_transcoder), dss_ctl2_val);
>> > + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
>> dss_ctl1_val);
>> > + intel_de_write(display, dss_ctl2_reg(crtc,
>> > +crtc_state->cpu_transcoder), dss_ctl2_val);
>> > }
>> >
>> > void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>> > {
>> > + struct intel_display *display = to_intel_display(old_crtc_state);
>> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >
>> > /* Disable only if either of them is enabled */
>> > if (old_crtc_state->dsc.compression_enable ||
>> > old_crtc_state->joiner_pipes) {
>> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state-
>> >cpu_transcoder), 0);
>> > - intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state-
>> >cpu_transcoder), 0);
>> > + intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state-
>> >cpu_transcoder), 0);
>> > + intel_de_write(display, dss_ctl2_reg(crtc,
>> > +old_crtc_state->cpu_transcoder), 0);
>> > }
>> > }
>> >
>> > static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
>> > bool *all_equal)
>> > {
>> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > i915_reg_t dsc_reg[3];
>> > int i, vdsc_per_pipe, dsc_reg_num;
>> > u32 val;
>> > @@ -825,16 +823,16 @@ static u32 intel_dsc_pps_read(struct
>> intel_crtc_state *crtc_state, int pps,
>> > vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
>> > dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
>> >
>> > - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
>> > + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
>> >
>> > intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
>> >
>> > *all_equal = true;
>> >
>> > - val = intel_de_read(i915, dsc_reg[0]);
>> > + val = intel_de_read(display, dsc_reg[0]);
>> >
>> > for (i = 1; i < dsc_reg_num; i++) {
>> > - if (intel_de_read(i915, dsc_reg[i]) != val) {
>> > + if (intel_de_read(display, dsc_reg[i]) != val) {
>> > *all_equal = false;
>> > break;
>> > }
>> > @@ -845,22 +843,20 @@ static u32 intel_dsc_pps_read(struct
>> > intel_crtc_state *crtc_state, int pps,
>> >
>> > static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state
>> > *crtc_state, int pps) {
>> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > u32 val;
>> > bool all_equal;
>> >
>> > val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
>> > - drm_WARN_ON(&i915->drm, !all_equal);
>> > + drm_WARN_ON(display->drm, !all_equal);
>> >
>> > return val;
>> > }
>> >
>> > static void intel_dsc_get_pps_config(struct intel_crtc_state
>> > *crtc_state) {
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > int num_vdsc_instances =
>> intel_dsc_get_num_vdsc_instances(crtc_state);
>> > u32 pps_temp;
>> >
>> > @@ -946,7 +942,7 @@ static void intel_dsc_get_pps_config(struct
>> > intel_crtc_state *crtc_state)
>> >
>> > vdsc_cfg->slice_chunk_size =
>> > REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
>> >
>> > - if (DISPLAY_VER(i915) >= 14) {
>> > + if (DISPLAY_VER(display) >= 14) {
>> > /* PPS 17 */
>> > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
>> >
>> > @@ -964,7 +960,6 @@ void intel_dsc_get_config(struct intel_crtc_state
>> > *crtc_state) {
>> > struct intel_display *display = to_intel_display(crtc_state);
>> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> > enum intel_display_power_domain power_domain;
>> > intel_wakeref_t wakeref;
>> > @@ -979,8 +974,8 @@ void intel_dsc_get_config(struct intel_crtc_state
>> *crtc_state)
>> > if (!wakeref)
>> > return;
>> >
>> > - dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
>> > - dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
>> > + dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
>> > + dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc,
>> > +cpu_transcoder));
>> >
>> > crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
>> > if (!crtc_state->dsc.compression_enable)
>> > @@ -1020,8 +1015,7 @@ void intel_vdsc_state_dump(struct drm_printer
>> > *p, int indent,
>> >
>> > int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>> > {
>> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct intel_display *display = to_intel_display(crtc);
>> > + struct intel_display *display = to_intel_display(crtc_state);
>> > int num_vdsc_instances =
>> intel_dsc_get_num_vdsc_instances(crtc_state);
>> > int min_cdclk;
>>
>> --
>> Jani Nikula, Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ i915.CI.Full: failure for drm/i915/vdsc: intel_display conversions
2025-02-27 11:22 [PATCH] drm/i915/vdsc: intel_display conversions Suraj Kandpal
2025-02-27 12:17 ` Jani Nikula
2025-02-27 12:57 ` ✓ i915.CI.BAT: success for " Patchwork
@ 2025-02-27 23:25 ` Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2025-02-27 23:25 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 101686 bytes --]
== Series Details ==
Series: drm/i915/vdsc: intel_display conversions
URL : https://patchwork.freedesktop.org/series/145570/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16193_full -> Patchwork_145570v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_145570v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_145570v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_145570v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-vga1:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-snb7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-vga1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-vga1.html
Known issues
------------
Here are the changes found in Patchwork_145570v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-cold-reset-rebind:
- shard-tglu: NOTRUN -> [SKIP][3] ([i915#11078])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@all-busy-check-all:
- shard-dg2-9: NOTRUN -> [SKIP][4] ([i915#8414]) +1 other test skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@drm_fdinfo@all-busy-check-all.html
* igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][5] ([i915#8414]) +6 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@drm_fdinfo@busy-check-all@bcs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#8414]) +6 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@drm_fdinfo@most-busy-idle-check-all@ccs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#8414]) +10 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@drm_fdinfo@most-busy-idle-check-all@vecs1.html
* igt@gem_ccs@block-copy-compressed:
- shard-snb: NOTRUN -> [SKIP][8] +60 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb1/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@large-ctrl-surf-copy:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#13008])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_ccs@large-ctrl-surf-copy.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg2-9: NOTRUN -> [SKIP][10] ([i915#7697])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#7697])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@gem_close_race@multigpu-basic-threads.html
- shard-tglu-1: NOTRUN -> [SKIP][12] ([i915#7697])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@gem_close_race@multigpu-basic-threads.html
- shard-dg1: NOTRUN -> [SKIP][13] ([i915#7697])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-tglu: NOTRUN -> [SKIP][14] ([i915#6335])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][15] ([i915#1099]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb1/igt@gem_ctx_persistence@engines-queued.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#5882]) +7 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@gem_ctx_persistence@saturated-hostile-nopreempt.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0:
- shard-mtlp: NOTRUN -> [SKIP][17] ([i915#5882]) +6 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#280]) +2 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@gem_ctx_sseu@invalid-sseu.html
- shard-tglu: NOTRUN -> [SKIP][19] ([i915#280])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@hibernate:
- shard-tglu: NOTRUN -> [ABORT][20] ([i915#7975])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@gem_eio@hibernate.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][21] -> [FAIL][22] ([i915#12543] / [i915#5784])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-18/igt@gem_eio@reset-stress.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-17/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-semaphore:
- shard-dg1: NOTRUN -> [SKIP][23] ([i915#4812])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@gem_exec_balancer@bonded-semaphore.html
- shard-dg2-9: NOTRUN -> [SKIP][24] ([i915#4812])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_exec_balancer@bonded-semaphore.html
* igt@gem_exec_balancer@noheartbeat:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#8555])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@gem_exec_balancer@noheartbeat.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-tglu-1: NOTRUN -> [SKIP][26] ([i915#4525])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_capture@capture-invisible:
- shard-dg2-9: NOTRUN -> [SKIP][27] ([i915#6334]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_capture@capture@vecs0-lmem0:
- shard-dg2: NOTRUN -> [FAIL][28] ([i915#11965]) +4 other tests fail
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@gem_exec_capture@capture@vecs0-lmem0.html
* igt@gem_exec_endless@dispatch:
- shard-glk: [PASS][29] -> [TIMEOUT][30] ([i915#3778]) +1 other test timeout
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-glk9/igt@gem_exec_endless@dispatch.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-glk2/igt@gem_exec_endless@dispatch.html
* igt@gem_exec_fence@submit:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#4812])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@gem_exec_fence@submit.html
* igt@gem_exec_flush@basic-uc-prw-default:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#3539])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@gem_exec_flush@basic-uc-prw-default.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg1: NOTRUN -> [SKIP][33] ([i915#3539] / [i915#4852])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_flush@basic-wb-ro-before-default:
- shard-dg2-9: NOTRUN -> [SKIP][34] ([i915#3539] / [i915#4852]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_exec_flush@basic-wb-ro-before-default.html
* igt@gem_exec_reloc@basic-cpu-read:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3281]) +8 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@gem_exec_reloc@basic-cpu-read.html
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][36] ([i915#3281]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
* igt@gem_exec_reloc@basic-gtt-read:
- shard-dg2-9: NOTRUN -> [SKIP][37] ([i915#3281]) +5 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_exec_reloc@basic-gtt-read.html
* igt@gem_exec_reloc@basic-write-read:
- shard-rkl: NOTRUN -> [SKIP][38] ([i915#3281]) +2 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@gem_exec_reloc@basic-write-read.html
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#3281]) +3 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_exec_schedule@semaphore-power:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4537] / [i915#4812])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s3-devices:
- shard-dg1: [PASS][41] -> [DMESG-WARN][42] ([i915#4423]) +3 other tests dmesg-warn
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-14/igt@gem_exec_suspend@basic-s3-devices.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-18/igt@gem_exec_suspend@basic-s3-devices.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#4860])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@gem_fence_thrash@bo-write-verify-x.html
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#4860])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-dg2-9: NOTRUN -> [SKIP][45] ([i915#4860]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_fenced_exec_thrash@2-spare-fences.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][46] ([i915#4613]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglu: NOTRUN -> [SKIP][47] ([i915#4613]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@random-engines:
- shard-mtlp: NOTRUN -> [SKIP][48] ([i915#4613])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_lmem_swapping@random-engines.html
* igt@gem_madvise@dontneed-before-pwrite:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#3282]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@gem_madvise@dontneed-before-pwrite.html
- shard-dg1: NOTRUN -> [SKIP][50] ([i915#3282])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gem_madvise@dontneed-before-pwrite.html
* igt@gem_media_vme:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#284])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_media_vme.html
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#284])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@gem_media_vme.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#4077]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_mmap_gtt@basic-read-write-distinct.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-dg2-9: NOTRUN -> [SKIP][54] ([i915#4077]) +3 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@gem_mmap_gtt@hang:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#4077]) +7 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@gem_mmap_gtt@hang.html
* igt@gem_mmap_wc@close:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#4083]) +5 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@gem_mmap_wc@close.html
* igt@gem_mmap_wc@read-write-distinct:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#4083])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_mmap_wc@read-write-distinct.html
* igt@gem_mmap_wc@write:
- shard-dg2-9: NOTRUN -> [SKIP][58] ([i915#4083]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_mmap_wc@write.html
* igt@gem_mmap_wc@write-read-distinct:
- shard-dg1: NOTRUN -> [SKIP][59] ([i915#4083]) +2 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gem_mmap_wc@write-read-distinct.html
* igt@gem_partial_pwrite_pread@write:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#3282]) +5 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@gem_partial_pwrite_pread@write.html
* igt@gem_partial_pwrite_pread@write-uncached:
- shard-dg2-9: NOTRUN -> [SKIP][61] ([i915#3282]) +3 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_partial_pwrite_pread@write-uncached.html
* igt@gem_pread@exhaustion:
- shard-tglu-1: NOTRUN -> [WARN][62] ([i915#2658])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@gem_pread@exhaustion.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-dg2-9: NOTRUN -> [SKIP][63] ([i915#4270])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#4270]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-rkl: NOTRUN -> [TIMEOUT][65] ([i915#12917] / [i915#12964])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@gem_pxp@verify-pxp-stale-buf-execution.html
- shard-dg1: NOTRUN -> [SKIP][66] ([i915#4270])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][67] ([i915#5190] / [i915#8428]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#5190] / [i915#8428]) +4 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#8428])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@gem_softpin@evict-snoop:
- shard-dg2-9: NOTRUN -> [SKIP][70] ([i915#4885])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gem_softpin@evict-snoop.html
* igt@gem_tiled_pread_basic:
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#4079])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gem_tiled_pread_basic.html
* igt@gem_tiled_pread_pwrite:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#4079])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@gem_tiled_pread_pwrite.html
* igt@gem_unfence_active_buffers:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#4879])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_unfence_active_buffers.html
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#4879])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@access-control:
- shard-mtlp: NOTRUN -> [SKIP][75] ([i915#3297])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_userptr_blits@access-control.html
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#3297]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#3297] / [i915#4880]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#3297]) +2 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-after-close.html
- shard-tglu-1: NOTRUN -> [SKIP][79] ([i915#3297]) +2 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@gem_userptr_blits@unsync-unmap-after-close.html
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#3297]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen3_render_tiledx_blits:
- shard-dg2: NOTRUN -> [SKIP][81] +14 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@gen3_render_tiledx_blits.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#2856]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@bb-secure:
- shard-tglu: NOTRUN -> [SKIP][83] ([i915#2527] / [i915#2856]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@bb-start-param:
- shard-dg2-9: NOTRUN -> [SKIP][84] ([i915#2856])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@gen9_exec_parse@bb-start-param.html
* igt@gen9_exec_parse@valid-registers:
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#2527])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@gen9_exec_parse@valid-registers.html
- shard-tglu-1: NOTRUN -> [SKIP][86] ([i915#2527] / [i915#2856]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@gen9_exec_parse@valid-registers.html
- shard-dg1: NOTRUN -> [SKIP][87] ([i915#2527]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@gen9_exec_parse@valid-registers.html
* igt@i915_fb_tiling@basic-x-tiling:
- shard-dg2-9: NOTRUN -> [SKIP][88] ([i915#13786])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@i915_fb_tiling@basic-x-tiling.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][89] -> [ABORT][90] ([i915#10887] / [i915#9820])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-tglu: NOTRUN -> [SKIP][91] ([i915#8399])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-tglu-1: NOTRUN -> [SKIP][92] ([i915#8399])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#11681] / [i915#6621])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-dg2-9: NOTRUN -> [SKIP][94] ([i915#11681] / [i915#6621])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@i915_pm_rps@min-max-config-loaded.html
* igt@i915_selftest@mock:
- shard-snb: NOTRUN -> [DMESG-WARN][95] ([i915#9311]) +1 other test dmesg-warn
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb1/igt@i915_selftest@mock.html
* igt@intel_hwmon@hwmon-write:
- shard-tglu-1: NOTRUN -> [SKIP][96] ([i915#7707])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg2-9: NOTRUN -> [SKIP][97] ([i915#4212]) +1 other test skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_addfb_basic@basic-x-tiled-legacy.html
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#4212])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#4212])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-tglu-1: NOTRUN -> [SKIP][100] ([i915#12454] / [i915#12712])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@alternate-sync-async-flip-atomic:
- shard-tglu: [PASS][101] -> [FAIL][102] ([i915#10991] / [i915#13320])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-tglu-7/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-4/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
* igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][103] -> [FAIL][104] ([i915#10991])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-tglu-7/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-4/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-tglu: NOTRUN -> [SKIP][105] ([i915#8709]) +3 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#8709]) +1 other test skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#8709]) +7 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_async_flips@invalid-async-flip:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#12967] / [i915#6228])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#9531])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#1769] / [i915#3555])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-dg1: NOTRUN -> [SKIP][111] ([i915#5286])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglu-1: NOTRUN -> [SKIP][112] ([i915#5286]) +3 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
- shard-dg1: NOTRUN -> [SKIP][113] ([i915#4538] / [i915#5286])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
- shard-rkl: NOTRUN -> [SKIP][114] ([i915#5286])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][115] ([i915#5286]) +2 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][116] +2 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-dg2-9: NOTRUN -> [SKIP][117] +5 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-0:
- shard-dg2-9: NOTRUN -> [SKIP][118] ([i915#4538] / [i915#5190]) +3 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#4538] / [i915#5190]) +9 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#5190]) +1 other test skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][121] +2 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
- shard-dg1: NOTRUN -> [SKIP][122] ([i915#4538]) +1 other test skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-dg2-9: NOTRUN -> [SKIP][123] ([i915#5190])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#10307] / [i915#10434] / [i915#6095]) +5 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#10307] / [i915#6095]) +155 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][126] ([i915#10307] / [i915#6095]) +19 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#6095]) +44 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][128] ([i915#12313])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][129] ([i915#6095]) +44 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][130] ([i915#6095]) +9 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][131] ([i915#6095]) +68 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#6095]) +15 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#6095]) +124 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-13/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][134] ([i915#12313])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-mtlp: NOTRUN -> [SKIP][135] ([i915#12313])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#12313])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-dg2-9: NOTRUN -> [SKIP][137] ([i915#11151] / [i915#7828]) +5 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#11151] / [i915#7828]) +7 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-mtlp: NOTRUN -> [SKIP][139] ([i915#11151] / [i915#7828]) +1 other test skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-tglu-1: NOTRUN -> [SKIP][140] ([i915#11151] / [i915#7828]) +2 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@hdmi-hpd-fast:
- shard-tglu: NOTRUN -> [SKIP][141] ([i915#11151] / [i915#7828]) +2 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-rkl: NOTRUN -> [SKIP][142] ([i915#3116])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_content_protection@dp-mst-type-0.html
- shard-tglu-1: NOTRUN -> [SKIP][143] ([i915#3116] / [i915#3299]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_content_protection@dp-mst-type-0.html
- shard-dg1: NOTRUN -> [SKIP][144] ([i915#3299])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@srm:
- shard-dg2-9: NOTRUN -> [SKIP][145] ([i915#7118])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_content_protection@srm.html
- shard-dg1: NOTRUN -> [SKIP][146] ([i915#7116])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][147] ([i915#1339] / [i915#7173]) +1 other test fail
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#13049])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-dg2-9: NOTRUN -> [SKIP][149] ([i915#3555])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2-9: NOTRUN -> [SKIP][150] ([i915#13049]) +2 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_cursor_crc@cursor-onscreen-512x512.html
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#13049])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-mtlp: NOTRUN -> [SKIP][152] ([i915#3555] / [i915#8814]) +1 other test skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-tglu-1: NOTRUN -> [SKIP][153] ([i915#13049])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-128x42@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [DMESG-WARN][154] ([i915#12964]) +9 other tests dmesg-warn
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-1/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-b-hdmi-a-2.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#13046] / [i915#5354]) +2 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglu-1: NOTRUN -> [SKIP][156] ([i915#4103])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-dg2-9: NOTRUN -> [SKIP][157] ([i915#13046] / [i915#5354]) +1 other test skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#9833])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-tglu-1: NOTRUN -> [SKIP][159] ([i915#9723])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-dg2-9: NOTRUN -> [SKIP][160] ([i915#8588])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-tglu: NOTRUN -> [SKIP][161] ([i915#1769] / [i915#3555] / [i915#3804])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][162] ([i915#3804])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][163] ([i915#3804])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-tglu-1: NOTRUN -> [SKIP][164] ([i915#3840])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#3840])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
- shard-mtlp: NOTRUN -> [SKIP][166] ([i915#3840])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-formats:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#3840])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#3840] / [i915#9053])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
- shard-dg2-9: NOTRUN -> [SKIP][169] ([i915#9934]) +1 other test skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-tglu: NOTRUN -> [SKIP][170] ([i915#3637]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-snb: [PASS][171] -> [FAIL][172] ([i915#11832] / [i915#13743])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1:
- shard-snb: [PASS][173] -> [FAIL][174] ([i915#11832])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#9934]) +8 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#3637]) +1 other test skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-tglu-1: NOTRUN -> [SKIP][177] ([i915#3637]) +5 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_flip@2x-flip-vs-fences.html
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#8381])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_flip@2x-flip-vs-fences.html
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#9934])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-snb: [PASS][180] -> [FAIL][181] ([i915#13743])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-snb7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
- shard-mtlp: [PASS][182] -> [FAIL][183] ([i915#13743]) +1 other test fail
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-mtlp-3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][184] ([i915#2672] / [i915#3555]) +1 other test skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
- shard-tglu-1: NOTRUN -> [SKIP][185] ([i915#2672] / [i915#3555]) +1 other test skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][186] ([i915#2672]) +1 other test skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#2672]) +3 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][188] ([i915#2587] / [i915#2672]) +1 other test skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][189] ([i915#2587] / [i915#2672] / [i915#3555])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][190] ([i915#2587] / [i915#2672]) +2 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-dg2-9: NOTRUN -> [SKIP][191] ([i915#2672] / [i915#3555] / [i915#5190])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][192] ([i915#2672]) +1 other test skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-tglu: NOTRUN -> [SKIP][193] ([i915#2672] / [i915#3555]) +1 other test skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#2672] / [i915#3555]) +2 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
- shard-dg2-9: NOTRUN -> [SKIP][195] ([i915#2672] / [i915#3555])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][196] ([i915#2587] / [i915#2672]) +2 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#2672] / [i915#3555]) +5 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
- shard-dg2: [PASS][198] -> [FAIL][199] ([i915#6880])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][200] ([i915#8708]) +5 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#8708]) +13 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
- shard-dg1: NOTRUN -> [SKIP][202] +10 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-tglu-1: NOTRUN -> [SKIP][203] +58 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-dg2-9: NOTRUN -> [SKIP][204] ([i915#8708]) +13 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][205] ([i915#1825]) +7 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-dg2-9: NOTRUN -> [SKIP][206] ([i915#3458]) +3 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][207] ([i915#8708]) +2 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][208] +46 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-mtlp: NOTRUN -> [SKIP][209] ([i915#1825]) +3 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][210] ([i915#3023]) +3 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
- shard-dg1: NOTRUN -> [SKIP][211] ([i915#3458]) +2 other tests skip
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2-9: NOTRUN -> [SKIP][212] ([i915#5354]) +13 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#5354]) +26 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#3458]) +13 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2: NOTRUN -> [SKIP][215] ([i915#13331])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@static-toggle:
- shard-tglu-1: NOTRUN -> [SKIP][216] ([i915#3555] / [i915#8228])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2-9: NOTRUN -> [SKIP][217] ([i915#3555] / [i915#8228]) +1 other test skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@basic-big-joiner:
- shard-dg2-9: NOTRUN -> [SKIP][218] ([i915#10656])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][219] ([i915#12394])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-tglu: NOTRUN -> [SKIP][220] ([i915#13688])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-tglu: NOTRUN -> [SKIP][221] ([i915#10656])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_joiner@invalid-modeset-big-joiner.html
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#10656])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-tglu: NOTRUN -> [SKIP][223] ([i915#1839]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@legacy:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#6301])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_panel_fitting@legacy.html
* igt@kms_plane@plane-panning-top-left@pipe-a:
- shard-rkl: [PASS][225] -> [DMESG-WARN][226] ([i915#12964]) +2 other tests dmesg-warn
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-2/igt@kms_plane@plane-panning-top-left@pipe-a.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-5/igt@kms_plane@plane-panning-top-left@pipe-a.html
* igt@kms_plane_multiple@tiling-y:
- shard-dg2-9: NOTRUN -> [SKIP][227] ([i915#8806])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c:
- shard-rkl: NOTRUN -> [SKIP][228] ([i915#12247]) +3 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a:
- shard-mtlp: NOTRUN -> [SKIP][229] ([i915#12247]) +4 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
- shard-dg2: NOTRUN -> [SKIP][230] ([i915#12247] / [i915#9423])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d:
- shard-dg2: NOTRUN -> [SKIP][231] ([i915#12247]) +3 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-rkl: NOTRUN -> [SKIP][232] ([i915#12247] / [i915#6953])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
- shard-tglu-1: NOTRUN -> [SKIP][233] ([i915#12247] / [i915#6953])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
- shard-dg1: NOTRUN -> [SKIP][234] ([i915#12247] / [i915#6953])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b:
- shard-dg1: NOTRUN -> [SKIP][235] ([i915#12247]) +3 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c:
- shard-tglu-1: NOTRUN -> [SKIP][236] ([i915#12247]) +3 other tests skip
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c.html
* igt@kms_pm_backlight@fade:
- shard-dg1: NOTRUN -> [SKIP][237] ([i915#5354])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_pm_backlight@fade.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-tglu: NOTRUN -> [SKIP][238] ([i915#9812])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-tglu-1: NOTRUN -> [SKIP][239] ([i915#9812])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2: NOTRUN -> [SKIP][240] ([i915#9685])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_pm_dc@dc3co-vpb-simulation.html
- shard-tglu: NOTRUN -> [SKIP][241] ([i915#9685])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-tglu: NOTRUN -> [SKIP][242] ([i915#8430])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg2-9: NOTRUN -> [SKIP][243] ([i915#9519])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [PASS][244] -> [SKIP][245] ([i915#9519])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#9519]) +1 other test skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-mtlp: NOTRUN -> [SKIP][247] ([i915#9519])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@pm-caching:
- shard-dg1: NOTRUN -> [SKIP][248] ([i915#4077]) +2 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_pm_rpm@pm-caching.html
* igt@kms_prime@d3hot:
- shard-tglu-1: NOTRUN -> [SKIP][249] ([i915#6524])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
- shard-mtlp: NOTRUN -> [SKIP][250] ([i915#12316]) +1 other test skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
- shard-dg2-9: NOTRUN -> [SKIP][251] ([i915#11520]) +2 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
- shard-snb: NOTRUN -> [SKIP][252] ([i915#11520]) +2 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb1/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
- shard-tglu: NOTRUN -> [SKIP][253] ([i915#11520]) +5 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
- shard-dg2: NOTRUN -> [SKIP][254] ([i915#11520]) +5 other tests skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][255] ([i915#11520]) +1 other test skip
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
- shard-tglu-1: NOTRUN -> [SKIP][256] ([i915#11520]) +5 other tests skip
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
- shard-dg1: NOTRUN -> [SKIP][257] ([i915#11520]) +2 other tests skip
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][258] ([i915#9683]) +1 other test skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-cursor-plane-onoff:
- shard-tglu-1: NOTRUN -> [SKIP][259] ([i915#9732]) +13 other tests skip
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_psr@fbc-pr-cursor-plane-onoff.html
* igt@kms_psr@fbc-psr-cursor-render:
- shard-tglu: NOTRUN -> [SKIP][260] ([i915#9732]) +10 other tests skip
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_psr@fbc-psr-cursor-render.html
* igt@kms_psr@fbc-psr2-suspend:
- shard-mtlp: NOTRUN -> [SKIP][261] ([i915#9688]) +2 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_psr@fbc-psr2-suspend.html
* igt@kms_psr@pr-sprite-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][262] ([i915#1072] / [i915#9732]) +3 other tests skip
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_psr@pr-sprite-mmap-gtt.html
- shard-dg1: NOTRUN -> [SKIP][263] ([i915#1072] / [i915#9732]) +7 other tests skip
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_psr@pr-sprite-mmap-gtt.html
* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-dg2-9: NOTRUN -> [SKIP][264] ([i915#1072] / [i915#9732]) +10 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_psr@psr-cursor-mmap-cpu.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][265] ([i915#1072] / [i915#9732]) +19 other tests skip
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_psr@psr2-primary-mmap-gtt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][266] ([i915#4077] / [i915#9688]) +1 other test skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_psr@psr2-primary-mmap-gtt@edp-1.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][267] ([i915#12755] / [i915#5190])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2-9: NOTRUN -> [SKIP][268] ([i915#12755] / [i915#5190])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglu: NOTRUN -> [SKIP][269] ([i915#5289])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-rkl: NOTRUN -> [SKIP][270] ([i915#5289])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
- shard-tglu-1: NOTRUN -> [SKIP][271] ([i915#5289])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
- shard-dg1: NOTRUN -> [SKIP][272] ([i915#5289])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-tglu: NOTRUN -> [SKIP][273] ([i915#3555]) +3 other tests skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-dg2: NOTRUN -> [SKIP][274] ([i915#3555]) +6 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_selftest@drm_framebuffer:
- shard-rkl: NOTRUN -> [ABORT][275] ([i915#13179]) +1 other test abort
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_selftest@drm_framebuffer.html
- shard-tglu-1: NOTRUN -> [ABORT][276] ([i915#13179]) +1 other test abort
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_selftest@drm_framebuffer.html
- shard-dg1: NOTRUN -> [ABORT][277] ([i915#13179]) +1 other test abort
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_selftest@drm_framebuffer.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-tglu-1: NOTRUN -> [SKIP][278] ([i915#3555]) +3 other tests skip
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_setmode@clone-exclusive-crtc.html
- shard-dg1: NOTRUN -> [SKIP][279] ([i915#3555]) +2 other tests skip
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglu-1: NOTRUN -> [SKIP][280] ([i915#8623])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg2-9: NOTRUN -> [SKIP][281] ([i915#9906])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@flipline:
- shard-rkl: NOTRUN -> [SKIP][282] ([i915#3555]) +1 other test skip
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_vrr@flipline.html
* igt@kms_vrr@lobf:
- shard-dg2-9: NOTRUN -> [SKIP][283] ([i915#11920])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@kms_vrr@lobf.html
- shard-dg1: NOTRUN -> [SKIP][284] ([i915#11920])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@kms_vrr@lobf.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-tglu: NOTRUN -> [SKIP][285] ([i915#9906])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-7/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-tglu-1: NOTRUN -> [SKIP][286] ([i915#9906])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg2: NOTRUN -> [SKIP][287] ([i915#9906]) +2 other tests skip
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output:
- shard-tglu: NOTRUN -> [SKIP][288] ([i915#2437])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-mtlp: NOTRUN -> [SKIP][289] ([i915#2437] / [i915#9412])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@kms_writeback@writeback-pixel-formats.html
- shard-dg2: NOTRUN -> [SKIP][290] ([i915#2437] / [i915#9412])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2-9: NOTRUN -> [SKIP][291] ([i915#2436])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@global-sseu-config-invalid:
- shard-dg2: NOTRUN -> [SKIP][292] ([i915#7387])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@perf@global-sseu-config-invalid.html
* igt@perf_pmu@event-wait:
- shard-mtlp: NOTRUN -> [SKIP][293] ([i915#8807])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@perf_pmu@event-wait.html
* igt@perf_pmu@event-wait@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][294] ([i915#3555] / [i915#8807])
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@perf_pmu@event-wait@rcs0.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2: NOTRUN -> [FAIL][295] ([i915#12549] / [i915#6806]) +1 other test fail
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-7/igt@perf_pmu@frequency@gt0.html
* igt@perf_pmu@invalid-init:
- shard-tglu: NOTRUN -> [FAIL][296] ([i915#13663])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-3/igt@perf_pmu@invalid-init.html
* igt@prime_mmap@test_aperture_limit:
- shard-dg2: NOTRUN -> [WARN][297] ([i915#9351])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@prime_mmap@test_aperture_limit.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: NOTRUN -> [CRASH][298] ([i915#9351])
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][299] ([i915#3291] / [i915#3708])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@prime_vgem@basic-fence-read.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg2: NOTRUN -> [SKIP][300] ([i915#9917]) +1 other test skip
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg2-9: NOTRUN -> [SKIP][301] ([i915#9917])
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-9/igt@sriov_basic@enable-vfs-autoprobe-on.html
- shard-dg1: NOTRUN -> [SKIP][302] ([i915#9917])
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-19/igt@sriov_basic@enable-vfs-autoprobe-on.html
#### Possible fixes ####
* igt@gem_eio@in-flight-1us:
- shard-mtlp: [ABORT][303] ([i915#13193]) -> [PASS][304]
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-mtlp-7/igt@gem_eio@in-flight-1us.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-6/igt@gem_eio@in-flight-1us.html
* igt@gem_exec_schedule@preemptive-hang:
- shard-rkl: [DMESG-WARN][305] ([i915#12964]) -> [PASS][306] +7 other tests pass
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-5/igt@gem_exec_schedule@preemptive-hang.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@gem_exec_schedule@preemptive-hang.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-rkl: [TIMEOUT][307] ([i915#12964]) -> [PASS][308]
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-2/igt@gem_pxp@fail-invalid-protected-context.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-8/igt@gem_pxp@fail-invalid-protected-context.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [ABORT][309] ([i915#9820]) -> [PASS][310]
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg1: [ABORT][311] ([i915#9820]) -> [PASS][312]
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-16/igt@i915_module_load@reload-with-fault-injection.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-16/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0:
- shard-dg1: [FAIL][313] ([i915#3591]) -> [PASS][314] +1 other test pass
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
* igt@i915_suspend@debugfs-reader:
- shard-dg2: [INCOMPLETE][315] ([i915#4817]) -> [PASS][316]
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-11/igt@i915_suspend@debugfs-reader.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-3/igt@i915_suspend@debugfs-reader.html
* igt@kms_async_flips@alternate-sync-async-flip-atomic:
- shard-dg1: [FAIL][317] ([i915#13320]) -> [PASS][318]
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-19/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-13/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
* igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-2:
- shard-rkl: [FAIL][319] ([i915#13566]) -> [PASS][320] +1 other test pass
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-2.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-2.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- shard-glk: [FAIL][321] ([i915#2346]) -> [PASS][322]
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-glk8/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-glk1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-tglu: [FAIL][323] ([i915#13743]) -> [PASS][324] +1 other test pass
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-tglu-7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-tglu-9/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-dg2: [FAIL][325] ([i915#6880]) -> [PASS][326] +3 other tests pass
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-snb: [SKIP][327] -> [PASS][328] +3 other tests pass
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_hdr@static-swap:
- shard-dg2: [SKIP][329] ([i915#3555] / [i915#8228]) -> [PASS][330] +1 other test pass
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-5/igt@kms_hdr@static-swap.html
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_hdr@static-swap.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- shard-dg1: [DMESG-WARN][331] ([i915#4423]) -> [PASS][332] +1 other test pass
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-19/igt@kms_pipe_crc_basic@suspend-read-crc.html
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-13/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [SKIP][333] ([i915#9340]) -> [PASS][334]
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-10/igt@kms_pm_lpsp@kms-lpsp.html
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-8/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: [SKIP][335] ([i915#9519]) -> [PASS][336]
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp-stress.html
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-rkl: [SKIP][337] ([i915#9519]) -> [PASS][338] +2 other tests pass
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-dg1: [FAIL][339] ([i915#9196]) -> [PASS][340]
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-19/igt@kms_universal_plane@cursor-fb-leak.html
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_vrr@negative-basic:
- shard-dg2: [SKIP][341] ([i915#3555] / [i915#9906]) -> [PASS][342]
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-4/igt@kms_vrr@negative-basic.html
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_vrr@negative-basic.html
* igt@perf@polling@0-rcs0:
- shard-rkl: [FAIL][343] ([i915#10538]) -> [PASS][344] +1 other test pass
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-3/igt@perf@polling@0-rcs0.html
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-8/igt@perf@polling@0-rcs0.html
#### Warnings ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][345] ([i915#10131] / [i915#10887] / [i915#9820]) -> [ABORT][346] ([i915#10131] / [i915#9820])
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rpm@gem-evict-pwrite:
- shard-dg1: [SKIP][347] ([i915#4077] / [i915#4423]) -> [SKIP][348] ([i915#4077])
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-12/igt@i915_pm_rpm@gem-evict-pwrite.html
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-15/igt@i915_pm_rpm@gem-evict-pwrite.html
* igt@i915_pm_rpm@gem-execbuf:
- shard-rkl: [SKIP][349] ([i915#13328]) -> [DMESG-WARN][350] ([i915#12964])
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-5/igt@i915_pm_rpm@gem-execbuf.html
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-3/igt@i915_pm_rpm@gem-execbuf.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][351] ([i915#7118] / [i915#9424]) -> [SKIP][352] ([i915#7118] / [i915#7162] / [i915#9424])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-5/igt@kms_content_protection@type1.html
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-10/igt@kms_content_protection@type1.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg1: [SKIP][353] ([i915#9337]) -> [SKIP][354] ([i915#4423] / [i915#9337])
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-14/igt@kms_feature_discovery@dp-mst.html
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-18/igt@kms_feature_discovery@dp-mst.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-dg1: [SKIP][355] ([i915#4423] / [i915#9934]) -> [SKIP][356] ([i915#9934])
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-14/igt@kms_flip@2x-flip-vs-panning.html
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-18/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-dg2: [SKIP][357] ([i915#3458]) -> [SKIP][358] ([i915#10433] / [i915#3458]) +3 other tests skip
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-dg2: [SKIP][359] ([i915#10433] / [i915#3458]) -> [SKIP][360] ([i915#3458])
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg1: [SKIP][361] ([i915#1187] / [i915#12713]) -> [SKIP][362] ([i915#12713])
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-13/igt@kms_hdr@brightness-with-hdr.html
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-12/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][363] ([i915#4070] / [i915#4816]) -> [SKIP][364] ([i915#1839] / [i915#4816])
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][365] ([i915#3361]) -> [SKIP][366] ([i915#4281])
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-3/igt@kms_pm_dc@dc9-dpms.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][367] ([i915#3828]) -> [SKIP][368] ([i915#9340])
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-rkl-7/igt@kms_pm_lpsp@kms-lpsp.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-dg1: [SKIP][369] ([i915#11520]) -> [SKIP][370] ([i915#11520] / [i915#4423])
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-14/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-18/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr@pr-cursor-mmap-gtt:
- shard-dg1: [SKIP][371] ([i915#1072] / [i915#4423] / [i915#9732]) -> [SKIP][372] ([i915#1072] / [i915#9732])
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16193/shard-dg1-12/igt@kms_psr@pr-cursor-mmap-gtt.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/shard-dg1-15/igt@kms_psr@pr-cursor-mmap-gtt.html
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#10991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10991
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11832]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11832
[i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
[i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
[i915#12543]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12543
[i915#12549]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12549
[i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
[i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#12967]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12967
[i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
[i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
[i915#13320]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13320
[i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
[i915#13331]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13331
[i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13663]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13663
[i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
[i915#13743]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13743
[i915#13786]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13786
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6806
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
[i915#8807]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8807
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_16193 -> Patchwork_145570v1
CI-20190529: 20190529
CI_DRM_16193: 1a52d296ec3278de76f33064361b059a152c3fc3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8250: 43a53635da9a5ecb1a9ca189cb15df2c0b78bd38 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_145570v1: 1a52d296ec3278de76f33064361b059a152c3fc3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145570v1/index.html
[-- Attachment #2: Type: text/html, Size: 128352 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/i915/vdsc: intel_display conversions
2025-02-27 18:47 ` Jani Nikula
@ 2025-02-28 1:30 ` Kandpal, Suraj
0 siblings, 0 replies; 7+ messages in thread
From: Kandpal, Suraj @ 2025-02-28 1:30 UTC (permalink / raw)
To: Nikula, Jani, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, February 28, 2025 12:18 AM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915/vdsc: intel_display conversions
>
> On Thu, 27 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Thursday, February 27, 2025 5:47 PM
> >> To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> >> intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> Cc: Kandpal, Suraj <suraj.kandpal@intel.com>
> >> Subject: Re: [PATCH] drm/i915/vdsc: intel_display conversions
> >>
> >> On Thu, 27 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> >> > intel_display conversions for vdsc in an effort to move away from
> >> > drm_i915_private.
> >> > While at it use display->platform.xx.
> >>
> >> Please update with
> >>
> >> -#include "i915_drv.h"
> >> +#include "i915_utils.h"
> >>
> >> and you get
> >>
> >> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> >
> > Thanks for the reviews pushed to drm-intel-next with the above
> > mentioned changes
>
> I didn't really mean you should make the changes while applying.
Ahh ohkay will keep that in mind in the future
Regards,
Suraj Kandpal
>
> BR,
> Jani.
>
>
>
> >
> > Regards,
> > Suraj Kandpal
> >
> >>
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >>
> >> >
> >> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/display/intel_vdsc.c | 180
> >> > +++++++++++-----------
> >> > 1 file changed, 87 insertions(+), 93 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > index 6e7151346382..35d558ca98db 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > @@ -22,14 +22,13 @@
> >> >
> >> > bool intel_dsc_source_support(const struct intel_crtc_state
> >> > *crtc_state) {
> >> > - const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> >
> >> > - if (!HAS_DSC(i915))
> >> > + if (!HAS_DSC(display))
> >> > return false;
> >> >
> >> > - if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
> >> > + if (DISPLAY_VER(display) == 11 && cpu_transcoder ==
> >> > + TRANSCODER_A)
> >> > return false;
> >> >
> >> > return true;
> >> > @@ -37,9 +36,9 @@ bool intel_dsc_source_support(const struct
> >> > intel_crtc_state *crtc_state)
> >> >
> >> > static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder
> >> > cpu_transcoder) {
> >> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > + struct intel_display *display = to_intel_display(crtc);
> >> >
> >> > - if (DISPLAY_VER(i915) >= 12)
> >> > + if (DISPLAY_VER(display) >= 12)
> >> > return true;
> >> >
> >> > if (cpu_transcoder == TRANSCODER_EDP || @@ -48,7 +47,7 @@
> >> > static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder
> cpu_transcoder)
> >> > return false;
> >> >
> >> > /* There's no pipe A DSC engine on ICL */
> >> > - drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
> >> > + drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
> >> >
> >> > return true;
> >> > }
> >> > @@ -262,8 +261,7 @@ static int
> >> > intel_dsc_slice_dimensions_valid(struct
> >> > intel_crtc_state *pipe_config
> >> >
> >> > int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) {
> >> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> >> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > + struct intel_display *display = to_intel_display(pipe_config);
> >> > struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> >> > u16 compressed_bpp = fxp_q4_to_int(pipe_config-
> >> >dsc.compressed_bpp_x16);
> >> > int err;
> >> > @@ -276,7 +274,7 @@ int intel_dsc_compute_params(struct
> >> >intel_crtc_state
> >> *pipe_config)
> >> > err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
> >> >
> >> > if (err) {
> >> > - drm_dbg_kms(&dev_priv->drm, "Slice dimension
> >> requirements not met\n");
> >> > + drm_dbg_kms(display->drm, "Slice dimension requirements
> >> not
> >> > +met\n");
> >> > return err;
> >> > }
> >> >
> >> > @@ -287,7 +285,7 @@ int intel_dsc_compute_params(struct
> >> > intel_crtc_state
> >> *pipe_config)
> >> > vdsc_cfg->convert_rgb = pipe_config->output_format !=
> >> INTEL_OUTPUT_FORMAT_YCBCR420 &&
> >> > pipe_config->output_format !=
> >> INTEL_OUTPUT_FORMAT_YCBCR444;
> >> >
> >> > - if (DISPLAY_VER(dev_priv) >= 14 &&
> >> > + if (DISPLAY_VER(display) >= 14 &&
> >> > pipe_config->output_format ==
> >> INTEL_OUTPUT_FORMAT_YCBCR420)
> >> > vdsc_cfg->native_420 = true;
> >> > /* We do not support YcBCr422 as of now */ @@ -308,7 +306,7 @@
> >> > int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> >> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> >> >
> >> > if (vdsc_cfg->bits_per_component < 8) {
> >> > - drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not
> >> met bpc: %d\n",
> >> > + drm_dbg_kms(display->drm, "DSC bpc requirements not met
> >> bpc: %d\n",
> >> > vdsc_cfg->bits_per_component);
> >> > return -EINVAL;
> >> > }
> >> > @@ -320,7 +318,7 @@ int intel_dsc_compute_params(struct
> >> > intel_crtc_state
> >> *pipe_config)
> >> > * upto uncompressed bpp-1, hence add calculations for all the rc
> >> > * parameters
> >> > */
> >> > - if (DISPLAY_VER(dev_priv) >= 13) {
> >> > + if (DISPLAY_VER(display) >= 13) {
> >> > calculate_rc_params(vdsc_cfg);
> >> > } else {
> >> > if ((compressed_bpp == 8 || @@ -356,7 +354,7 @@ int
> >> > intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> >> > enum intel_display_power_domain intel_dsc_power_domain(struct
> >> > intel_crtc *crtc, enum transcoder
> >> > cpu_transcoder) {
> >> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > + struct intel_display *display = to_intel_display(crtc);
> >> > enum pipe pipe = crtc->pipe;
> >> >
> >> > /*
> >> > @@ -370,7 +368,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc,
> >> enum transcoder cpu_transcoder)
> >> > * the pipe in use. Hence another reference on the pipe power domain
> >> > * will suffice. (Except no VDSC/joining on ICL pipe A.)
> >> > */
> >> > - if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe ==
> >> PIPE_A)
> >> > + if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&
> >> > + pipe == PIPE_A)
> >> > return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> >> > else if (is_pipe_dsc(crtc, cpu_transcoder))
> >> > return POWER_DOMAIN_PIPE(pipe); @@ -416,26 +415,25 @@
> >> > static void intel_dsc_get_pps_reg(const struct intel_crtc_state
> >> > *crtc_state, int static void intel_dsc_pps_write(const struct
> >> intel_crtc_state *crtc_state,
> >> > int pps, u32 pps_val) {
> >> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > i915_reg_t dsc_reg[3];
> >> > int i, vdsc_per_pipe, dsc_reg_num;
> >> >
> >> > vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> >> > dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
> >> >
> >> > - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
> >> > + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
> >> >
> >> > intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
> >> >
> >> > for (i = 0; i < dsc_reg_num; i++)
> >> > - intel_de_write(i915, dsc_reg[i], pps_val);
> >> > + intel_de_write(display, dsc_reg[i], pps_val);
> >> > }
> >> >
> >> > static void intel_dsc_pps_configure(const struct intel_crtc_state
> >> > *crtc_state) {
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> >> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> > enum pipe pipe = crtc->pipe;
> >> > @@ -529,7 +527,7 @@ static void intel_dsc_pps_configure(const
> >> > struct
> >> intel_crtc_state *crtc_state)
> >> > vdsc_cfg->slice_height);
> >> > intel_dsc_pps_write(crtc_state, 16, pps_val);
> >> >
> >> > - if (DISPLAY_VER(dev_priv) >= 14) {
> >> > + if (DISPLAY_VER(display) >= 14) {
> >> > /* PPS 17 */
> >> > pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg-
> >> >second_line_bpg_offset);
> >> > intel_dsc_pps_write(crtc_state, 17, pps_val); @@
> >> >-547,44
> >> +545,44 @@
> >> > static void intel_dsc_pps_configure(const struct intel_crtc_state
> *crtc_state)
> >> > (u32)(vdsc_cfg->rc_buf_thresh[i] <<
> >> > BITS_PER_BYTE * (i % 4));
> >> > if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> >> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
> >> > + intel_de_write(display, DSCA_RC_BUF_THRESH_0,
> >> > rc_buf_thresh_dword[0]);
> >> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
> >> > + intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,
> >> > rc_buf_thresh_dword[1]);
> >> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
> >> > + intel_de_write(display, DSCA_RC_BUF_THRESH_1,
> >> > rc_buf_thresh_dword[2]);
> >> > - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
> >> > + intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,
> >> > rc_buf_thresh_dword[3]);
> >> > if (vdsc_instances_per_pipe > 1) {
> >> > - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
> >> > + intel_de_write(display, DSCC_RC_BUF_THRESH_0,
> >> > rc_buf_thresh_dword[0]);
> >> > - intel_de_write(dev_priv,
> >> DSCC_RC_BUF_THRESH_0_UDW,
> >> > + intel_de_write(display,
> >> DSCC_RC_BUF_THRESH_0_UDW,
> >> > rc_buf_thresh_dword[1]);
> >> > - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
> >> > + intel_de_write(display, DSCC_RC_BUF_THRESH_1,
> >> > rc_buf_thresh_dword[2]);
> >> > - intel_de_write(dev_priv,
> >> DSCC_RC_BUF_THRESH_1_UDW,
> >> > + intel_de_write(display,
> >> DSCC_RC_BUF_THRESH_1_UDW,
> >> > rc_buf_thresh_dword[3]);
> >> > }
> >> > } else {
> >> > - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
> >> > + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),
> >> > rc_buf_thresh_dword[0]);
> >> > - intel_de_write(dev_priv,
> >> ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> >> > + intel_de_write(display,
> >> ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> >> > rc_buf_thresh_dword[1]);
> >> > - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
> >> > + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),
> >> > rc_buf_thresh_dword[2]);
> >> > - intel_de_write(dev_priv,
> >> ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> >> > + intel_de_write(display,
> >> ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> >> > rc_buf_thresh_dword[3]);
> >> > if (vdsc_instances_per_pipe > 1) {
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> > ICL_DSC1_RC_BUF_THRESH_0(pipe),
> >> > rc_buf_thresh_dword[0]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> > ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
> >> > rc_buf_thresh_dword[1]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> > ICL_DSC1_RC_BUF_THRESH_1(pipe),
> >> > rc_buf_thresh_dword[2]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> > ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
> >> > rc_buf_thresh_dword[3]);
> >> > }
> >> > @@ -601,88 +599,88 @@ static void intel_dsc_pps_configure(const
> >> > struct
> >> intel_crtc_state *crtc_state)
> >> > (vdsc_cfg->rc_range_params[i].range_min_qp <<
> >> > RC_MIN_QP_SHIFT)) << 16 * (i % 2));
> >> > if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> >> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
> >> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,
> >> > rc_range_params_dword[0]);
> >> > - intel_de_write(dev_priv,
> >> DSCA_RC_RANGE_PARAMETERS_0_UDW,
> >> > + intel_de_write(display,
> >> DSCA_RC_RANGE_PARAMETERS_0_UDW,
> >> > rc_range_params_dword[1]);
> >> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
> >> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,
> >> > rc_range_params_dword[2]);
> >> > - intel_de_write(dev_priv,
> >> DSCA_RC_RANGE_PARAMETERS_1_UDW,
> >> > + intel_de_write(display,
> >> DSCA_RC_RANGE_PARAMETERS_1_UDW,
> >> > rc_range_params_dword[3]);
> >> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
> >> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,
> >> > rc_range_params_dword[4]);
> >> > - intel_de_write(dev_priv,
> >> DSCA_RC_RANGE_PARAMETERS_2_UDW,
> >> > + intel_de_write(display,
> >> DSCA_RC_RANGE_PARAMETERS_2_UDW,
> >> > rc_range_params_dword[5]);
> >> > - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
> >> > + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,
> >> > rc_range_params_dword[6]);
> >> > - intel_de_write(dev_priv,
> >> DSCA_RC_RANGE_PARAMETERS_3_UDW,
> >> > + intel_de_write(display,
> >> DSCA_RC_RANGE_PARAMETERS_3_UDW,
> >> > rc_range_params_dword[7]);
> >> > if (vdsc_instances_per_pipe > 1) {
> >> > - intel_de_write(dev_priv,
> >> DSCC_RC_RANGE_PARAMETERS_0,
> >> > + intel_de_write(display,
> >> DSCC_RC_RANGE_PARAMETERS_0,
> >> > rc_range_params_dword[0]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> > DSCC_RC_RANGE_PARAMETERS_0_UDW,
> >> > rc_range_params_dword[1]);
> >> > - intel_de_write(dev_priv,
> >> DSCC_RC_RANGE_PARAMETERS_1,
> >> > + intel_de_write(display,
> >> DSCC_RC_RANGE_PARAMETERS_1,
> >> > rc_range_params_dword[2]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> > DSCC_RC_RANGE_PARAMETERS_1_UDW,
> >> > rc_range_params_dword[3]);
> >> > - intel_de_write(dev_priv,
> >> DSCC_RC_RANGE_PARAMETERS_2,
> >> > + intel_de_write(display,
> >> DSCC_RC_RANGE_PARAMETERS_2,
> >> > rc_range_params_dword[4]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> > DSCC_RC_RANGE_PARAMETERS_2_UDW,
> >> > rc_range_params_dword[5]);
> >> > - intel_de_write(dev_priv,
> >> DSCC_RC_RANGE_PARAMETERS_3,
> >> > + intel_de_write(display,
> >> DSCC_RC_RANGE_PARAMETERS_3,
> >> > rc_range_params_dword[6]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> > DSCC_RC_RANGE_PARAMETERS_3_UDW,
> >> > rc_range_params_dword[7]);
> >> > }
> >> > } else {
> >> > - intel_de_write(dev_priv,
> >> ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> >> > + intel_de_write(display,
> >> ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> >> > rc_range_params_dword[0]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
> >> > rc_range_params_dword[1]);
> >> > - intel_de_write(dev_priv,
> >> ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> >> > + intel_de_write(display,
> >> ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> >> > rc_range_params_dword[2]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
> >> > rc_range_params_dword[3]);
> >> > - intel_de_write(dev_priv,
> >> ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> >> > + intel_de_write(display,
> >> ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> >> > rc_range_params_dword[4]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
> >> > rc_range_params_dword[5]);
> >> > - intel_de_write(dev_priv,
> >> ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> >> > + intel_de_write(display,
> >> ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> >> > rc_range_params_dword[6]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
> >> > rc_range_params_dword[7]);
> >> > if (vdsc_instances_per_pipe > 1) {
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
> >> > rc_range_params_dword[0]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
> >> > rc_range_params_dword[1]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
> >> > rc_range_params_dword[2]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
> >> > rc_range_params_dword[3]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
> >> > rc_range_params_dword[4]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
> >> > rc_range_params_dword[5]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
> >> > rc_range_params_dword[6]);
> >> > - intel_de_write(dev_priv,
> >> > + intel_de_write(display,
> >> >
> >> ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
> >> > rc_range_params_dword[7]);
> >> > }
> >> > @@ -746,8 +744,8 @@ static i915_reg_t dss_ctl2_reg(struct
> >> > intel_crtc *crtc, enum transcoder cpu_tran
> >> >
> >> > void intel_uncompressed_joiner_enable(const struct
> >> > intel_crtc_state
> >> > *crtc_state) {
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > u32 dss_ctl1_val = 0;
> >> >
> >> > if (crtc_state->joiner_pipes &&
> >> > !crtc_state->dsc.compression_enable)
> >> > { @@ -756,14 +754,15 @@ void intel_uncompressed_joiner_enable(const
> >> struct intel_crtc_state *crtc_state)
> >> > else
> >> > dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
> >> >
> >> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state-
> >> >cpu_transcoder), dss_ctl1_val);
> >> > + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state-
> >> >cpu_transcoder),
> >> > + dss_ctl1_val);
> >> > }
> >> > }
> >> >
> >> > void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
> >> > {
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > u32 dss_ctl1_val = 0;
> >> > u32 dss_ctl2_val = 0;
> >> > int vdsc_instances_per_pipe =
> >> > intel_dsc_get_vdsc_per_pipe(crtc_state);
> >> > @@ -796,28 +795,27 @@ void intel_dsc_enable(const struct
> >> > intel_crtc_state
> >> *crtc_state)
> >> > if (intel_crtc_is_bigjoiner_primary(crtc_state))
> >> > dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
> >> > }
> >> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state-
> >> >cpu_transcoder), dss_ctl1_val);
> >> > - intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state-
> >> >cpu_transcoder), dss_ctl2_val);
> >> > + intel_de_write(display, dss_ctl1_reg(crtc,
> >> > + crtc_state->cpu_transcoder),
> >> dss_ctl1_val);
> >> > + intel_de_write(display, dss_ctl2_reg(crtc,
> >> > +crtc_state->cpu_transcoder), dss_ctl2_val);
> >> > }
> >> >
> >> > void intel_dsc_disable(const struct intel_crtc_state
> >> > *old_crtc_state) {
> >> > + struct intel_display *display =
> >> > + to_intel_display(old_crtc_state);
> >> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> >
> >> > /* Disable only if either of them is enabled */
> >> > if (old_crtc_state->dsc.compression_enable ||
> >> > old_crtc_state->joiner_pipes) {
> >> > - intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state-
> >> >cpu_transcoder), 0);
> >> > - intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state-
> >> >cpu_transcoder), 0);
> >> > + intel_de_write(display, dss_ctl1_reg(crtc,
> >> > + old_crtc_state-
> >> >cpu_transcoder), 0);
> >> > + intel_de_write(display, dss_ctl2_reg(crtc,
> >> > +old_crtc_state->cpu_transcoder), 0);
> >> > }
> >> > }
> >> >
> >> > static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
> >> > bool *all_equal) {
> >> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > i915_reg_t dsc_reg[3];
> >> > int i, vdsc_per_pipe, dsc_reg_num;
> >> > u32 val;
> >> > @@ -825,16 +823,16 @@ static u32 intel_dsc_pps_read(struct
> >> intel_crtc_state *crtc_state, int pps,
> >> > vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> >> > dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
> >> >
> >> > - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
> >> > + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
> >> >
> >> > intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
> >> >
> >> > *all_equal = true;
> >> >
> >> > - val = intel_de_read(i915, dsc_reg[0]);
> >> > + val = intel_de_read(display, dsc_reg[0]);
> >> >
> >> > for (i = 1; i < dsc_reg_num; i++) {
> >> > - if (intel_de_read(i915, dsc_reg[i]) != val) {
> >> > + if (intel_de_read(display, dsc_reg[i]) != val) {
> >> > *all_equal = false;
> >> > break;
> >> > }
> >> > @@ -845,22 +843,20 @@ static u32 intel_dsc_pps_read(struct
> >> > intel_crtc_state *crtc_state, int pps,
> >> >
> >> > static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state
> >> > *crtc_state, int pps) {
> >> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > u32 val;
> >> > bool all_equal;
> >> >
> >> > val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
> >> > - drm_WARN_ON(&i915->drm, !all_equal);
> >> > + drm_WARN_ON(display->drm, !all_equal);
> >> >
> >> > return val;
> >> > }
> >> >
> >> > static void intel_dsc_get_pps_config(struct intel_crtc_state
> >> > *crtc_state) {
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> >> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > int num_vdsc_instances =
> >> intel_dsc_get_num_vdsc_instances(crtc_state);
> >> > u32 pps_temp;
> >> >
> >> > @@ -946,7 +942,7 @@ static void intel_dsc_get_pps_config(struct
> >> > intel_crtc_state *crtc_state)
> >> >
> >> > vdsc_cfg->slice_chunk_size =
> >> > REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
> >> >
> >> > - if (DISPLAY_VER(i915) >= 14) {
> >> > + if (DISPLAY_VER(display) >= 14) {
> >> > /* PPS 17 */
> >> > pps_temp = intel_dsc_pps_read_and_verify(crtc_state,
> >> > 17);
> >> >
> >> > @@ -964,7 +960,6 @@ void intel_dsc_get_config(struct
> >> > intel_crtc_state
> >> > *crtc_state) {
> >> > struct intel_display *display = to_intel_display(crtc_state);
> >> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> > enum intel_display_power_domain power_domain;
> >> > intel_wakeref_t wakeref;
> >> > @@ -979,8 +974,8 @@ void intel_dsc_get_config(struct
> >> > intel_crtc_state
> >> *crtc_state)
> >> > if (!wakeref)
> >> > return;
> >> >
> >> > - dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
> >> > - dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
> >> > + dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
> >> > + dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc,
> >> > +cpu_transcoder));
> >> >
> >> > crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
> >> > if (!crtc_state->dsc.compression_enable)
> >> > @@ -1020,8 +1015,7 @@ void intel_vdsc_state_dump(struct drm_printer
> >> > *p, int indent,
> >> >
> >> > int intel_vdsc_min_cdclk(const struct intel_crtc_state
> >> > *crtc_state) {
> >> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > - struct intel_display *display = to_intel_display(crtc);
> >> > + struct intel_display *display = to_intel_display(crtc_state);
> >> > int num_vdsc_instances =
> >> intel_dsc_get_num_vdsc_instances(crtc_state);
> >> > int min_cdclk;
> >>
> >> --
> >> Jani Nikula, Intel
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-02-28 1:31 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-27 11:22 [PATCH] drm/i915/vdsc: intel_display conversions Suraj Kandpal
2025-02-27 12:17 ` Jani Nikula
2025-02-27 16:03 ` Kandpal, Suraj
2025-02-27 18:47 ` Jani Nikula
2025-02-28 1:30 ` Kandpal, Suraj
2025-02-27 12:57 ` ✓ i915.CI.BAT: success for " Patchwork
2025-02-27 23:25 ` ✗ i915.CI.Full: failure " Patchwork
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