intel-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	rodrigo.vivi@intel.com
Subject: Re: [PATCH 0/8] drm/i915 & drm/xe: shared PCI ID macros
Date: Tue, 03 Sep 2024 10:32:03 +0300	[thread overview]
Message-ID: <87o755tcp8.fsf@intel.com> (raw)
In-Reply-To: <bslcjve463mplypyr7logylpnkq3asfbalg2a43h3kl5cckefp@wzjcpnaw26ah>

On Mon, 02 Sep 2024, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Mon, Sep 02, 2024 at 08:13:59PM GMT, Jani Nikula wrote:
>>There's considerable overlap in i915 and xe PCI ID macros, and (as can
>>be seen in this series) they get updated out of sync. With i915 display
>>continuing to use PCI IDs for platforms that i915 core does not support,
>
> humn.. but display is not using a separate device. It's rather the same
> that we bind to the xe driver. Why does i915 need to know the PCI ID?

Because display does its own device identification for display, for
display needs, without depending on either xe or i915 passing along some
data that has to be managed between all three.

>>but xe does, the duplication will just increase. Just use a single file
>>for all of them.
>
> I'd expect PCI IDs to stop being added in one header and start to be
> added in another.

Display could include xe_pciids.h too, and start using the XE_*_IDS()
macros for LNL+, but still the intersection of PCI IDs from both i915
and xe should match.


BR,
Jani.


-- 
Jani Nikula, Intel

  reply	other threads:[~2024-09-03  7:32 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-02 17:13 [PATCH 0/8] drm/i915 & drm/xe: shared PCI ID macros Jani Nikula
2024-09-02 17:14 ` [PATCH 1/8] drm/i915/pciids: use designated initializers in INTEL_VGA_DEVICE() Jani Nikula
2024-09-02 17:14 ` [PATCH 2/8] drm/i915/pciids: separate ARL and MTL PCI IDs Jani Nikula
2024-09-02 17:14 ` [PATCH 3/8] drm/xe/pciids: add some missing ADL-N " Jani Nikula
2024-09-02 17:14 ` [PATCH 4/8] drm/xe/pciids: separate RPL-U and RPL-P " Jani Nikula
2024-09-02 17:14 ` [PATCH 5/8] drm/xe/pciids: separate ARL and MTL " Jani Nikula
2024-09-02 17:14 ` [PATCH 6/8] drm/i915/pciids: add PVC PCI ID macros Jani Nikula
2024-09-02 17:14 ` [PATCH 7/8] drm/intel/pciids: rename i915_pciids.h to just pciids.h Jani Nikula
2024-09-10 18:52   ` Rodrigo Vivi
2024-09-02 17:14 ` [PATCH 8/8] drm/xe: switch to common PCI ID macros Jani Nikula
2024-09-10 18:53   ` Rodrigo Vivi
2024-09-02 18:14 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915 & drm/xe: shared " Patchwork
2024-09-02 18:14 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-09-02 18:33 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-03  2:41 ` [PATCH 0/8] " Lucas De Marchi
2024-09-03  7:32   ` Jani Nikula [this message]
2024-09-10 15:04     ` Lucas De Marchi
2024-09-03 20:39 ` ✓ Fi.CI.IGT: success for " Patchwork
2024-09-04  9:55 ` [PATCH 0/8] " Jani Nikula

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87o755tcp8.fsf@intel.com \
    --to=jani.nikula@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).