[PATCH v3 00/21] Panel replay selective update support

[PATCH v3 00/21] Panel replay selective update support

[Jouni Högander]

This patch set is implementing panel replay selective update support
for Intel hardware.

It is also fixing several exisiting issues in current panel replay implementation:

Several needed functions are not execute for panel replay
Ensure link training follows enabling panel replay on sink side
Do not update phy power state for panel replay.
Do not apply workarounds not applicable for panel replay
Do not write registers/bits not applicable for panel replay

v3:
  - do not disable panel replay by default
  - set has_psr for panel replay as well
  - enable sink before link training
  - do not apply all PSR workarounds for panel replay
  - do not write/read registers/bits not applicable for panel replay
  - use psr bit definitions in granularity configuration as well
  - goto unsupported instead of return when global enabled check fails
  - update module parameter descriptions.
v2:
  - make psr pause/resume to work for panel replay as well

Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>

Jouni Högander (21):
  drm/i915/psr: Add some documentation of variables used in psr code
  drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well
  drm/i915/psr: Intel_psr_pause/resume needs to support panel replay
  drm/i915/psr: Rename intel_psr_enabled
  drm/i915/psr: Do not update phy power state in case of panel replay
  drm/i915/psr: Check possible errors for panel replay as well
  drm/i915/psr: Do not write registers/bits not applicable for panel
    replay
  drm/i915/psr: Unify panel replay enable/disable sink
  drm/i915/psr: Panel replay has to be enabled before link training
  drm/i915/psr: Rename has_psr2 as has_sel_update
  drm/i915/psr: Modify VSC SDP calculation to support panel replay + su
  drm/i915/psr: Rename psr2_enabled as sel_update_enabled
  drm/panelreplay: dpcd register definition for panelreplay SU
  drm/i915/psr: Detect panel replay selective update support
  drm/i915/psr: Modify intel_dp_get_su_granularity to support panel
    replay
  drm/i915/psr: Ensure early transport is not enabled for panel replay
  drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
  drm/i915/psr: Do not apply workarounds in case of panel replay
  drm/i915/psr: Update PSR module parameter descriptions
  drm/i915/psr: Split intel_psr2_config_valid for panel replay
  drm/i915/psr: Add panel replay sel update support to debugfs interface

 .../drm/i915/display/intel_crtc_state_dump.c  |   5 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  11 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  12 +
 .../drm/i915/display/intel_display_params.c   |   5 +-
 .../drm/i915/display/intel_display_types.h    |   6 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  26 +-
 drivers/gpu/drm/i915/display/intel_fbc.c      |   5 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   3 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 375 ++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h      |   7 +-
 include/drm/display/drm_dp.h                  |   6 +
 11 files changed, 324 insertions(+), 137 deletions(-)

-- 
2.34.1

[PATCH v3 01/21] drm/i915/psr: Add some documentation of variables used in psr code

[Jouni Högander]

We are adding more boolean variable into intel_psr and intel_crtc_state
structs. Add some documentation about these for sake of clarity.

v2: Modify has_psr +  has_panel_replay to mean panel replay

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 696d5d32ca9d..b9d2f6ceb568 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -171,6 +171,22 @@
  *
  * The rest of the bits are more self-explanatory and/or
  * irrelevant for normal operation.
+ *
+ * Description of intel_crtc_state variables. has_psr, has_panel_replay and
+ * has_sel_update:
+ *
+ *  has_psr (alone):					PSR1
+ *  has_psr + has_sel_update:				PSR2
+ *  has_psr + has_panel_replay:				Panel Replay
+ *  has_psr + has_panel_replay + has_sel_update:	Panel Replay Selective Update
+ *
+ * Description of some intel_psr varibles. enabled, panel_replay_enabled,
+ * sel_update_enabled
+ *
+ *  enabled (alone):						PSR1
+ *  enabled + sel_update_enabled:				PSR2
+ *  enabled + panel_replay_enabled:				Panel Replay
+ *  enabled + panel_replay_enabled + sel_update_enabled:	Panel Replay SU
  */
 
 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
-- 
2.34.1

RE: [PATCH v3 01/21] drm/i915/psr: Add some documentation of variables used in psr code

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 01/21] drm/i915/psr: Add some documentation of
> variables used in psr code
> 
> We are adding more boolean variable into intel_psr and intel_crtc_state
> structs. Add some documentation about these for sake of clarity.
> 
> v2: Modify has_psr +  has_panel_replay to mean panel replay
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 696d5d32ca9d..b9d2f6ceb568 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -171,6 +171,22 @@
>   *
>   * The rest of the bits are more self-explanatory and/or
>   * irrelevant for normal operation.
> + *
> + * Description of intel_crtc_state variables. has_psr, has_panel_replay
> + and
> + * has_sel_update:
> + *
> + *  has_psr (alone):					PSR1
> + *  has_psr + has_sel_update:				PSR2
> + *  has_psr + has_panel_replay:				Panel Replay
> + *  has_psr + has_panel_replay + has_sel_update:	Panel Replay Selective
> Update
> + *
> + * Description of some intel_psr varibles. enabled,
> + panel_replay_enabled,
> + * sel_update_enabled
> + *
> + *  enabled (alone):						PSR1
> + *  enabled + sel_update_enabled:				PSR2
> + *  enabled + panel_replay_enabled:				Panel Replay
> + *  enabled + panel_replay_enabled + sel_update_enabled:	Panel Replay
> SU
>   */
> 
>  #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> --
> 2.34.1

[PATCH v3 02/21] drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well

[Jouni Högander]

Current code is setting only intel_crtc_state->has_panel_replay in panel
replay case. There are lots of stuff behind intel_crtc_state->has_psr that
is needed for panel replay as well. Instead of converting each check to
has_psr || has_panel_replay set has_psr in case of panel replay as
well. Code can then differentiate between psr and panel replay by using
intel_crtc_state->has_panel_replay.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b9d2f6ceb568..d69fefc2a94d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1409,10 +1409,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 
 	if (CAN_PANEL_REPLAY(intel_dp))
 		crtc_state->has_panel_replay = true;
-	else
-		crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state);
 
-	if (!(crtc_state->has_panel_replay || crtc_state->has_psr))
+	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
+		_psr_compute_config(intel_dp, crtc_state);
+
+	if (!crtc_state->has_psr)
 		return;
 
 	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
@@ -1439,7 +1440,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 		goto unlock;
 
 	if (intel_dp->psr.panel_replay_enabled) {
-		pipe_config->has_panel_replay = true;
+		pipe_config->has_psr = pipe_config->has_panel_replay = true;
 	} else {
 		/*
 		 * Not possible to read EDP_PSR/PSR2_CTL registers as it is
@@ -2352,7 +2353,7 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder;
 
-	if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
+	if (!crtc_state->has_psr)
 		return;
 
 	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
-- 
2.34.1

RE: [PATCH v3 02/21] drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 02/21] drm/i915/psr: Set intel_crtc_state->has_psr on
> panel replay as well
> 
> Current code is setting only intel_crtc_state->has_panel_replay in panel
> replay case. There are lots of stuff behind intel_crtc_state->has_psr that is
> needed for panel replay as well. Instead of converting each check to has_psr
> || has_panel_replay set has_psr in case of panel replay as well. Code can
> then differentiate between psr and panel replay by using intel_crtc_state-
> >has_panel_replay.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b9d2f6ceb568..d69fefc2a94d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1409,10 +1409,11 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> 
>  	if (CAN_PANEL_REPLAY(intel_dp))
>  		crtc_state->has_panel_replay = true;
> -	else
> -		crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
> 
> -	if (!(crtc_state->has_panel_replay || crtc_state->has_psr))
> +	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
> +		_psr_compute_config(intel_dp, crtc_state);
> +
> +	if (!crtc_state->has_psr)
>  		return;
> 
>  	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> @@ -1439,7 +1440,7 @@ void intel_psr_get_config(struct intel_encoder
> *encoder,
>  		goto unlock;
> 
>  	if (intel_dp->psr.panel_replay_enabled) {
> -		pipe_config->has_panel_replay = true;
> +		pipe_config->has_psr = pipe_config->has_panel_replay =
> true;
>  	} else {
>  		/*
>  		 * Not possible to read EDP_PSR/PSR2_CTL registers as it is
> @@ -2352,7 +2353,7 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_encoder *encoder;
> 
> -	if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
> +	if (!crtc_state->has_psr)
>  		return;
> 
>  	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> --
> 2.34.1

[PATCH v3 03/21] drm/i915/psr: Intel_psr_pause/resume needs to support panel replay

[Jouni Högander]

Currently intel_psr_pause and intel_psr_resume do nothing in case of panel
replay. Change them to perform pause and return also in case of panel
replay.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d69fefc2a94d..d11f8ea6e0a9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1847,7 +1847,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_psr *psr = &intel_dp->psr;
 
-	if (!CAN_PSR(intel_dp))
+	if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
 		return;
 
 	mutex_lock(&psr->lock);
@@ -1880,7 +1880,7 @@ void intel_psr_resume(struct intel_dp *intel_dp)
 {
 	struct intel_psr *psr = &intel_dp->psr;
 
-	if (!CAN_PSR(intel_dp))
+	if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
 		return;
 
 	mutex_lock(&psr->lock);
-- 
2.34.1

[PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled

[Jouni Högander]

Intel_psr_enabled is now misleading name as we are using main link on with
panel replay. I.e. link retraining is not controlled by hardware. Rename
intel_psr_enabled as intel_psr_hw_controls_link_retrain.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ab415f41924d..e7cda3162ea2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4951,7 +4951,7 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
 	 * Also when exiting PSR, HW will retrain the link anyways fixing
 	 * any link status error.
 	 */
-	if (intel_psr_enabled(intel_dp))
+	if (intel_psr_hw_controls_link_retrain(intel_dp))
 		return false;
 
 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d11f8ea6e0a9..7b3290f4e0b4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3011,7 +3011,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	mutex_unlock(&psr->lock);
 }
 
-bool intel_psr_enabled(struct intel_dp *intel_dp)
+bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp)
 {
 	bool ret;
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index cde781df84d5..f7c5cc07864f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -45,7 +45,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
 void intel_psr_short_pulse(struct intel_dp *intel_dp);
 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);
-bool intel_psr_enabled(struct intel_dp *intel_dp);
+bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp);
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc);
 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
-- 
2.34.1

RE: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
> 
> Intel_psr_enabled is now misleading name as we are using main link on with
> panel replay. I.e. link retraining is not controlled by hardware. Rename
> intel_psr_enabled as intel_psr_hw_controls_link_retrain.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index ab415f41924d..e7cda3162ea2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4951,7 +4951,7 @@ intel_dp_needs_link_retrain(struct intel_dp
> *intel_dp)
>  	 * Also when exiting PSR, HW will retrain the link anyways fixing
>  	 * any link status error.
>  	 */
> -	if (intel_psr_enabled(intel_dp))
> +	if (intel_psr_hw_controls_link_retrain(intel_dp))
>  		return false;
> 
>  	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux,
> DP_PHY_DPRX, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d11f8ea6e0a9..7b3290f4e0b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3011,7 +3011,7 @@ void intel_psr_short_pulse(struct intel_dp
> *intel_dp)
>  	mutex_unlock(&psr->lock);
>  }
> 
> -bool intel_psr_enabled(struct intel_dp *intel_dp)
> +bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp)

Based on CAN_PSR() check the function will return early and only get executed for psr. No sure still do we need to rename it?

Regards,
Animesh 
>  {
>  	bool ret;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index cde781df84d5..f7c5cc07864f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -45,7 +45,7 @@ void intel_psr_get_config(struct intel_encoder
> *encoder,  void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
> void intel_psr_short_pulse(struct intel_dp *intel_dp);  void
> intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> *new_crtc_state); -bool intel_psr_enabled(struct intel_dp *intel_dp);
> +bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp);
>  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc);
>  void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> *crtc_state);
> --
> 2.34.1

Re: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled

[Hogander, Jouni]

On Fri, 2024-02-02 at 07:34 +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Friday, January 19, 2024 3:40 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> > <jouni.hogander@intel.com>
> > Subject: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
> > 
> > Intel_psr_enabled is now misleading name as we are using main link
> > on with
> > panel replay. I.e. link retraining is not controlled by hardware.
> > Rename
> > intel_psr_enabled as intel_psr_hw_controls_link_retrain.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c  | 2 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
> >  3 files changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index ab415f41924d..e7cda3162ea2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4951,7 +4951,7 @@ intel_dp_needs_link_retrain(struct intel_dp
> > *intel_dp)
> >          * Also when exiting PSR, HW will retrain the link anyways
> > fixing
> >          * any link status error.
> >          */
> > -       if (intel_psr_enabled(intel_dp))
> > +       if (intel_psr_hw_controls_link_retrain(intel_dp))
> >                 return false;
> > 
> >         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux,
> > DP_PHY_DPRX, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index d11f8ea6e0a9..7b3290f4e0b4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -3011,7 +3011,7 @@ void intel_psr_short_pulse(struct intel_dp
> > *intel_dp)
> >         mutex_unlock(&psr->lock);
> >  }
> > 
> > -bool intel_psr_enabled(struct intel_dp *intel_dp)
> > +bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp)
> 
> Based on CAN_PSR() check the function will return early and only get
> executed for psr. No sure still do we need to rename it?

Ok. For me it was just surprice what it does and why this function
exists, thus renaming. Much more descriptive. Also we will soon have
main link off with Panel Replay as well then this is not about having
PSR or Panel Replay enabled, but HW controlling link retraining.

I'm fine with dropping the patch if you have strong opinion on this.

BR,

Jouni Högander

> 
> Regards,
> Animesh 
> >  {
> >         bool ret;
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index cde781df84d5..f7c5cc07864f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -45,7 +45,7 @@ void intel_psr_get_config(struct intel_encoder
> > *encoder,  void intel_psr_irq_handler(struct intel_dp *intel_dp,
> > u32 psr_iir);
> > void intel_psr_short_pulse(struct intel_dp *intel_dp);  void
> > intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> > *new_crtc_state); -bool intel_psr_enabled(struct intel_dp
> > *intel_dp);
> > +bool intel_psr_hw_controls_link_retrain(struct intel_dp
> > *intel_dp);
> >  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> >                                 struct intel_crtc *crtc);
> >  void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state
> > *crtc_state);
> > --
> > 2.34.1
> 

RE: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, February 2, 2024 1:17 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
> 
> On Fri, 2024-02-02 at 07:34 +0000, Manna, Animesh wrote:
> >
> >
> > > -----Original Message-----
> > > From: Hogander, Jouni <jouni.hogander@intel.com>
> > > Sent: Friday, January 19, 2024 3:40 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> > > <jouni.hogander@intel.com>
> > > Subject: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
> > >
> > > Intel_psr_enabled is now misleading name as we are using main link
> > > on with panel replay. I.e. link retraining is not controlled by
> > > hardware.
> > > Rename
> > > intel_psr_enabled as intel_psr_hw_controls_link_retrain.
> > >
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c  | 2 +-
> > > drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
> > >  3 files changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index ab415f41924d..e7cda3162ea2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -4951,7 +4951,7 @@ intel_dp_needs_link_retrain(struct intel_dp
> > > *intel_dp)
> > >          * Also when exiting PSR, HW will retrain the link anyways
> > > fixing
> > >          * any link status error.
> > >          */
> > > -       if (intel_psr_enabled(intel_dp))
> > > +       if (intel_psr_hw_controls_link_retrain(intel_dp))
> > >                 return false;
> > >
> > >         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux,
> > > DP_PHY_DPRX, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index d11f8ea6e0a9..7b3290f4e0b4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -3011,7 +3011,7 @@ void intel_psr_short_pulse(struct intel_dp
> > > *intel_dp)
> > >         mutex_unlock(&psr->lock);
> > >  }
> > >
> > > -bool intel_psr_enabled(struct intel_dp *intel_dp)
> > > +bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp)
> >
> > Based on CAN_PSR() check the function will return early and only get
> > executed for psr. No sure still do we need to rename it?
> 
> Ok. For me it was just surprice what it does and why this function exists, thus
> renaming. Much more descriptive. Also we will soon have main link off with
> Panel Replay as well then this is not about having PSR or Panel Replay
> enabled, but HW controlling link retraining.
> 
> I'm fine with dropping the patch if you have strong opinion on this.

Do not see any value addition, though no strong objection.

Regards,
Animesh
> 
> BR,
> 
> Jouni Högander
> 
> >
> > Regards,
> > Animesh
> > >  {
> > >         bool ret;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index cde781df84d5..f7c5cc07864f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -45,7 +45,7 @@ void intel_psr_get_config(struct intel_encoder
> > > *encoder,  void intel_psr_irq_handler(struct intel_dp *intel_dp,
> > > u32 psr_iir);
> > > void intel_psr_short_pulse(struct intel_dp *intel_dp);  void
> > > intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> > > *new_crtc_state); -bool intel_psr_enabled(struct intel_dp
> > > *intel_dp);
> > > +bool intel_psr_hw_controls_link_retrain(struct intel_dp
> > > *intel_dp);
> > >  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > >                                 struct intel_crtc *crtc);
> > >  void intel_psr2_program_trans_man_trk_ctl(const struct
> > > intel_crtc_state *crtc_state);
> > > --
> > > 2.34.1
> >

Re: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled

[Hogander, Jouni]

On Mon, 2024-02-05 at 04:50 +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Friday, February 2, 2024 1:17 PM
> > To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Subject: Re: [PATCH v3 04/21] drm/i915/psr: Rename
> > intel_psr_enabled
> > 
> > On Fri, 2024-02-02 at 07:34 +0000, Manna, Animesh wrote:
> > > 
> > > 
> > > > -----Original Message-----
> > > > From: Hogander, Jouni <jouni.hogander@intel.com>
> > > > Sent: Friday, January 19, 2024 3:40 PM
> > > > To: intel-gfx@lists.freedesktop.org
> > > > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> > > > <jouni.hogander@intel.com>
> > > > Subject: [PATCH v3 04/21] drm/i915/psr: Rename
> > > > intel_psr_enabled
> > > > 
> > > > Intel_psr_enabled is now misleading name as we are using main
> > > > link
> > > > on with panel replay. I.e. link retraining is not controlled by
> > > > hardware.
> > > > Rename
> > > > intel_psr_enabled as intel_psr_hw_controls_link_retrain.
> > > > 
> > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_dp.c  | 2 +-
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> > > > drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
> > > >  3 files changed, 3 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index ab415f41924d..e7cda3162ea2 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -4951,7 +4951,7 @@ intel_dp_needs_link_retrain(struct
> > > > intel_dp
> > > > *intel_dp)
> > > >          * Also when exiting PSR, HW will retrain the link
> > > > anyways
> > > > fixing
> > > >          * any link status error.
> > > >          */
> > > > -       if (intel_psr_enabled(intel_dp))
> > > > +       if (intel_psr_hw_controls_link_retrain(intel_dp))
> > > >                 return false;
> > > > 
> > > >         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux,
> > > > DP_PHY_DPRX, diff --git
> > > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index d11f8ea6e0a9..7b3290f4e0b4 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -3011,7 +3011,7 @@ void intel_psr_short_pulse(struct
> > > > intel_dp
> > > > *intel_dp)
> > > >         mutex_unlock(&psr->lock);
> > > >  }
> > > > 
> > > > -bool intel_psr_enabled(struct intel_dp *intel_dp)
> > > > +bool intel_psr_hw_controls_link_retrain(struct intel_dp
> > > > *intel_dp)
> > > 
> > > Based on CAN_PSR() check the function will return early and only
> > > get
> > > executed for psr. No sure still do we need to rename it?
> > 
> > Ok. For me it was just surprice what it does and why this function
> > exists, thus
> > renaming. Much more descriptive. Also we will soon have main link
> > off with
> > Panel Replay as well then this is not about having PSR or Panel
> > Replay
> > enabled, but HW controlling link retraining.
> > 
> > I'm fine with dropping the patch if you have strong opinion on
> > this.
> 
> Do not see any value addition, though no strong objection.

I sent updated version of this set. I have addressed some of your
comments there including this on. Can you please recheck my patches.

BR,

Jouni Högander

> 
> Regards,
> Animesh
> > 
> > BR,
> > 
> > Jouni Högander
> > 
> > > 
> > > Regards,
> > > Animesh
> > > >  {
> > > >         bool ret;
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > index cde781df84d5..f7c5cc07864f 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > @@ -45,7 +45,7 @@ void intel_psr_get_config(struct
> > > > intel_encoder
> > > > *encoder,  void intel_psr_irq_handler(struct intel_dp
> > > > *intel_dp,
> > > > u32 psr_iir);
> > > > void intel_psr_short_pulse(struct intel_dp *intel_dp);  void
> > > > intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> > > > *new_crtc_state); -bool intel_psr_enabled(struct intel_dp
> > > > *intel_dp);
> > > > +bool intel_psr_hw_controls_link_retrain(struct intel_dp
> > > > *intel_dp);
> > > >  int intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > *state,
> > > >                                 struct intel_crtc *crtc);
> > > >  void intel_psr2_program_trans_man_trk_ctl(const struct
> > > > intel_crtc_state *crtc_state);
> > > > --
> > > > 2.34.1
> > > 
> 

[PATCH v3 05/21] drm/i915/psr: Do not update phy power state in case of panel replay

[Jouni Högander]

Currently panel replay is supporting only main link on mode -> Do not
update phy power state for panel replay.

Bspec: 53370

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7b3290f4e0b4..893c72ea8cf1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1681,13 +1681,15 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	if (!psr_interrupt_error_check(intel_dp))
 		return;
 
-	if (intel_dp->psr.panel_replay_enabled)
+	if (intel_dp->psr.panel_replay_enabled) {
 		drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
-	else
+	} else {
 		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
 			    intel_dp->psr.psr2_enabled ? "2" : "1");
 
-	intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
+		intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
+	}
+
 	intel_psr_enable_sink(intel_dp);
 	intel_psr_enable_source(intel_dp, crtc_state);
 	intel_dp->psr.enabled = true;
@@ -1794,7 +1796,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 				     CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
 	}
 
-	intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
+	if (!intel_dp->psr.panel_replay_enabled)
+		intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
 
 	/* Disable PSR on Sink */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
-- 
2.34.1

RE: [PATCH v3 05/21] drm/i915/psr: Do not update phy power state in case of panel replay

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 05/21] drm/i915/psr: Do not update phy power state in
> case of panel replay
> 
> Currently panel replay is supporting only main link on mode -> Do not update
> phy power state for panel replay.
> 
> Bspec: 53370
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7b3290f4e0b4..893c72ea8cf1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1681,13 +1681,15 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
>  	if (!psr_interrupt_error_check(intel_dp))
>  		return;
> 
> -	if (intel_dp->psr.panel_replay_enabled)
> +	if (intel_dp->psr.panel_replay_enabled) {
>  		drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
> -	else
> +	} else {
>  		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
>  			    intel_dp->psr.psr2_enabled ? "2" : "1");
> 
> -	intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
> +		intel_snps_phy_update_psr_power_state(dev_priv, phy,
> true);
> +	}
> +
>  	intel_psr_enable_sink(intel_dp);
>  	intel_psr_enable_source(intel_dp, crtc_state);
>  	intel_dp->psr.enabled = true;
> @@ -1794,7 +1796,8 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>  				     CLKGATE_DIS_MISC_DMASC_GATING_DIS,
> 0);
>  	}
> 
> -	intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
> +	if (!intel_dp->psr.panel_replay_enabled)
> +		intel_snps_phy_update_psr_power_state(dev_priv, phy,
> false);
> 
>  	/* Disable PSR on Sink */
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
> --
> 2.34.1

[PATCH v3 06/21] drm/i915/psr: Check possible errors for panel replay as well

[Jouni Högander]

On HPD interrupt we want to check if the reason for HPD was some panel
replay error detected by monitor/panel. This is already done for PSR. We
want to do this for panel replay as well. Modify intel_psr_short_pulse to
support panel replay as well.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 893c72ea8cf1..6d7ef74201d2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2959,6 +2959,13 @@ static void psr_capability_changed_check(struct intel_dp *intel_dp)
 	}
 }
 
+/*
+ * On common bits:
+ * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR
+ * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR
+ * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR
+ * this function is relying on PSR definitions
+ */
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -2968,7 +2975,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
 			  DP_PSR_LINK_CRC_ERROR;
 
-	if (!CAN_PSR(intel_dp))
+	if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
 		return;
 
 	mutex_lock(&psr->lock);
@@ -2982,12 +2989,14 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 		goto exit;
 	}
 
-	if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
+	if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) ||
+	    (error_status & errors)) {
 		intel_psr_disable_locked(intel_dp);
 		psr->sink_not_reliable = true;
 	}
 
-	if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
+	if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR &&
+	    !error_status)
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR sink internal error, disabling PSR\n");
 	if (error_status & DP_PSR_RFB_STORAGE_ERROR)
@@ -3007,8 +3016,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	/* clear status register */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
 
-	psr_alpm_check(intel_dp);
-	psr_capability_changed_check(intel_dp);
+	if (!psr->panel_replay_enabled) {
+		psr_alpm_check(intel_dp);
+		psr_capability_changed_check(intel_dp);
+	}
 
 exit:
 	mutex_unlock(&psr->lock);
-- 
2.34.1

RE: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel replay as well

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel
> replay as well
> 
> On HPD interrupt we want to check if the reason for HPD was some panel
> replay error detected by monitor/panel. This is already done for PSR. We
> want to do this for panel replay as well. Modify intel_psr_short_pulse to
> support panel replay as well.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 21 ++++++++++++++++-----
>  1 file changed, 16 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 893c72ea8cf1..6d7ef74201d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2959,6 +2959,13 @@ static void psr_capability_changed_check(struct
> intel_dp *intel_dp)
>  	}
>  }
> 
> +/*
> + * On common bits:
> + * DP_PSR_RFB_STORAGE_ERROR ==
> DP_PANEL_REPLAY_RFB_STORAGE_ERROR
> + * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR ==
> +DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR
> + * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR
> + * this function is relying on PSR definitions  */
>  void intel_psr_short_pulse(struct intel_dp *intel_dp)  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -
> 2968,7 +2975,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
>  			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
>  			  DP_PSR_LINK_CRC_ERROR;
> 
> -	if (!CAN_PSR(intel_dp))
> +	if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))

I feel here the condition check would be:
	if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
 
>  		return;
> 
>  	mutex_lock(&psr->lock);
> @@ -2982,12 +2989,14 @@ void intel_psr_short_pulse(struct intel_dp
> *intel_dp)
>  		goto exit;
>  	}
> 
> -	if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status &
> errors)) {
> +	if ((!psr->panel_replay_enabled && status ==
> DP_PSR_SINK_INTERNAL_ERROR) ||
> +	    (error_status & errors)) {

This will check only for psr, rt? .. The flag panel_replay_enabled will be true and will not check for error status for panel-replay.

>  		intel_psr_disable_locked(intel_dp);
>  		psr->sink_not_reliable = true;
>  	}
> 
> -	if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
> +	if (!psr->panel_replay_enabled && status ==
> DP_PSR_SINK_INTERNAL_ERROR &&
> +	    !error_status)

Same doubt as above.

Regards,
Animesh

>  		drm_dbg_kms(&dev_priv->drm,
>  			    "PSR sink internal error, disabling PSR\n");
>  	if (error_status & DP_PSR_RFB_STORAGE_ERROR) @@ -3007,8
> +3016,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
>  	/* clear status register */
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS,
> error_status);
> 
> -	psr_alpm_check(intel_dp);
> -	psr_capability_changed_check(intel_dp);
> +	if (!psr->panel_replay_enabled) {
> +		psr_alpm_check(intel_dp);
> +		psr_capability_changed_check(intel_dp);
> +	}
> 
>  exit:
>  	mutex_unlock(&psr->lock);
> --
> 2.34.1

Re: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel replay as well

[Hogander, Jouni]

On Fri, 2024-02-02 at 08:10 +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Friday, January 19, 2024 3:40 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> > <jouni.hogander@intel.com>
> > Subject: [PATCH v3 06/21] drm/i915/psr: Check possible errors for
> > panel
> > replay as well
> > 
> > On HPD interrupt we want to check if the reason for HPD was some
> > panel
> > replay error detected by monitor/panel. This is already done for
> > PSR. We
> > want to do this for panel replay as well. Modify
> > intel_psr_short_pulse to
> > support panel replay as well.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 21 ++++++++++++++++----
> > -
> >  1 file changed, 16 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 893c72ea8cf1..6d7ef74201d2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2959,6 +2959,13 @@ static void
> > psr_capability_changed_check(struct
> > intel_dp *intel_dp)
> >         }
> >  }
> > 
> > +/*
> > + * On common bits:
> > + * DP_PSR_RFB_STORAGE_ERROR ==
> > DP_PANEL_REPLAY_RFB_STORAGE_ERROR
> > + * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR ==
> > +DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR
> > + * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR
> > + * this function is relying on PSR definitions  */
> >  void intel_psr_short_pulse(struct intel_dp *intel_dp)  {
> >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > @@ -
> > 2968,7 +2975,7 @@ void intel_psr_short_pulse(struct intel_dp
> > *intel_dp)
> >                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
> >                           DP_PSR_LINK_CRC_ERROR;
> > 
> > -       if (!CAN_PSR(intel_dp))
> > +       if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
> 
> I feel here the condition check would be:
>         if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))

This is matter of taste. Received some time ago opposing comment. I
don't have strong opinion on this. I.e I can change it.

>  
> >                 return;
> > 
> >         mutex_lock(&psr->lock);
> > @@ -2982,12 +2989,14 @@ void intel_psr_short_pulse(struct intel_dp
> > *intel_dp)
> >                 goto exit;
> >         }
> > 
> > -       if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status &
> > errors)) {
> > +       if ((!psr->panel_replay_enabled && status ==
> > DP_PSR_SINK_INTERNAL_ERROR) ||
> > +           (error_status & errors)) {
> 
> This will check only for psr, rt? .. The flag panel_replay_enabled
> will be true and will not check for error status for panel-replay.

I think DP_PSR_SINK_INTERNAL_ERROR is only in PSR status register.
error_status bits are for both and they are still checked.

> 
> >                 intel_psr_disable_locked(intel_dp);
> >                 psr->sink_not_reliable = true;
> >         }
> > 
> > -       if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
> > +       if (!psr->panel_replay_enabled && status ==
> > DP_PSR_SINK_INTERNAL_ERROR &&
> > +           !error_status)
> 
> Same doubt as above.

DP_PSR_SINK_INTERNAL_ERROR doesn't exist in Panel Replay status
register. I.e. if panel replay is enabled do not check further for
internal error or error status bits.

BR,

Jouni Högander

> 
> Regards,
> Animesh
> 
> >                 drm_dbg_kms(&dev_priv->drm,
> >                             "PSR sink internal error, disabling
> > PSR\n");
> >         if (error_status & DP_PSR_RFB_STORAGE_ERROR) @@ -3007,8
> > +3016,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> >         /* clear status register */
> >         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS,
> > error_status);
> > 
> > -       psr_alpm_check(intel_dp);
> > -       psr_capability_changed_check(intel_dp);
> > +       if (!psr->panel_replay_enabled) {
> > +               psr_alpm_check(intel_dp);
> > +               psr_capability_changed_check(intel_dp);
> > +       }
> > 
> >  exit:
> >         mutex_unlock(&psr->lock);
> > --
> > 2.34.1
> 

RE: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel replay as well

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, February 2, 2024 1:50 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel
> replay as well
> 
> On Fri, 2024-02-02 at 08:10 +0000, Manna, Animesh wrote:
> >
> >
> > > -----Original Message-----
> > > From: Hogander, Jouni <jouni.hogander@intel.com>
> > > Sent: Friday, January 19, 2024 3:40 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> > > <jouni.hogander@intel.com>
> > > Subject: [PATCH v3 06/21] drm/i915/psr: Check possible errors for
> > > panel replay as well
> > >
> > > On HPD interrupt we want to check if the reason for HPD was some
> > > panel replay error detected by monitor/panel. This is already done
> > > for PSR. We want to do this for panel replay as well. Modify
> > > intel_psr_short_pulse to support panel replay as well.
> > >
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 21 ++++++++++++++++----
> > > -
> > >  1 file changed, 16 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 893c72ea8cf1..6d7ef74201d2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -2959,6 +2959,13 @@ static void
> > > psr_capability_changed_check(struct
> > > intel_dp *intel_dp)
> > >         }
> > >  }
> > >
> > > +/*
> > > + * On common bits:
> > > + * DP_PSR_RFB_STORAGE_ERROR ==
> > > DP_PANEL_REPLAY_RFB_STORAGE_ERROR
> > > + * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR ==
> > > +DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR
> > > + * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR
> > > + * this function is relying on PSR definitions  */
> > >  void intel_psr_short_pulse(struct intel_dp *intel_dp)  {
> > >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@
> > > -
> > > 2968,7 +2975,7 @@ void intel_psr_short_pulse(struct intel_dp
> > > *intel_dp)
> > >                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
> > >                           DP_PSR_LINK_CRC_ERROR;
> > >
> > > -       if (!CAN_PSR(intel_dp))
> > > +       if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
> >
> > I feel here the condition check would be:
> >         if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
> 
> This is matter of taste. Received some time ago opposing comment. I don't
> have strong opinion on this. I.e I can change it.
> 
> >
> > >                 return;
> > >
> > >         mutex_lock(&psr->lock);
> > > @@ -2982,12 +2989,14 @@ void intel_psr_short_pulse(struct intel_dp
> > > *intel_dp)
> > >                 goto exit;
> > >         }
> > >
> > > -       if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status &
> > > errors)) {
> > > +       if ((!psr->panel_replay_enabled && status ==
> > > DP_PSR_SINK_INTERNAL_ERROR) ||
> > > +           (error_status & errors)) {
> >
> > This will check only for psr, rt? .. The flag panel_replay_enabled
> > will be true and will not check for error status for panel-replay.
> 
> I think DP_PSR_SINK_INTERNAL_ERROR is only in PSR status register.
> error_status bits are for both and they are still checked.
> 
> >
> > >                 intel_psr_disable_locked(intel_dp);
> > >                 psr->sink_not_reliable = true;
> > >         }
> > >
> > > -       if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
> > > +       if (!psr->panel_replay_enabled && status ==
> > > DP_PSR_SINK_INTERNAL_ERROR &&
> > > +           !error_status)
> >
> > Same doubt as above.
> 
> DP_PSR_SINK_INTERNAL_ERROR doesn't exist in Panel Replay status register.
> I.e. if panel replay is enabled do not check further for internal error or error
> status bits.

Ok. LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> 
> BR,
> 
> Jouni Högander
> 
> >
> > Regards,
> > Animesh
> >
> > >                 drm_dbg_kms(&dev_priv->drm,
> > >                             "PSR sink internal error, disabling
> > > PSR\n");
> > >         if (error_status & DP_PSR_RFB_STORAGE_ERROR) @@ -3007,8
> > > +3016,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> > >         /* clear status register */
> > >         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS,
> > > error_status);
> > >
> > > -       psr_alpm_check(intel_dp);
> > > -       psr_capability_changed_check(intel_dp);
> > > +       if (!psr->panel_replay_enabled) {
> > > +               psr_alpm_check(intel_dp);
> > > +               psr_capability_changed_check(intel_dp);
> > > +       }
> > >
> > >  exit:
> > >         mutex_unlock(&psr->lock);
> > > --
> > > 2.34.1
> >

[PATCH v3 07/21] drm/i915/psr: Do not write registers/bits not applicable for panel replay

[Jouni Högander]

From bspec:

Additional programming considerations (repurposed eDP registers)

mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug]
are used in panel replay mode.

Status register: Only SRD_STATUS[SRD state] field is used in panel replay
mode.

Due to this stop writing and reading registers and bits not used by panel
replay if panel replay is used.

Bspec: 53370

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 6d7ef74201d2..2d5d1c2ce246 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -346,6 +346,9 @@ static void psr_irq_control(struct intel_dp *intel_dp)
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 	u32 mask;
 
+	if (intel_dp->psr.panel_replay_enabled)
+		return;
+
 	mask = psr_irq_psr_error_bit_get(intel_dp);
 	if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
 		mask |= psr_irq_post_exit_bit_get(intel_dp) |
@@ -1559,13 +1562,19 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 	 * mask LPSP to avoid dependency on other drivers that might block
 	 * runtime_pm besides preventing  other hw tracking issues now we
 	 * can rely on frontbuffer tracking.
+	 *
+	 * From bspec: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug]
+	 * are used in panel replay mode.
 	 */
-	mask = EDP_PSR_DEBUG_MASK_MEMUP |
-	       EDP_PSR_DEBUG_MASK_HPD |
-	       EDP_PSR_DEBUG_MASK_LPSP;
+	mask = EDP_PSR_DEBUG_MASK_HPD;
 
-	if (DISPLAY_VER(dev_priv) < 20)
-		mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+	if (!intel_dp->psr.panel_replay_enabled) {
+		mask |= EDP_PSR_DEBUG_MASK_MEMUP |
+			EDP_PSR_DEBUG_MASK_LPSP;
+
+		if (DISPLAY_VER(dev_priv) < 20)
+			mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+	}
 
 	/*
 	 * No separate pipe reg write mask on hsw/bdw, so have to unmask all
@@ -1634,6 +1643,9 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 	u32 val;
 
+	if (intel_dp->psr.panel_replay_enabled)
+		goto no_err;
+
 	/*
 	 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
 	 * will still keep the error set even after the reset done in the
@@ -1651,6 +1663,7 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
 		return false;
 	}
 
+no_err:
 	return true;
 }
 
-- 
2.34.1

RE: [PATCH v3 07/21] drm/i915/psr: Do not write registers/bits not applicable for panel replay

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 07/21] drm/i915/psr: Do not write registers/bits not
> applicable for panel replay
> 
> From bspec:
> 
> Additional programming considerations (repurposed eDP registers)
> 
> mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask
> Hotplug] are used in panel replay mode.
> 
> Status register: Only SRD_STATUS[SRD state] field is used in panel replay
> mode.
> 
> Due to this stop writing and reading registers and bits not used by panel
> replay if panel replay is used.
> 
> Bspec: 53370
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++-----
>  1 file changed, 18 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6d7ef74201d2..2d5d1c2ce246 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -346,6 +346,9 @@ static void psr_irq_control(struct intel_dp *intel_dp)
>  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
>  	u32 mask;
> 
> +	if (intel_dp->psr.panel_replay_enabled)
> +		return;
> +
>  	mask = psr_irq_psr_error_bit_get(intel_dp);
>  	if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
>  		mask |= psr_irq_post_exit_bit_get(intel_dp) | @@ -1559,13
> +1562,19 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  	 * mask LPSP to avoid dependency on other drivers that might block
>  	 * runtime_pm besides preventing  other hw tracking issues now we
>  	 * can rely on frontbuffer tracking.
> +	 *
> +	 * From bspec: Only PSR_MASK[Mask FBC modify] and
> PSR_MASK[Mask Hotplug]
> +	 * are used in panel replay mode.
>  	 */
> -	mask = EDP_PSR_DEBUG_MASK_MEMUP |
> -	       EDP_PSR_DEBUG_MASK_HPD |
> -	       EDP_PSR_DEBUG_MASK_LPSP;
> +	mask = EDP_PSR_DEBUG_MASK_HPD;
> 
> -	if (DISPLAY_VER(dev_priv) < 20)
> -		mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> +	if (!intel_dp->psr.panel_replay_enabled) {
> +		mask |= EDP_PSR_DEBUG_MASK_MEMUP |
> +			EDP_PSR_DEBUG_MASK_LPSP;
> +
> +		if (DISPLAY_VER(dev_priv) < 20)
> +			mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> +	}
> 
>  	/*
>  	 * No separate pipe reg write mask on hsw/bdw, so have to unmask
> all @@ -1634,6 +1643,9 @@ static bool psr_interrupt_error_check(struct
> intel_dp *intel_dp)
>  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
>  	u32 val;
> 
> +	if (intel_dp->psr.panel_replay_enabled)
> +		goto no_err;
> +
>  	/*
>  	 * If a PSR error happened and the driver is reloaded, the
> EDP_PSR_IIR
>  	 * will still keep the error set even after the reset done in the @@ -
> 1651,6 +1663,7 @@ static bool psr_interrupt_error_check(struct intel_dp
> *intel_dp)
>  		return false;
>  	}
> 
> +no_err:
>  	return true;
>  }
> 
> --
> 2.34.1

[PATCH v3 08/21] drm/i915/psr: Unify panel replay enable/disable sink

[Jouni Högander]

Unify enabling and disabling of psr/panel replay for a sink. Modify
intel_psr_enable_sink accordingly and use it for both cases.

v2:
  - enable panel replay for sink before link training
  - write ALPM_CONFIG only for PSR
  - add DP_PSR_CRC_VERIFICATION only for PSR
  - take care of disable sink as well

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++--
 drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++++++++++++-------
 drivers/gpu/drm/i915/display/intel_psr.h |  2 +
 3 files changed, 46 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 922194b957be..6721a478a633 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2800,15 +2800,14 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
 				    const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-	if (HAS_DP20(dev_priv)) {
+	if (HAS_DP20(dev_priv))
 		intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
 					    crtc_state);
-		if (crtc_state->has_panel_replay)
-			drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
-					   DP_PANEL_REPLAY_ENABLE);
-	}
+
+	/* Panel replay has to be enabled in sink dpcd before link training. */
+	if (crtc_state->has_panel_replay)
+		intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state);
 
 	if (DISPLAY_VER(dev_priv) >= 14)
 		mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2d5d1c2ce246..b905aee0ec81 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -638,19 +638,29 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
 	return false;
 }
 
-static void intel_psr_enable_sink(struct intel_dp *intel_dp)
+static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp)
+{
+	return intel_dp->psr.panel_replay_enabled ?
+		PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
+}
+
+/*
+ * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and DP_PSR_EN_CFG. We
+ * are relying on PSR definitions on these "common" bits.
+ */
+void intel_psr_enable_sink(struct intel_dp *intel_dp,
+			   const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 dpcd_val = DP_PSR_ENABLE;
 
-	if (intel_dp->psr.panel_replay_enabled)
-		return;
-
-	if (intel_dp->psr.psr2_enabled) {
+	if (crtc_state->has_psr2) {
 		/* Enable ALPM at sink for psr2 */
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
-				   DP_ALPM_ENABLE |
-				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
+		if (!crtc_state->has_panel_replay)
+			drm_dp_dpcd_writeb(&intel_dp->aux,
+					   DP_RECEIVER_ALPM_CONFIG,
+					   DP_ALPM_ENABLE |
+					   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
 
 		dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 		if (psr2_su_region_et_valid(intel_dp))
@@ -659,19 +669,26 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 		if (intel_dp->psr.link_standby)
 			dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 
-		if (DISPLAY_VER(dev_priv) >= 8)
+		if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv) >= 8)
 			dpcd_val |= DP_PSR_CRC_VERIFICATION;
 	}
 
-	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
+	if (crtc_state->has_panel_replay)
+		dpcd_val |= DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
+			DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN;
+
+	if (crtc_state->req_psr2_sdp_prior_scanline)
 		dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
 
 	if (intel_dp->psr.entry_setup_frames > 0)
 		dpcd_val |= DP_PSR_FRAME_CAPTURE;
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
+	drm_dp_dpcd_writeb(&intel_dp->aux,
+			   intel_psr_get_enable_sink_offset(intel_dp),
+			   dpcd_val);
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
+	if (intel_dp_is_edp(intel_dp))
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 }
 
 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
@@ -1701,9 +1718,14 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 			    intel_dp->psr.psr2_enabled ? "2" : "1");
 
 		intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
+
+		/*
+		 * Panel replay has to be enabled before link training: doing it
+		 * only for PSR here.
+		 */
+		intel_psr_enable_sink(intel_dp, crtc_state);
 	}
 
-	intel_psr_enable_sink(intel_dp);
 	intel_psr_enable_source(intel_dp, crtc_state);
 	intel_dp->psr.enabled = true;
 	intel_dp->psr.paused = false;
@@ -1813,9 +1835,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 		intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
 
 	/* Disable PSR on Sink */
-	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
+	drm_dp_dpcd_writeb(&intel_dp->aux,
+			   intel_psr_get_enable_sink_offset(intel_dp), 0);
 
-	if (intel_dp->psr.psr2_enabled)
+	if (!intel_dp->psr.panel_replay_enabled &&
+	    intel_dp->psr.psr2_enabled)
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
 
 	intel_dp->psr.enabled = false;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index f7c5cc07864f..b74382b38f4a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -23,6 +23,8 @@ struct intel_plane_state;
 
 bool intel_encoder_can_psr(struct intel_encoder *encoder);
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
+void intel_psr_enable_sink(struct intel_dp *intel_dp,
+			   const struct intel_crtc_state *crtc_state);
 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc);
 void intel_psr_post_plane_update(struct intel_atomic_state *state,
-- 
2.34.1

RE: [PATCH v3 08/21] drm/i915/psr: Unify panel replay enable/disable sink

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 08/21] drm/i915/psr: Unify panel replay enable/disable
> sink
> 
> Unify enabling and disabling of psr/panel replay for a sink. Modify
> intel_psr_enable_sink accordingly and use it for both cases.
> 
> v2:
>   - enable panel replay for sink before link training
>   - write ALPM_CONFIG only for PSR
>   - add DP_PSR_CRC_VERIFICATION only for PSR
>   - take care of disable sink as well
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++--
> drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++++++++++++-------
> drivers/gpu/drm/i915/display/intel_psr.h |  2 +
>  3 files changed, 46 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 922194b957be..6721a478a633 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2800,15 +2800,14 @@ static void intel_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
>  				    const struct drm_connector_state
> *conn_state)  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> 
> -	if (HAS_DP20(dev_priv)) {
> +	if (HAS_DP20(dev_priv))
>  		intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
>  					    crtc_state);
> -		if (crtc_state->has_panel_replay)
> -			drm_dp_dpcd_writeb(&intel_dp->aux,
> PANEL_REPLAY_CONFIG,
> -					   DP_PANEL_REPLAY_ENABLE);
> -	}
> +
> +	/* Panel replay has to be enabled in sink dpcd before link training. */
> +	if (crtc_state->has_panel_replay)
> +		intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state);
> 
>  	if (DISPLAY_VER(dev_priv) >= 14)
>  		mtl_ddi_pre_enable_dp(state, encoder, crtc_state,
> conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2d5d1c2ce246..b905aee0ec81 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -638,19 +638,29 @@ static bool psr2_su_region_et_valid(struct intel_dp
> *intel_dp)
>  	return false;
>  }
> 
> -static void intel_psr_enable_sink(struct intel_dp *intel_dp)
> +static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp
> +*intel_dp) {
> +	return intel_dp->psr.panel_replay_enabled ?
> +		PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
> +}
> +
> +/*
> + * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and
> +DP_PSR_EN_CFG. We
> + * are relying on PSR definitions on these "common" bits.
> + */
> +void intel_psr_enable_sink(struct intel_dp *intel_dp,
> +			   const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 dpcd_val = DP_PSR_ENABLE;
> 
> -	if (intel_dp->psr.panel_replay_enabled)
> -		return;
> -
> -	if (intel_dp->psr.psr2_enabled) {
> +	if (crtc_state->has_psr2) {
>  		/* Enable ALPM at sink for psr2 */
> -		drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
> -				   DP_ALPM_ENABLE |
> -
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> +		if (!crtc_state->has_panel_replay)
> +			drm_dp_dpcd_writeb(&intel_dp->aux,
> +					   DP_RECEIVER_ALPM_CONFIG,
> +					   DP_ALPM_ENABLE |
> +
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> 
>  		dpcd_val |= DP_PSR_ENABLE_PSR2 |
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
>  		if (psr2_su_region_et_valid(intel_dp))
> @@ -659,19 +669,26 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp)
>  		if (intel_dp->psr.link_standby)
>  			dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> 
> -		if (DISPLAY_VER(dev_priv) >= 8)
> +		if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv)
> >= 8)
>  			dpcd_val |= DP_PSR_CRC_VERIFICATION;
>  	}
> 
> -	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
> +	if (crtc_state->has_panel_replay)
> +		dpcd_val |=
> DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
> +			DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN;
> +
> +	if (crtc_state->req_psr2_sdp_prior_scanline)
>  		dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
> 
>  	if (intel_dp->psr.entry_setup_frames > 0)
>  		dpcd_val |= DP_PSR_FRAME_CAPTURE;
> 
> -	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
> +	drm_dp_dpcd_writeb(&intel_dp->aux,
> +			   intel_psr_get_enable_sink_offset(intel_dp),
> +			   dpcd_val);
> 
> -	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
> +	if (intel_dp_is_edp(intel_dp))
> +		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
>  }
> 
>  static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) @@ -1701,9
> +1718,14 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  			    intel_dp->psr.psr2_enabled ? "2" : "1");
> 
>  		intel_snps_phy_update_psr_power_state(dev_priv, phy,
> true);
> +
> +		/*
> +		 * Panel replay has to be enabled before link training: doing it
> +		 * only for PSR here.
> +		 */
> +		intel_psr_enable_sink(intel_dp, crtc_state);
>  	}
> 
> -	intel_psr_enable_sink(intel_dp);
>  	intel_psr_enable_source(intel_dp, crtc_state);
>  	intel_dp->psr.enabled = true;
>  	intel_dp->psr.paused = false;
> @@ -1813,9 +1835,11 @@ static void intel_psr_disable_locked(struct
> intel_dp *intel_dp)
>  		intel_snps_phy_update_psr_power_state(dev_priv, phy,
> false);
> 
>  	/* Disable PSR on Sink */
> -	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
> +	drm_dp_dpcd_writeb(&intel_dp->aux,
> +			   intel_psr_get_enable_sink_offset(intel_dp), 0);
> 
> -	if (intel_dp->psr.psr2_enabled)
> +	if (!intel_dp->psr.panel_replay_enabled &&
> +	    intel_dp->psr.psr2_enabled)
>  		drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG, 0);
> 
>  	intel_dp->psr.enabled = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index f7c5cc07864f..b74382b38f4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -23,6 +23,8 @@ struct intel_plane_state;
> 
>  bool intel_encoder_can_psr(struct intel_encoder *encoder);  void
> intel_psr_init_dpcd(struct intel_dp *intel_dp);
> +void intel_psr_enable_sink(struct intel_dp *intel_dp,
> +			   const struct intel_crtc_state *crtc_state);
>  void intel_psr_pre_plane_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc);
>  void intel_psr_post_plane_update(struct intel_atomic_state *state,
> --
> 2.34.1

[PATCH v3 09/21] drm/i915/psr: Panel replay has to be enabled before link training

[Jouni Högander]

Panel replay has to be enabled on sink side before link training. Take this
into account in fastset check and in initial fastset check.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.c      |  8 ++++++++
 drivers/gpu/drm/i915/display/intel_psr.c     |  3 ---
 drivers/gpu/drm/i915/display/intel_psr.h     |  3 +++
 4 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a92e959c8ac7..b7e5b2774f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5214,6 +5214,18 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_CSC(output_csc);
 	}
 
+	/*
+	 * Panel replay has to be enabled before link training. PSR doesn't have
+	 * this requirement -> check these only if using panel replay
+	 */
+	if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
+		PIPE_CONF_CHECK_BOOL(has_psr);
+		PIPE_CONF_CHECK_BOOL(has_psr2);
+		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
+		PIPE_CONF_CHECK_BOOL(has_panel_replay);
+	}
+
 	PIPE_CONF_CHECK_BOOL(double_wide);
 
 	if (dev_priv->display.dpll.mgr) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e7cda3162ea2..11143fb9b0f0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3326,6 +3326,14 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
 		fastset = false;
 	}
 
+	if (CAN_PANEL_REPLAY(intel_dp)) {
+		drm_dbg_kms(&i915->drm,
+			    "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
+			    encoder->base.base.id, encoder->base.name);
+		crtc_state->uapi.mode_changed = true;
+		fastset = false;
+	}
+
 	return fastset;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b905aee0ec81..24a80f47b84f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -192,9 +192,6 @@
 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
 			   (intel_dp)->psr.source_support)
 
-#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
-				    (intel_dp)->psr.source_panel_replay_support)
-
 bool intel_encoder_can_psr(struct intel_encoder *encoder)
 {
 	if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index b74382b38f4a..e687d7bdbb1f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -21,6 +21,9 @@ struct intel_encoder;
 struct intel_plane;
 struct intel_plane_state;
 
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+				    (intel_dp)->psr.source_panel_replay_support)
+
 bool intel_encoder_can_psr(struct intel_encoder *encoder);
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable_sink(struct intel_dp *intel_dp,
-- 
2.34.1

Re: [PATCH v3 09/21] drm/i915/psr: Panel replay has to be enabled before link training

[Jani Nikula]

On Fri, 19 Jan 2024, Jouni Högander <jouni.hogander@intel.com> wrote:
> Panel replay has to be enabled on sink side before link training. Take this
> into account in fastset check and in initial fastset check.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.c      |  8 ++++++++
>  drivers/gpu/drm/i915/display/intel_psr.c     |  3 ---
>  drivers/gpu/drm/i915/display/intel_psr.h     |  3 +++
>  4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a92e959c8ac7..b7e5b2774f2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5214,6 +5214,18 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  		PIPE_CONF_CHECK_CSC(output_csc);
>  	}
>  
> +	/*
> +	 * Panel replay has to be enabled before link training. PSR doesn't have
> +	 * this requirement -> check these only if using panel replay
> +	 */
> +	if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
> +		PIPE_CONF_CHECK_BOOL(has_psr);
> +		PIPE_CONF_CHECK_BOOL(has_psr2);
> +		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> +		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> +		PIPE_CONF_CHECK_BOOL(has_panel_replay);
> +	}
> +
>  	PIPE_CONF_CHECK_BOOL(double_wide);
>  
>  	if (dev_priv->display.dpll.mgr) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index e7cda3162ea2..11143fb9b0f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3326,6 +3326,14 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
>  		fastset = false;
>  	}
>  
> +	if (CAN_PANEL_REPLAY(intel_dp)) {
> +		drm_dbg_kms(&i915->drm,
> +			    "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
> +			    encoder->base.base.id, encoder->base.name);
> +		crtc_state->uapi.mode_changed = true;
> +		fastset = false;
> +	}
> +

I think I'd rather start adding functionality specific functions that
get called instead of exposing CAN_PANEL_REPLAY() and DP code covering
everything.

I.e. intel_psr_initial_fastset_check().

BR,
Jani.

>  	return fastset;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b905aee0ec81..24a80f47b84f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -192,9 +192,6 @@
>  #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
>  			   (intel_dp)->psr.source_support)
>  
> -#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
> -				    (intel_dp)->psr.source_panel_replay_support)
> -
>  bool intel_encoder_can_psr(struct intel_encoder *encoder)
>  {
>  	if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index b74382b38f4a..e687d7bdbb1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,9 @@ struct intel_encoder;
>  struct intel_plane;
>  struct intel_plane_state;
>  
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
> +				    (intel_dp)->psr.source_panel_replay_support)
> +
>  bool intel_encoder_can_psr(struct intel_encoder *encoder);
>  void intel_psr_init_dpcd(struct intel_dp *intel_dp);
>  void intel_psr_enable_sink(struct intel_dp *intel_dp,

-- 
Jani Nikula, Intel

Re: [PATCH v3 09/21] drm/i915/psr: Panel replay has to be enabled before link training

[Jani Nikula]

On Tue, 23 Jan 2024, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 19 Jan 2024, Jouni Högander <jouni.hogander@intel.com> wrote:
>> Panel replay has to be enabled on sink side before link training. Take this
>> into account in fastset check and in initial fastset check.
>>
>> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++++
>>  drivers/gpu/drm/i915/display/intel_dp.c      |  8 ++++++++
>>  drivers/gpu/drm/i915/display/intel_psr.c     |  3 ---
>>  drivers/gpu/drm/i915/display/intel_psr.h     |  3 +++
>>  4 files changed, 23 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index a92e959c8ac7..b7e5b2774f2e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5214,6 +5214,18 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>  		PIPE_CONF_CHECK_CSC(output_csc);
>>  	}
>>  
>> +	/*
>> +	 * Panel replay has to be enabled before link training. PSR doesn't have
>> +	 * this requirement -> check these only if using panel replay
>> +	 */
>> +	if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
>> +		PIPE_CONF_CHECK_BOOL(has_psr);
>> +		PIPE_CONF_CHECK_BOOL(has_psr2);
>> +		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
>> +		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
>> +		PIPE_CONF_CHECK_BOOL(has_panel_replay);
>> +	}
>> +
>>  	PIPE_CONF_CHECK_BOOL(double_wide);
>>  
>>  	if (dev_priv->display.dpll.mgr) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index e7cda3162ea2..11143fb9b0f0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3326,6 +3326,14 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
>>  		fastset = false;
>>  	}
>>  
>> +	if (CAN_PANEL_REPLAY(intel_dp)) {
>> +		drm_dbg_kms(&i915->drm,
>> +			    "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
>> +			    encoder->base.base.id, encoder->base.name);
>> +		crtc_state->uapi.mode_changed = true;
>> +		fastset = false;
>> +	}
>> +
>
> I think I'd rather start adding functionality specific functions that
> get called instead of exposing CAN_PANEL_REPLAY() and DP code covering
> everything.
>
> I.e. intel_psr_initial_fastset_check().

Rule of thumb: if code looks at intel_dp->psr, it belongs in
intel_psr.c.

Or, what would have to change if intel_dp->psr became an opaque pointer?

BR,
Jani.



>
> BR,
> Jani.
>
>>  	return fastset;
>>  }
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index b905aee0ec81..24a80f47b84f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -192,9 +192,6 @@
>>  #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
>>  			   (intel_dp)->psr.source_support)
>>  
>> -#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
>> -				    (intel_dp)->psr.source_panel_replay_support)
>> -
>>  bool intel_encoder_can_psr(struct intel_encoder *encoder)
>>  {
>>  	if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
>> index b74382b38f4a..e687d7bdbb1f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>> @@ -21,6 +21,9 @@ struct intel_encoder;
>>  struct intel_plane;
>>  struct intel_plane_state;
>>  
>> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
>> +				    (intel_dp)->psr.source_panel_replay_support)
>> +
>>  bool intel_encoder_can_psr(struct intel_encoder *encoder);
>>  void intel_psr_init_dpcd(struct intel_dp *intel_dp);
>>  void intel_psr_enable_sink(struct intel_dp *intel_dp,

-- 
Jani Nikula, Intel

RE: [PATCH v3 09/21] drm/i915/psr: Panel replay has to be enabled before link training

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 09/21] drm/i915/psr: Panel replay has to be enabled
> before link training
> 
> Panel replay has to be enabled on sink side before link training. Take this into
> account in fastset check and in initial fastset check.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.c      |  8 ++++++++
>  drivers/gpu/drm/i915/display/intel_psr.c     |  3 ---
>  drivers/gpu/drm/i915/display/intel_psr.h     |  3 +++
>  4 files changed, 23 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a92e959c8ac7..b7e5b2774f2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5214,6 +5214,18 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  		PIPE_CONF_CHECK_CSC(output_csc);
>  	}
> 
> +	/*
> +	 * Panel replay has to be enabled before link training. PSR doesn't
> have
> +	 * this requirement -> check these only if using panel replay
> +	 */
> +	if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
> +		PIPE_CONF_CHECK_BOOL(has_psr);
> +		PIPE_CONF_CHECK_BOOL(has_psr2);
> +		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> +		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> +		PIPE_CONF_CHECK_BOOL(has_panel_replay);
> +	}
> +
>  	PIPE_CONF_CHECK_BOOL(double_wide);
> 
>  	if (dev_priv->display.dpll.mgr) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e7cda3162ea2..11143fb9b0f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3326,6 +3326,14 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
>  		fastset = false;
>  	}
> 
> +	if (CAN_PANEL_REPLAY(intel_dp)) {
> +		drm_dbg_kms(&i915->drm,
> +			    "[ENCODER:%d:%s] Forcing full modeset to
> compute panel replay state\n",
> +			    encoder->base.base.id, encoder->base.name);
> +		crtc_state->uapi.mode_changed = true;
> +		fastset = false;
> +	}
> +
>  	return fastset;
>  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b905aee0ec81..24a80f47b84f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -192,9 +192,6 @@
>  #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
>  			   (intel_dp)->psr.source_support)
> 
> -#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> -				    (intel_dp)-
> >psr.source_panel_replay_support)
> -
>  bool intel_encoder_can_psr(struct intel_encoder *encoder)  {
>  	if (intel_encoder_is_dp(encoder) || encoder->type ==
> INTEL_OUTPUT_DP_MST) diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index b74382b38f4a..e687d7bdbb1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,9 @@ struct intel_encoder;
>  struct intel_plane;
>  struct intel_plane_state;
> 
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> +				    (intel_dp)-
> >psr.source_panel_replay_support)
> +
>  bool intel_encoder_can_psr(struct intel_encoder *encoder);  void
> intel_psr_init_dpcd(struct intel_dp *intel_dp);  void
> intel_psr_enable_sink(struct intel_dp *intel_dp,
> --
> 2.34.1

[PATCH v3 10/21] drm/i915/psr: Rename has_psr2 as has_sel_update

[Jouni Högander]

We are going to reuse has_psr2 for panel_replay as well. Rename it
as has_sel_update to avoid confusion.

v2: Rebase

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c |  5 +++--
 drivers/gpu/drm/i915/display/intel_display.c         |  2 +-
 drivers/gpu/drm/i915/display/intel_display_types.h   |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c              |  2 +-
 drivers/gpu/drm/i915/display/intel_fbc.c             |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c             | 10 +++++-----
 6 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 49fd100ec98a..5edbc9b3d766 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -266,9 +266,10 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		drm_dbg_kms(&i915->drm, "sdp split: %s\n",
 			    str_enabled_disabled(pipe_config->sdp_split_enable));
 
-		drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",
+		drm_dbg_kms(&i915->drm,
+			    "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n",
 			    str_enabled_disabled(pipe_config->has_psr),
-			    str_enabled_disabled(pipe_config->has_psr2),
+			    str_enabled_disabled(pipe_config->has_sel_update),
 			    str_enabled_disabled(pipe_config->has_panel_replay),
 			    str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b7e5b2774f2e..8bf1ba30b3fc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5220,7 +5220,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	 */
 	if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
 		PIPE_CONF_CHECK_BOOL(has_psr);
-		PIPE_CONF_CHECK_BOOL(has_psr2);
+		PIPE_CONF_CHECK_BOOL(has_sel_update);
 		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
 		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
 		PIPE_CONF_CHECK_BOOL(has_panel_replay);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ae2e8cff9d69..5890fef86547 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1211,7 +1211,7 @@ struct intel_crtc_state {
 
 	/* PSR is supported but might not be enabled due the lack of enabled planes */
 	bool has_psr;
-	bool has_psr2;
+	bool has_sel_update;
 	bool enable_psr2_sel_fetch;
 	bool enable_psr2_su_region_et;
 	bool req_psr2_sdp_prior_scanline;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 11143fb9b0f0..4e01182662ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2633,7 +2633,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
 		intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
 						 vsc);
-	} else if (crtc_state->has_psr2) {
+	} else if (crtc_state->has_psr && crtc_state->has_sel_update) {
 		/*
 		 * [PSR2 without colorimetry]
 		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index f17a1afb4929..647dd1b56073 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1235,7 +1235,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 	 * Recommendation is to keep this combination disabled
 	 * Bspec: 50422 HSD: 14010260002
 	 */
-	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
+	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
 		plane_state->no_fbc_reason = "PSR2 enabled";
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 24a80f47b84f..e328bef8916f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 dpcd_val = DP_PSR_ENABLE;
 
-	if (crtc_state->has_psr2) {
+	if (crtc_state->has_sel_update) {
 		/* Enable ALPM at sink for psr2 */
 		if (!crtc_state->has_panel_replay)
 			drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -1433,7 +1433,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	if (!crtc_state->has_psr)
 		return;
 
-	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
+	crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
@@ -1466,7 +1466,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 		pipe_config->has_psr = true;
 	}
 
-	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
+	pipe_config->has_sel_update = intel_dp->psr.psr2_enabled;
 	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 
 	if (!intel_dp->psr.psr2_enabled)
@@ -1691,7 +1691,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
 
-	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+	intel_dp->psr.psr2_enabled = crtc_state->has_sel_update;
 	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
@@ -2368,7 +2368,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 		needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
 		needs_to_disable |= !new_crtc_state->has_psr;
 		needs_to_disable |= !new_crtc_state->active_planes;
-		needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
+		needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled;
 		needs_to_disable |= DISPLAY_VER(i915) < 11 &&
 			new_crtc_state->wm_level_disabled;
 
-- 
2.34.1

RE: [PATCH v3 10/21] drm/i915/psr: Rename has_psr2 as has_sel_update

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 10/21] drm/i915/psr: Rename has_psr2 as
> has_sel_update
> 
> We are going to reuse has_psr2 for panel_replay as well. Rename it as
> has_sel_update to avoid confusion.
> 
> v2: Rebase
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_crtc_state_dump.c |  5 +++--
>  drivers/gpu/drm/i915/display/intel_display.c         |  2 +-
>  drivers/gpu/drm/i915/display/intel_display_types.h   |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c              |  2 +-
>  drivers/gpu/drm/i915/display/intel_fbc.c             |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c             | 10 +++++-----
>  6 files changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 49fd100ec98a..5edbc9b3d766 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -266,9 +266,10 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
>  		drm_dbg_kms(&i915->drm, "sdp split: %s\n",
>  			    str_enabled_disabled(pipe_config-
> >sdp_split_enable));
> 
> -		drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, panel replay:
> %s, selective fetch: %s\n",
> +		drm_dbg_kms(&i915->drm,
> +			    "psr: %s, selective update: %s, panel replay: %s,
> selective
> +fetch: %s\n",
>  			    str_enabled_disabled(pipe_config->has_psr),
> -			    str_enabled_disabled(pipe_config->has_psr2),
> +			    str_enabled_disabled(pipe_config-
> >has_sel_update),
>  			    str_enabled_disabled(pipe_config-
> >has_panel_replay),
>  			    str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b7e5b2774f2e..8bf1ba30b3fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5220,7 +5220,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  	 */
>  	if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
>  		PIPE_CONF_CHECK_BOOL(has_psr);
> -		PIPE_CONF_CHECK_BOOL(has_psr2);
> +		PIPE_CONF_CHECK_BOOL(has_sel_update);
>  		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
>  		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
>  		PIPE_CONF_CHECK_BOOL(has_panel_replay);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ae2e8cff9d69..5890fef86547 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1211,7 +1211,7 @@ struct intel_crtc_state {
> 
>  	/* PSR is supported but might not be enabled due the lack of enabled
> planes */
>  	bool has_psr;
> -	bool has_psr2;
> +	bool has_sel_update;
>  	bool enable_psr2_sel_fetch;
>  	bool enable_psr2_su_region_et;
>  	bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 11143fb9b0f0..4e01182662ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2633,7 +2633,7 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
>  	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
>  		intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>  						 vsc);
> -	} else if (crtc_state->has_psr2) {
> +	} else if (crtc_state->has_psr && crtc_state->has_sel_update) {
>  		/*
>  		 * [PSR2 without colorimetry]
>  		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index f17a1afb4929..647dd1b56073 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1235,7 +1235,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>  	 * Recommendation is to keep this combination disabled
>  	 * Bspec: 50422 HSD: 14010260002
>  	 */
> -	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
> +	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
>  		plane_state->no_fbc_reason = "PSR2 enabled";
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 24a80f47b84f..e328bef8916f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 dpcd_val = DP_PSR_ENABLE;
> 
> -	if (crtc_state->has_psr2) {
> +	if (crtc_state->has_sel_update) {
>  		/* Enable ALPM at sink for psr2 */
>  		if (!crtc_state->has_panel_replay)
>  			drm_dp_dpcd_writeb(&intel_dp->aux,
> @@ -1433,7 +1433,7 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>  	if (!crtc_state->has_psr)
>  		return;
> 
> -	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> +	crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp,
> +crtc_state);
>  }
> 
>  void intel_psr_get_config(struct intel_encoder *encoder, @@ -1466,7
> +1466,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
>  		pipe_config->has_psr = true;
>  	}
> 
> -	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
> +	pipe_config->has_sel_update = intel_dp->psr.psr2_enabled;
>  	pipe_config->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> 
>  	if (!intel_dp->psr.psr2_enabled)
> @@ -1691,7 +1691,7 @@ static void intel_psr_enable_locked(struct intel_dp
> *intel_dp,
> 
>  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> 
> -	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> +	intel_dp->psr.psr2_enabled = crtc_state->has_sel_update;
>  	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
>  	intel_dp->psr.busy_frontbuffer_bits = 0;
>  	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> @@ -2368,7 +2368,7 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
>  		needs_to_disable |=
> intel_crtc_needs_modeset(new_crtc_state);
>  		needs_to_disable |= !new_crtc_state->has_psr;
>  		needs_to_disable |= !new_crtc_state->active_planes;
> -		needs_to_disable |= new_crtc_state->has_psr2 != psr-
> >psr2_enabled;
> +		needs_to_disable |= new_crtc_state->has_sel_update !=
> +psr->psr2_enabled;
>  		needs_to_disable |= DISPLAY_VER(i915) < 11 &&
>  			new_crtc_state->wm_level_disabled;
> 
> --
> 2.34.1

[PATCH v3 11/21] drm/i915/psr: Modify VSC SDP calculation to support panel replay + su

[Jouni Högander]

Current VSC SDP calculation doesn't support panel replay + su. Change it to
support this combination as well.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4e01182662ff..ae368d9999b4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2633,14 +2633,6 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
 		intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
 						 vsc);
-	} else if (crtc_state->has_psr && crtc_state->has_sel_update) {
-		/*
-		 * [PSR2 without colorimetry]
-		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
-		 * 3D stereo + PSR/PSR2 + Y-coordinate.
-		 */
-		vsc->revision = 0x4;
-		vsc->length = 0xe;
 	} else if (crtc_state->has_panel_replay) {
 		/*
 		 * [Panel Replay without colorimetry info]
@@ -2649,6 +2641,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 		 */
 		vsc->revision = 0x6;
 		vsc->length = 0x10;
+	} else if (crtc_state->has_sel_update) {
+		/*
+		 * [PSR2 without colorimetry]
+		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
+		 * 3D stereo + PSR/PSR2 + Y-coordinate.
+		 */
+		vsc->revision = 0x4;
+		vsc->length = 0xe;
 	} else {
 		/*
 		 * [PSR1]
-- 
2.34.1

RE: [PATCH v3 11/21] drm/i915/psr: Modify VSC SDP calculation to support panel replay + su

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 11/21] drm/i915/psr: Modify VSC SDP calculation to
> support panel replay + su
> 
> Current VSC SDP calculation doesn't support panel replay + su. Change it to
> support this combination as well.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4e01182662ff..ae368d9999b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2633,14 +2633,6 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
>  	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
>  		intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>  						 vsc);
> -	} else if (crtc_state->has_psr && crtc_state->has_sel_update) {
> -		/*
> -		 * [PSR2 without colorimetry]
> -		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> -		 * 3D stereo + PSR/PSR2 + Y-coordinate.
> -		 */
> -		vsc->revision = 0x4;
> -		vsc->length = 0xe;
>  	} else if (crtc_state->has_panel_replay) {
>  		/*
>  		 * [Panel Replay without colorimetry info] @@ -2649,6
> +2641,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>  		 */
>  		vsc->revision = 0x6;
>  		vsc->length = 0x10;
> +	} else if (crtc_state->has_sel_update) {
> +		/*
> +		 * [PSR2 without colorimetry]
> +		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> +		 * 3D stereo + PSR/PSR2 + Y-coordinate.
> +		 */

The above code comments need to be modified for panel replay as well. How psr2+selective_update and pr+selective_update will be managed with the same intel_dp_compute_vsc_sdp() good to add some function description.

Regards,
Animesh 
> +		vsc->revision = 0x4;
> +		vsc->length = 0xe;
>  	} else {
>  		/*
>  		 * [PSR1]
> --
> 2.34.1

Re: [PATCH v3 11/21] drm/i915/psr: Modify VSC SDP calculation to support panel replay + su

[Hogander, Jouni]

On Fri, 2024-02-02 at 13:58 +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Friday, January 19, 2024 3:40 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> > <jouni.hogander@intel.com>
> > Subject: [PATCH v3 11/21] drm/i915/psr: Modify VSC SDP calculation
> > to
> > support panel replay + su
> > 
> > Current VSC SDP calculation doesn't support panel replay + su.
> > Change it to
> > support this combination as well.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++--------
> >  1 file changed, 8 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 4e01182662ff..ae368d9999b4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2633,14 +2633,6 @@ static void intel_dp_compute_vsc_sdp(struct
> > intel_dp *intel_dp,
> >         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> >                 intel_dp_compute_vsc_colorimetry(crtc_state,
> > conn_state,
> >                                                  vsc);
> > -       } else if (crtc_state->has_psr && crtc_state-
> > >has_sel_update) {
> > -               /*
> > -                * [PSR2 without colorimetry]
> > -                * Prepare VSC Header for SU as per eDP 1.4 spec,
> > Table 6-11
> > -                * 3D stereo + PSR/PSR2 + Y-coordinate.
> > -                */
> > -               vsc->revision = 0x4;
> > -               vsc->length = 0xe;
> >         } else if (crtc_state->has_panel_replay) {
> >                 /*
> >                  * [Panel Replay without colorimetry info] @@ -
> > 2649,6
> > +2641,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> > *intel_dp,
> >                  */
> >                 vsc->revision = 0x6;
> >                 vsc->length = 0x10;
> > +       } else if (crtc_state->has_sel_update) {
> > +               /*
> > +                * [PSR2 without colorimetry]
> > +                * Prepare VSC Header for SU as per eDP 1.4 spec,
> > Table 6-11
> > +                * 3D stereo + PSR/PSR2 + Y-coordinate.
> > +                */
> 
> The above code comments need to be modified for panel replay as well.
> How psr2+selective_update and pr+selective_update will be managed
> with the same intel_dp_compute_vsc_sdp() good to add some function
> description.

Please note that else if (crtc_state->has_panel_replay) {" is used for
both Panel Replay full frame update and Panel Replay SU.

BR,

Jouni Högander

> 
> Regards,
> Animesh 
> > +               vsc->revision = 0x4;
> > +               vsc->length = 0xe;
> >         } else {
> >                 /*
> >                  * [PSR1]
> > --
> > 2.34.1
> 

[PATCH v3 12/21] drm/i915/psr: Rename psr2_enabled as sel_update_enabled

[Jouni Högander]

We are about to reuse psr2_enabled for panel replay as well. Rename
it as sel_update_enabled to avoid confusion.

v2: Rebase

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 50 +++++++++----------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5890fef86547..6cef3dabcf45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1705,7 +1705,7 @@ struct intel_psr {
 	unsigned int busy_frontbuffer_bits;
 	bool sink_psr2_support;
 	bool link_standby;
-	bool psr2_enabled;
+	bool sel_update_enabled;
 	bool psr2_sel_fetch_enabled;
 	bool psr2_sel_fetch_cff_enabled;
 	bool req_psr2_sdp_prior_scanline;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e328bef8916f..34bc0a4c1ba2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -356,12 +356,12 @@ static void psr_irq_control(struct intel_dp *intel_dp)
 }
 
 static void psr_event_print(struct drm_i915_private *i915,
-			    u32 val, bool psr2_enabled)
+			    u32 val, bool sel_update_enabled)
 {
 	drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
 	if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 		drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
-	if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
+	if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled)
 		drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
 	if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 		drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
@@ -389,7 +389,7 @@ static void psr_event_print(struct drm_i915_private *i915,
 		drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
 	if (val & PSR_EVENT_LPSP_MODE_EXIT)
 		drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
-	if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
+	if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled)
 		drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
 }
 
@@ -417,7 +417,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
 
 			val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0);
 
-			psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
+			psr_event_print(dev_priv, val, intel_dp->psr.sel_update_enabled);
 		}
 	}
 
@@ -1466,10 +1466,10 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 		pipe_config->has_psr = true;
 	}
 
-	pipe_config->has_sel_update = intel_dp->psr.psr2_enabled;
+	pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;
 	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 
-	if (!intel_dp->psr.psr2_enabled)
+	if (!intel_dp->psr.sel_update_enabled)
 		goto unlock;
 
 	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
@@ -1505,7 +1505,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	/* psr1, psr2 and panel-replay are mutually exclusive.*/
 	if (intel_dp->psr.panel_replay_enabled)
 		dg2_activate_panel_replay(intel_dp);
-	else if (intel_dp->psr.psr2_enabled)
+	else if (intel_dp->psr.sel_update_enabled)
 		hsw_activate_psr2(intel_dp);
 	else
 		hsw_activate_psr1(intel_dp);
@@ -1624,7 +1624,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 	 */
 	wm_optimization_wa(intel_dp, crtc_state);
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.sel_update_enabled) {
 		if (DISPLAY_VER(dev_priv) == 9)
 			intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
 				     PSR2_VSC_ENABLE_PROG_HEADER |
@@ -1691,7 +1691,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
 
-	intel_dp->psr.psr2_enabled = crtc_state->has_sel_update;
+	intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
 	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
@@ -1712,7 +1712,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 		drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
 	} else {
 		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
-			    intel_dp->psr.psr2_enabled ? "2" : "1");
+			    intel_dp->psr.sel_update_enabled ? "2" : "1");
 
 		intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
 
@@ -1751,7 +1751,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 	if (intel_dp->psr.panel_replay_enabled) {
 		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
 			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
-	} else if (intel_dp->psr.psr2_enabled) {
+	} else if (intel_dp->psr.sel_update_enabled) {
 		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
 
 		val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
@@ -1774,7 +1774,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
 	i915_reg_t psr_status;
 	u32 psr_status_mask;
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.sel_update_enabled) {
 		psr_status = EDP_PSR2_STATUS(cpu_transcoder);
 		psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 	} else {
@@ -1804,7 +1804,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 		drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n");
 	else
 		drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
-			    intel_dp->psr.psr2_enabled ? "2" : "1");
+			    intel_dp->psr.sel_update_enabled ? "2" : "1");
 
 	intel_psr_exit(intel_dp);
 	intel_psr_wait_exit_locked(intel_dp);
@@ -1817,7 +1817,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
 			     wa_16013835468_bit_get(intel_dp), 0);
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.sel_update_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
 		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
@@ -1836,12 +1836,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 			   intel_psr_get_enable_sink_offset(intel_dp), 0);
 
 	if (!intel_dp->psr.panel_replay_enabled &&
-	    intel_dp->psr.psr2_enabled)
+	    intel_dp->psr.sel_update_enabled)
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
 
 	intel_dp->psr.enabled = false;
 	intel_dp->psr.panel_replay_enabled = false;
-	intel_dp->psr.psr2_enabled = false;
+	intel_dp->psr.sel_update_enabled = false;
 	intel_dp->psr.psr2_sel_fetch_enabled = false;
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
 }
@@ -2368,7 +2368,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 		needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
 		needs_to_disable |= !new_crtc_state->has_psr;
 		needs_to_disable |= !new_crtc_state->active_planes;
-		needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled;
+		needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled;
 		needs_to_disable |= DISPLAY_VER(i915) < 11 &&
 			new_crtc_state->wm_level_disabled;
 
@@ -2486,7 +2486,7 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
 		if (!intel_dp->psr.enabled)
 			continue;
 
-		if (intel_dp->psr.psr2_enabled)
+		if (intel_dp->psr.sel_update_enabled)
 			ret = _psr2_ready_for_pipe_update_locked(intel_dp);
 		else
 			ret = _psr1_ready_for_pipe_update_locked(intel_dp);
@@ -2507,7 +2507,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
 	if (!intel_dp->psr.enabled)
 		return false;
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.sel_update_enabled) {
 		reg = EDP_PSR2_STATUS(cpu_transcoder);
 		mask = EDP_PSR2_STATUS_STATE_MASK;
 	} else {
@@ -2748,7 +2748,7 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
-	if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||
+	if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||
 	    !intel_dp->psr.active)
 		return;
 
@@ -2949,7 +2949,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
 	u8 val;
 	int r;
 
-	if (!psr->psr2_enabled)
+	if (!psr->sel_update_enabled)
 		return;
 
 	r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
@@ -3129,7 +3129,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
 	const char *status = "unknown";
 	u32 val, status_val;
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.sel_update_enabled) {
 		static const char * const live_status[] = {
 			"IDLE",
 			"CAPTURE",
@@ -3193,7 +3193,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 	if (psr->panel_replay_enabled)
 		status = "Panel Replay Enabled";
 	else if (psr->enabled)
-		status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
+		status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 enabled";
 	else
 		status = "disabled";
 	seq_printf(m, "PSR mode: %s\n", status);
@@ -3208,7 +3208,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 	if (psr->panel_replay_enabled) {
 		val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
 		enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
-	} else if (psr->psr2_enabled) {
+	} else if (psr->sel_update_enabled) {
 		val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
 		enabled = val & EDP_PSR2_ENABLE;
 	} else {
@@ -3234,7 +3234,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 		seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
 	}
 
-	if (psr->psr2_enabled) {
+	if (psr->sel_update_enabled) {
 		u32 su_frames_val[3];
 		int frame;
 
-- 
2.34.1

[PATCH v3 13/21] drm/panelreplay: dpcd register definition for panelreplay SU

[Jouni Högander]

Add definitions for panel replay selective update

v2: Remove unnecessary Cc from commit message

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 include/drm/display/drm_dp.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 281afff6ee4e..4ebf79948c7f 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -548,6 +548,12 @@
 # define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
 # define DP_PANEL_REPLAY_SU_SUPPORT         (1 << 1)
 
+#define DP_PANEL_PANEL_REPLAY_CAPABILITY		0xb1
+# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED	(1 << 5)
+
+#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY		0xb2
+#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY		0xb4
+
 /* Link Configuration */
 #define	DP_LINK_BW_SET		            0x100
 # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
-- 
2.34.1

RE: [PATCH v3 13/21] drm/panelreplay: dpcd register definition for panelreplay SU

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 13/21] drm/panelreplay: dpcd register definition for
> panelreplay SU
> 
> Add definitions for panel replay selective update
> 
> v2: Remove unnecessary Cc from commit message
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  include/drm/display/drm_dp.h | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 281afff6ee4e..4ebf79948c7f 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -548,6 +548,12 @@
>  # define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
>  # define DP_PANEL_REPLAY_SU_SUPPORT         (1 << 1)
> 
> +#define DP_PANEL_PANEL_REPLAY_CAPABILITY		0xb1
> +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED	(1 <<
> 5)
> +
> +#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY		0xb2
> +#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY		0xb4
> +
>  /* Link Configuration */
>  #define	DP_LINK_BW_SET		            0x100
>  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
> --
> 2.34.1

[PATCH v3 14/21] drm/i915/psr: Detect panel replay selective update support

[Jouni Högander]

Add new boolean to store panel replay selective update support of sink into
intel_psr struct.  Detect panel replay selective update support and store
it into this new boolean.

v2: Merge adding new boolean into this patch

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c           | 10 ++++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6cef3dabcf45..1c870ff8b27e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1720,6 +1720,7 @@ struct intel_psr {
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
+	bool sink_panel_replay_su_support;
 	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 34bc0a4c1ba2..8bf6d0754c18 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -520,9 +520,15 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 		return;
 	}
 
-	drm_dbg_kms(&i915->drm,
-		    "Panel replay is supported by panel\n");
 	intel_dp->psr.sink_panel_replay_support = true;
+
+	if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
+		intel_dp->psr.sink_panel_replay_su_support = true;
+
+	drm_dbg_kms(&i915->drm,
+		    "Panel replay %sis supported by panel\n",
+		    intel_dp->psr.sink_panel_replay_su_support ?
+		    "selective_update " : "");
 }
 
 static void _psr_init_dpcd(struct intel_dp *intel_dp)
-- 
2.34.1

RE: [PATCH v3 14/21] drm/i915/psr: Detect panel replay selective update support

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 14/21] drm/i915/psr: Detect panel replay selective update
> support
> 
> Add new boolean to store panel replay selective update support of sink into
> intel_psr struct.  Detect panel replay selective update support and store it
> into this new boolean.
> 
> v2: Merge adding new boolean into this patch
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c           | 10 ++++++++--
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6cef3dabcf45..1c870ff8b27e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1720,6 +1720,7 @@ struct intel_psr {
>  	u16 su_y_granularity;
>  	bool source_panel_replay_support;
>  	bool sink_panel_replay_support;
> +	bool sink_panel_replay_su_support;
>  	bool panel_replay_enabled;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 34bc0a4c1ba2..8bf6d0754c18 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -520,9 +520,15 @@ static void _panel_replay_init_dpcd(struct intel_dp
> *intel_dp)
>  		return;
>  	}
> 
> -	drm_dbg_kms(&i915->drm,
> -		    "Panel replay is supported by panel\n");
>  	intel_dp->psr.sink_panel_replay_support = true;
> +
> +	if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> +		intel_dp->psr.sink_panel_replay_su_support = true;
> +
> +	drm_dbg_kms(&i915->drm,
> +		    "Panel replay %sis supported by panel\n",
> +		    intel_dp->psr.sink_panel_replay_su_support ?
> +		    "selective_update " : "");
>  }
> 
>  static void _psr_init_dpcd(struct intel_dp *intel_dp)
> --
> 2.34.1

[PATCH v3 15/21] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay

[Jouni Högander]

Currently intel_dp_get_su_granularity doesn't support panel replay.
This fix modifies it to support panel replay as well.

v2: rely on PSR definitions on common bits

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 62 +++++++++++++++++++++---
 1 file changed, 55 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8bf6d0754c18..b8367fb8b3d4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -466,6 +466,40 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 	return val;
 }
 
+static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
+{
+	u8 su_capability;
+
+	if (intel_dp->psr.sink_panel_replay_su_support)
+		drm_dp_dpcd_read(&intel_dp->aux,
+				 DP_PANEL_PANEL_REPLAY_X_GRANULARITY,
+				 &su_capability, 1);
+	else
+		su_capability = intel_dp->psr_dpcd[1];
+
+	return su_capability;
+}
+
+static unsigned int
+intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
+{
+	return intel_dp->psr.sink_panel_replay_su_support ?
+		DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
+		DP_PSR2_SU_X_GRANULARITY;
+}
+
+static unsigned int
+intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
+{
+	return intel_dp->psr.sink_panel_replay_su_support ?
+		DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
+		DP_PSR2_SU_Y_GRANULARITY;
+}
+
+/*
+ * Note: Bits related to granularity are same in panel replay and psr
+ * registers. Rely on PSR definitions on these "common" bits.
+ */
 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -473,18 +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	u16 w;
 	u8 y;
 
-	/* If sink don't have specific granularity requirements set legacy ones */
-	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+	/*
+	 * TODO: Do we need to take into account panel supporting both PSR and
+	 * Panel replay?
+	 */
+
+	/*
+	 * If sink don't have specific granularity requirements set legacy
+	 * ones.
+	 */
+	if (!(intel_dp_get_su_capability(intel_dp) &
+	      DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 		/* As PSR2 HW sends full lines, we do not care about x granularity */
 		w = 4;
 		y = 4;
 		goto exit;
 	}
 
-	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
+	r = drm_dp_dpcd_read(&intel_dp->aux,
+			     intel_dp_get_su_x_granularity_offset(intel_dp),
+			     &w, 2);
 	if (r != 2)
 		drm_dbg_kms(&i915->drm,
-			    "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
+			    "Unable to read selective update x granularity\n");
 	/*
 	 * Spec says that if the value read is 0 the default granularity should
 	 * be used instead.
@@ -492,10 +537,12 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	if (r != 2 || w == 0)
 		w = 4;
 
-	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
+	r = drm_dp_dpcd_read(&intel_dp->aux,
+			     intel_dp_get_su_y_granularity_offset(intel_dp),
+			     &y, 1);
 	if (r != 1) {
 		drm_dbg_kms(&i915->drm,
-			    "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
+			    "Unable to read selective update y granularity\n");
 		y = 4;
 	}
 	if (y == 0)
@@ -588,7 +635,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	if (intel_dp->psr_dpcd[0])
 		_psr_init_dpcd(intel_dp);
 
-	if (intel_dp->psr.sink_psr2_support)
+	if (intel_dp->psr.sink_psr2_support ||
+	    intel_dp->psr.sink_panel_replay_su_support)
 		intel_dp_get_su_granularity(intel_dp);
 }
 
-- 
2.34.1

RE: [PATCH v3 15/21] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 15/21] drm/i915/psr: Modify intel_dp_get_su_granularity
> to support panel replay
> 
> Currently intel_dp_get_su_granularity doesn't support panel replay.
> This fix modifies it to support panel replay as well.
> 
> v2: rely on PSR definitions on common bits
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 62 +++++++++++++++++++++---
>  1 file changed, 55 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8bf6d0754c18..b8367fb8b3d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -466,6 +466,40 @@ static u8 intel_dp_get_sink_sync_latency(struct
> intel_dp *intel_dp)
>  	return val;
>  }
> 
> +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) {
> +	u8 su_capability;
> +
> +	if (intel_dp->psr.sink_panel_replay_su_support)
> +		drm_dp_dpcd_read(&intel_dp->aux,
> +				 DP_PANEL_PANEL_REPLAY_X_GRANULARITY,
> +				 &su_capability, 1);
> +	else
> +		su_capability = intel_dp->psr_dpcd[1];
> +
> +	return su_capability;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) {
> +	return intel_dp->psr.sink_panel_replay_su_support ?
> +		DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
> +		DP_PSR2_SU_X_GRANULARITY;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) {
> +	return intel_dp->psr.sink_panel_replay_su_support ?
> +		DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
> +		DP_PSR2_SU_Y_GRANULARITY;
> +}
> +
> +/*
> + * Note: Bits related to granularity are same in panel replay and psr
> + * registers. Rely on PSR definitions on these "common" bits.
> + */
>  static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -473,18
> +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp
> *intel_dp)
>  	u16 w;
>  	u8 y;
> 
> -	/* If sink don't have specific granularity requirements set legacy ones
> */
> -	if (!(intel_dp->psr_dpcd[1] &
> DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> +	/*
> +	 * TODO: Do we need to take into account panel supporting both PSR
> and
> +	 * Panel replay?
> +	 */
> +
> +	/*
> +	 * If sink don't have specific granularity requirements set legacy
> +	 * ones.
> +	 */
> +	if (!(intel_dp_get_su_capability(intel_dp) &
> +	      DP_PSR2_SU_GRANULARITY_REQUIRED)) {
>  		/* As PSR2 HW sends full lines, we do not care about x
> granularity */
>  		w = 4;
>  		y = 4;
>  		goto exit;
>  	}
> 
> -	r = drm_dp_dpcd_read(&intel_dp->aux,
> DP_PSR2_SU_X_GRANULARITY, &w, 2);
> +	r = drm_dp_dpcd_read(&intel_dp->aux,
> +			     intel_dp_get_su_x_granularity_offset(intel_dp),
> +			     &w, 2);
>  	if (r != 2)
>  		drm_dbg_kms(&i915->drm,
> -			    "Unable to read
> DP_PSR2_SU_X_GRANULARITY\n");
> +			    "Unable to read selective update x granularity\n");
>  	/*
>  	 * Spec says that if the value read is 0 the default granularity should
>  	 * be used instead.
> @@ -492,10 +537,12 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
>  	if (r != 2 || w == 0)
>  		w = 4;
> 
> -	r = drm_dp_dpcd_read(&intel_dp->aux,
> DP_PSR2_SU_Y_GRANULARITY, &y, 1);
> +	r = drm_dp_dpcd_read(&intel_dp->aux,
> +			     intel_dp_get_su_y_granularity_offset(intel_dp),
> +			     &y, 1);
>  	if (r != 1) {
>  		drm_dbg_kms(&i915->drm,
> -			    "Unable to read
> DP_PSR2_SU_Y_GRANULARITY\n");
> +			    "Unable to read selective update y granularity\n");
>  		y = 4;
>  	}
>  	if (y == 0)
> @@ -588,7 +635,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  	if (intel_dp->psr_dpcd[0])
>  		_psr_init_dpcd(intel_dp);
> 
> -	if (intel_dp->psr.sink_psr2_support)
> +	if (intel_dp->psr.sink_psr2_support ||
> +	    intel_dp->psr.sink_panel_replay_su_support)
>  		intel_dp_get_su_granularity(intel_dp);
>  }
> 
> --
> 2.34.1

[PATCH v3 16/21] drm/i915/psr: Ensure early transport is not enabled for panel replay

[Jouni Högander]

Early transport is not supported by DP2.0. Ensure early transport is kept
disabled for panel replay selective update.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 .../gpu/drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c          | 15 +++++++++++----
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1c870ff8b27e..82767751c674 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1706,6 +1706,7 @@ struct intel_psr {
 	bool sink_psr2_support;
 	bool link_standby;
 	bool sel_update_enabled;
+	bool sel_update_et_enabled;
 	bool psr2_sel_fetch_enabled;
 	bool psr2_sel_fetch_cff_enabled;
 	bool req_psr2_sdp_prior_scanline;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b8367fb8b3d4..617ffd1854dc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -677,15 +677,20 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 		       aux_ctl);
 }
 
-static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
+static bool psr2_su_region_et_valid(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
+	if (crtc_state->has_panel_replay)
+		goto unsupported;
+
 	if (DISPLAY_VER(i915) >= 20 &&
 	    intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
 	    !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
 		return true;
 
+unsupported:
 	return false;
 }
 
@@ -714,7 +719,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
 					   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
 
 		dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
-		if (psr2_su_region_et_valid(intel_dp))
+		if (crtc_state->enable_psr2_su_region_et)
 			dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
 	} else {
 		if (intel_dp->psr.link_standby)
@@ -973,7 +978,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), 0);
 	}
 
-	if (psr2_su_region_et_valid(intel_dp))
+	if (intel_dp->psr.sel_update_et_enabled)
 		val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
 
 	/*
@@ -1138,7 +1143,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (psr2_su_region_et_valid(intel_dp))
+	if (psr2_su_region_et_valid(intel_dp, crtc_state))
 		crtc_state->enable_psr2_su_region_et = true;
 
 	return crtc_state->enable_psr2_sel_fetch = true;
@@ -1746,6 +1751,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
 
 	intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
+	intel_dp->psr.sel_update_et_enabled = crtc_state->enable_psr2_su_region_et;
 	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
@@ -1896,6 +1902,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	intel_dp->psr.enabled = false;
 	intel_dp->psr.panel_replay_enabled = false;
 	intel_dp->psr.sel_update_enabled = false;
+	intel_dp->psr.sel_update_et_enabled = false;
 	intel_dp->psr.psr2_sel_fetch_enabled = false;
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
 }
-- 
2.34.1

RE: [PATCH v3 16/21] drm/i915/psr: Ensure early transport is not enabled for panel replay

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 16/21] drm/i915/psr: Ensure early transport is not
> enabled for panel replay
> 
> Early transport is not supported by DP2.0. Ensure early transport is kept
> disabled for panel replay selective update.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c          | 15 +++++++++++----
>  2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1c870ff8b27e..82767751c674 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1706,6 +1706,7 @@ struct intel_psr {
>  	bool sink_psr2_support;
>  	bool link_standby;
>  	bool sel_update_enabled;
> +	bool sel_update_et_enabled;
>  	bool psr2_sel_fetch_enabled;
>  	bool psr2_sel_fetch_cff_enabled;
>  	bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b8367fb8b3d4..617ffd1854dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -677,15 +677,20 @@ static void hsw_psr_setup_aux(struct intel_dp
> *intel_dp)
>  		       aux_ctl);
>  }
> 
> -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
> +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> 
> +	if (crtc_state->has_panel_replay)
> +		goto unsupported;
> +
>  	if (DISPLAY_VER(i915) >= 20 &&
>  	    intel_dp->psr_dpcd[0] ==
> DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
>  	    !(intel_dp->psr.debug &
> I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
>  		return true;
> 
> +unsupported:
>  	return false;
>  }
> 
> @@ -714,7 +719,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
> 
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> 
>  		dpcd_val |= DP_PSR_ENABLE_PSR2 |
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> -		if (psr2_su_region_et_valid(intel_dp))
> +		if (crtc_state->enable_psr2_su_region_et)
>  			dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
>  	} else {
>  		if (intel_dp->psr.link_standby)
> @@ -973,7 +978,7 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>  		intel_de_write(dev_priv,
> PSR2_MAN_TRK_CTL(cpu_transcoder), 0);
>  	}
> 
> -	if (psr2_su_region_et_valid(intel_dp))
> +	if (intel_dp->psr.sel_update_et_enabled)

AFICU this is the only place where the sel_update_et_enabled variable is used and calling the function psr2_su_region_et_valid() vs adding a variable in intel_psr structure, 
I feel good to go with call the function once.

Regards,
Animesh

>  		val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
> 
>  	/*
> @@ -1138,7 +1143,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct
> intel_dp *intel_dp,
>  		return false;
>  	}
> 
> -	if (psr2_su_region_et_valid(intel_dp))
> +	if (psr2_su_region_et_valid(intel_dp, crtc_state))
>  		crtc_state->enable_psr2_su_region_et = true;
> 
>  	return crtc_state->enable_psr2_sel_fetch = true; @@ -1746,6
> +1751,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> 
>  	intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
> +	intel_dp->psr.sel_update_et_enabled =
> +crtc_state->enable_psr2_su_region_et;
>  	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
>  	intel_dp->psr.busy_frontbuffer_bits = 0;
>  	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> @@ -1896,6 +1902,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>  	intel_dp->psr.enabled = false;
>  	intel_dp->psr.panel_replay_enabled = false;
>  	intel_dp->psr.sel_update_enabled = false;
> +	intel_dp->psr.sel_update_et_enabled = false;
>  	intel_dp->psr.psr2_sel_fetch_enabled = false;
>  	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;  }
> --
> 2.34.1

[PATCH v3 17/21] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status

[Jouni Högander]

Panel replay uses SRD_STATUS to track it's status despite selective update
mode.

Bspec: 53370

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 617ffd1854dc..01785587adbb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2547,7 +2547,8 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
 		if (!intel_dp->psr.enabled)
 			continue;
 
-		if (intel_dp->psr.sel_update_enabled)
+		if (!intel_dp->psr.panel_replay_enabled &&
+		    intel_dp->psr.sel_update_enabled)
 			ret = _psr2_ready_for_pipe_update_locked(intel_dp);
 		else
 			ret = _psr1_ready_for_pipe_update_locked(intel_dp);
@@ -2568,7 +2569,8 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
 	if (!intel_dp->psr.enabled)
 		return false;
 
-	if (intel_dp->psr.sel_update_enabled) {
+	if (!intel_dp->psr.panel_replay_enabled &&
+	    intel_dp->psr.sel_update_enabled) {
 		reg = EDP_PSR2_STATUS(cpu_transcoder);
 		mask = EDP_PSR2_STATUS_STATE_MASK;
 	} else {
-- 
2.34.1

[PATCH v3 18/21] drm/i915/psr: Do not apply workarounds in case of panel replay

[Jouni Högander]

There are some workarounds that are not applicable for panel replay. Do not
apply these if panel replay is used.

Bspec: 66624, 50422

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c  |  5 +++--
 drivers/gpu/drm/i915/display/intel_hdmi.c |  3 ++-
 drivers/gpu/drm/i915/display/intel_psr.c  | 16 ++++++++++------
 3 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 647dd1b56073..c5a1395428cd 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1235,7 +1235,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 	 * Recommendation is to keep this combination disabled
 	 * Bspec: 50422 HSD: 14010260002
 	 */
-	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
+	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update &&
+	    !crtc_state->has_panel_replay) {
 		plane_state->no_fbc_reason = "PSR2 enabled";
 		return 0;
 	}
@@ -1243,7 +1244,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 	/* Wa_14016291713 */
 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
 	     IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
-	    crtc_state->has_psr) {
+	    crtc_state->has_psr && !crtc_state->has_panel_replay) {
 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7020e5806109..7aabb2f745d8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -524,7 +524,8 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
 			       0);
 
 	/* Wa_14013475917 */
-	if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC))
+	if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
+	      !crtc_state->has_panel_replay && type == DP_SDP_VSC))
 		val |= hsw_infoframe_enable(type);
 
 	if (type == DP_SDP_VSC)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 01785587adbb..d28a3a1e945b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1694,13 +1694,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 * All supported adlp panels have 1-based X granularity, this may
 		 * cause issues if non-supported panels are used.
 		 */
-		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
-		    IS_ALDERLAKE_P(dev_priv))
+		if (!intel_dp->psr.panel_replay_enabled &&
+		    (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
+		     IS_ALDERLAKE_P(dev_priv)))
 			intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
 				     0, ADLP_1_BASED_X_GRANULARITY);
 
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
+		if (!intel_dp->psr.panel_replay_enabled &&
+		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1879,7 +1881,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.sel_update_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
+		if (!intel_dp->psr.panel_replay_enabled &&
+		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2321,8 +2324,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 
 	/* Wa_14014971492 */
-	if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
-	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
+	if (!crtc_state->has_panel_replay &&
+	    ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
+	      IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) &&
 	    crtc_state->splitter.enable)
 		crtc_state->psr2_su_area.y1 = 0;
 
-- 
2.34.1

[PATCH v3 19/21] drm/i915/psr: Update PSR module parameter descriptions

[Jouni Högander]

We are re-using PSR module parameters for panel replay. Update module
parameter descriptions with panel replay information:

enable_psr:

-1 (default) == follow what is in VBT
0 == disable PSR/PR
1 == Allow PSR1 and PR full frame update
2 == allow PSR1/PSR2 and PR Selective Update

enable_psr2_sel_fetch

0 == disable selective fetch for PSR and PR
1 (default) == allow selective fetch for PSR PR

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
index 11e03cfb774d..1c5e20ec7f1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -102,7 +102,8 @@ intel_display_param_named_unsafe(enable_fbc, int, 0400,
 
 intel_display_param_named_unsafe(enable_psr, int, 0400,
 	"Enable PSR "
-	"(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) "
+	"(0=disabled, 1=enable up to PSR1 and Panel Replay full frame update, "
+	"2=enable up to PSR2 and Panel Replay Selective Update) "
 	"Default: -1 (use per-chip default)");
 
 intel_display_param_named(psr_safest_params, bool, 0400,
@@ -112,7 +113,7 @@ intel_display_param_named(psr_safest_params, bool, 0400,
 	"Default: 0");
 
 intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400,
-	"Enable PSR2 selective fetch "
+	"Enable PSR2 and Panel Replay selective fetch "
 	"(0=disabled, 1=enabled) "
 	"Default: 1");
 
-- 
2.34.1

RE: [PATCH v3 19/21] drm/i915/psr: Update PSR module parameter descriptions

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v3 19/21] drm/i915/psr: Update PSR module parameter
> descriptions
> 
> We are re-using PSR module parameters for panel replay. Update module
> parameter descriptions with panel replay information:
> 
> enable_psr:
> 
> -1 (default) == follow what is in VBT
> 0 == disable PSR/PR
> 1 == Allow PSR1 and PR full frame update
> 2 == allow PSR1/PSR2 and PR Selective Update
> 
> enable_psr2_sel_fetch
> 
> 0 == disable selective fetch for PSR and PR
> 1 (default) == allow selective fetch for PSR PR
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_params.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
> b/drivers/gpu/drm/i915/display/intel_display_params.c
> index 11e03cfb774d..1c5e20ec7f1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -102,7 +102,8 @@ intel_display_param_named_unsafe(enable_fbc, int,
> 0400,
> 
>  intel_display_param_named_unsafe(enable_psr, int, 0400,
>  	"Enable PSR "
> -	"(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) "
> +	"(0=disabled, 1=enable up to PSR1 and Panel Replay full frame
> update, "
> +	"2=enable up to PSR2 and Panel Replay Selective Update) "
>  	"Default: -1 (use per-chip default)");
> 
>  intel_display_param_named(psr_safest_params, bool, 0400, @@ -112,7
> +113,7 @@ intel_display_param_named(psr_safest_params, bool, 0400,
>  	"Default: 0");
> 
>  intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400,
> -	"Enable PSR2 selective fetch "
> +	"Enable PSR2 and Panel Replay selective fetch "
>  	"(0=disabled, 1=enabled) "
>  	"Default: 1");
> 
> --
> 2.34.1

[PATCH v3 20/21] drm/i915/psr: Split intel_psr2_config_valid for panel replay

[Jouni Högander]

Part of intel_psr2_config_valid is valid for panel replay. rename it as
intel_sel_update_config_valid. Split psr2 specific part and name it as
intel_psr2_config_valid.

v2:
  - use psr2_global_enabled for panel replay as well
  - goto unsupported instead of return when global enabled check fails

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 70 +++++++++++++++---------
 1 file changed, 43 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d28a3a1e945b..40f71a0726fe 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1325,11 +1325,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!psr2_global_enabled(intel_dp)) {
-		drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
-		return false;
-	}
-
 	/*
 	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
 	 * resolution requires DSC to be enabled, priority is given to DSC
@@ -1342,12 +1337,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (crtc_state->crc_enabled) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
-		return false;
-	}
-
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		psr_max_h = 5120;
 		psr_max_v = 3200;
@@ -1398,30 +1387,57 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
-		if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
-		    !HAS_PSR_HW_TRACKING(dev_priv)) {
-			drm_dbg_kms(&dev_priv->drm,
-				    "PSR2 not enabled, selective fetch not valid and no HW tracking available\n");
-			return false;
-		}
-	}
-
-	if (!psr2_granularity_check(intel_dp, crtc_state)) {
-		drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
-		goto unsupported;
-	}
-
 	if (!crtc_state->enable_psr2_sel_fetch &&
 	    (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 			    crtc_hdisplay, crtc_vdisplay,
 			    psr_max_h, psr_max_v);
-		goto unsupported;
+		return false;
 	}
 
 	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
+
+	return true;
+}
+
+static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
+					  struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (HAS_PSR2_SEL_FETCH(dev_priv) &&
+	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
+	    !HAS_PSR_HW_TRACKING(dev_priv)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Selective update not enabled, selective fetch not valid and no HW tracking available\n");
+		goto unsupported;
+	}
+
+	if (!psr2_global_enabled(intel_dp)) {
+		drm_dbg_kms(&dev_priv->drm, "Selective update disabled by flag\n");
+		goto unsupported;
+	}
+
+	if (crtc_state->has_psr && !intel_psr2_config_valid(intel_dp, crtc_state))
+		goto unsupported;
+
+	if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 ||
+					     !intel_dp->psr.sink_panel_replay_su_support))
+		goto unsupported;
+
+	if (crtc_state->crc_enabled) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Selective update not enabled because it would inhibit pipe CRC calculation\n");
+		goto unsupported;
+	}
+
+	if (!psr2_granularity_check(intel_dp, crtc_state)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Selective update not enabled, SU granularity not compatible\n");
+		goto unsupported;
+	}
+
 	return true;
 
 unsupported:
@@ -1492,7 +1508,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	if (!crtc_state->has_psr)
 		return;
 
-	crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state);
+	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
-- 
2.34.1

[PATCH v3 21/21] drm/i915/psr: Add panel replay sel update support to debugfs interface

[Jouni Högander]

Add panel replay selective update support to debugfs status interface. In
case of sink supporting panel replay we will print out:

Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes

and PSR mode will look like this if printing out enabled panel replay
selective update:

PSR mode: Panel Replay Selective Update Enabled

Current PSR and panel replay printouts remain same.

Cc: Kunal Joshi <kunal1.joshi@intel.com>

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 40f71a0726fe..dbb06d10b8c3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3265,7 +3265,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 
 	if (psr->sink_support)
 		seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
-	seq_printf(m, ", Panel Replay = %s\n", str_yes_no(psr->sink_panel_replay_support));
+	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
+	seq_printf(m, ", Panel Replay Selective Update = %s\n",
+		   str_yes_no(psr->sink_panel_replay_su_support));
 
 	if (!(psr->sink_support || psr->sink_panel_replay_support))
 		return 0;
@@ -3274,9 +3276,10 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 	mutex_lock(&psr->lock);
 
 	if (psr->panel_replay_enabled)
-		status = "Panel Replay Enabled";
+		status = psr->sel_update_enabled ? "Panel Replay Selective Update Enabled" :
+			"Panel Replay Enabled";
 	else if (psr->enabled)
-		status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 enabled";
+		status = psr->sel_update_enabled ? "PSR2" : "PSR1";
 	else
 		status = "disabled";
 	seq_printf(m, "PSR mode: %s\n", status);
-- 
2.34.1

✗ Fi.CI.CHECKPATCH: warning for Panel replay selective update support (rev3)

[Patchwork]

== Series Details ==

Series: Panel replay selective update support (rev3)
URL   : https://patchwork.freedesktop.org/series/128193/
State : warning

== Summary ==

Error: dim checkpatch failed
024bac5cc251 drm/i915/psr: Add some documentation of variables used in psr code
ff9290e61f6b drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well
-:43: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#43: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1443:
+		pipe_config->has_psr = pipe_config->has_panel_replay = true;

total: 0 errors, 0 warnings, 1 checks, 30 lines checked
35345f77d4e3 drm/i915/psr: Intel_psr_pause/resume needs to support panel replay
63f9e063a416 drm/i915/psr: Rename intel_psr_enabled
93cbedb1374e drm/i915/psr: Do not update phy power state in case of panel replay
9c075f08e95c drm/i915/psr: Check possible errors for panel replay as well
2671160600c2 drm/i915/psr: Do not write registers/bits not applicable for panel replay
1f93c318a964 drm/i915/psr: Unify panel replay enable/disable sink
4805e61a988c drm/i915/psr: Panel replay has to be enabled before link training
-:79: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects?
#79: FILE: drivers/gpu/drm/i915/display/intel_psr.h:24:
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+				    (intel_dp)->psr.source_panel_replay_support)

total: 0 errors, 0 warnings, 1 checks, 50 lines checked
858a9894c10d drm/i915/psr: Rename has_psr2 as has_sel_update
8c7b152a0a07 drm/i915/psr: Modify VSC SDP calculation to support panel replay + su
0ba693cc169a drm/i915/psr: Rename psr2_enabled as sel_update_enabled
ce8e3ea6b398 drm/panelreplay: dpcd register definition for panelreplay SU
ec65f6a9c8f4 drm/i915/psr: Detect panel replay selective update support
8ae142b40f6d drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
0db819ecf6d6 drm/i915/psr: Ensure early transport is not enabled for panel replay
82319d5ba49b drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
6e27abef4672 drm/i915/psr: Do not apply workarounds in case of panel replay
4f8a9796833a drm/i915/psr: Update PSR module parameter descriptions
7690dec7cafd drm/i915/psr: Split intel_psr2_config_valid for panel replay
34faa9fbc0aa drm/i915/psr: Add panel replay sel update support to debugfs interface
-:13: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#13: 
Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes

total: 0 errors, 1 warnings, 0 checks, 22 lines checked

✗ Fi.CI.SPARSE: warning for Panel replay selective update support (rev3)

[Patchwork]

== Series Details ==

Series: Panel replay selective update support (rev3)
URL   : https://patchwork.freedesktop.org/series/128193/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ Fi.CI.BAT: success for Panel replay selective update support (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9831 bytes --]

== Series Details ==

Series: Panel replay selective update support (rev3)
URL   : https://patchwork.freedesktop.org/series/128193/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14145 -> Patchwork_128193v3
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/index.html

Participating hosts (37 -> 37)
------------------------------

  Additional (1): bat-mtlp-8 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_128193v3:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_psr@psr-primary-page-flip}:
    - {bat-rpls-3}:       [SKIP][1] ([i915#9673] / [i915#9732]) -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/bat-rpls-3/igt@kms_psr@psr-primary-page-flip.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-rpls-3/igt@kms_psr@psr-primary-page-flip.html

  
Known issues
------------

  Here are the changes found in Patchwork_128193v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-mtlp-8:         NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-8:         NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-mtlp-8:         NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@i915_pm_rps@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-mtlp-8:         NOTRUN -> [SKIP][9] ([i915#6645])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][10] ([i915#5190])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][11] ([i915#4212]) +8 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][12] ([i915#4213]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][13] ([i915#3555] / [i915#3840] / [i915#9159])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-mtlp-8:         NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-8:         NOTRUN -> [SKIP][15] ([i915#5274])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-mtlp-8:         NOTRUN -> [SKIP][16] ([i915#3555] / [i915#8809])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-mtlp-8:         NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-mtlp-8:         NOTRUN -> [SKIP][18] ([i915#3708]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - bat-jsl-3:          [INCOMPLETE][19] ([i915#9883]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_pm_rpm@module-reload:
    - bat-atsm-1:         [SKIP][21] -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/bat-atsm-1/igt@i915_pm_rpm@module-reload.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-atsm-1/igt@i915_pm_rpm@module-reload.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-jsl-3:          [FAIL][23] ([i915#10031]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#10031]: https://gitlab.freedesktop.org/drm/intel/issues/10031
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9883]: https://gitlab.freedesktop.org/drm/intel/issues/9883


Build changes
-------------

  * Linux: CI_DRM_14145 -> Patchwork_128193v3

  CI-20190529: 20190529
  CI_DRM_14145: ad8fc2d4a396b1123c48340004d8c35dd0320817 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7683: 7683
  Patchwork_128193v3: ad8fc2d4a396b1123c48340004d8c35dd0320817 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

cdbc64c5f366 drm/i915/psr: Add panel replay sel update support to debugfs interface
b439a77daf80 drm/i915/psr: Split intel_psr2_config_valid for panel replay
3e866741dc0f drm/i915/psr: Update PSR module parameter descriptions
a00b6fa07c1e drm/i915/psr: Do not apply workarounds in case of panel replay
ca6a8f6387c3 drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
be5b22c43681 drm/i915/psr: Ensure early transport is not enabled for panel replay
9966967fcd35 drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
a9d21a197690 drm/i915/psr: Detect panel replay selective update support
3d5c81eb8328 drm/panelreplay: dpcd register definition for panelreplay SU
8f04cbb40a76 drm/i915/psr: Rename psr2_enabled as sel_update_enabled
3e0ceb6f5918 drm/i915/psr: Modify VSC SDP calculation to support panel replay + su
179900851b07 drm/i915/psr: Rename has_psr2 as has_sel_update
4a1ae9c961b5 drm/i915/psr: Panel replay has to be enabled before link training
e0711bf3972c drm/i915/psr: Unify panel replay enable/disable sink
79c89d9da1f7 drm/i915/psr: Do not write registers/bits not applicable for panel replay
f4004de5e812 drm/i915/psr: Check possible errors for panel replay as well
439182bdca2c drm/i915/psr: Do not update phy power state in case of panel replay
1b3630931e79 drm/i915/psr: Rename intel_psr_enabled
1f0958a09ea2 drm/i915/psr: Intel_psr_pause/resume needs to support panel replay
1264efedfbbd drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well
bfa2984a58b1 drm/i915/psr: Add some documentation of variables used in psr code

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/index.html

[-- Attachment #2: Type: text/html, Size: 11206 bytes --]

✗ Fi.CI.IGT: failure for Panel replay selective update support (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 95290 bytes --]

== Series Details ==

Series: Panel replay selective update support (rev3)
URL   : https://patchwork.freedesktop.org/series/128193/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14145_full -> Patchwork_128193v3_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_128193v3_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_128193v3_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/index.html

Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_128193v3_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_capture@pi@ccs3:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-7/igt@gem_exec_capture@pi@ccs3.html

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset@pipe-d:
    - shard-dg1:          [PASS][2] -> [INCOMPLETE][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg1-13/igt@kms_busy@extended-modeset-hang-newfb-with-reset@pipe-d.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-14/igt@kms_busy@extended-modeset-hang-newfb-with-reset@pipe-d.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_content_protection@lic-type-0}:
    - shard-dg2:          NOTRUN -> [SKIP][4] +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-1/igt@kms_content_protection@lic-type-0.html

  * {igt@kms_content_protection@lic-type-1}:
    - shard-snb:          [SKIP][5] ([fdo#109271]) -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-snb5/igt@kms_content_protection@lic-type-1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-snb7/igt@kms_content_protection@lic-type-1.html

  
Known issues
------------

  Here are the changes found in Patchwork_128193v3_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@render-ccs:
    - shard-dg2:          NOTRUN -> [FAIL][7] ([i915#6122])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@api_intel_bb@render-ccs.html

  * igt@device_reset@cold-reset-bound:
    - shard-rkl:          NOTRUN -> [SKIP][8] ([i915#7701])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@device_reset@cold-reset-bound.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-dg2:          NOTRUN -> [SKIP][9] ([i915#7701])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@drm_fdinfo@busy-hang@bcs0:
    - shard-dg2:          NOTRUN -> [SKIP][10] ([i915#8414]) +10 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@drm_fdinfo@busy-hang@bcs0.html

  * igt@drm_fdinfo@busy@bcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][11] ([i915#8414]) +12 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@drm_fdinfo@busy@bcs0.html

  * igt@gem_bad_reloc@negative-reloc-lut:
    - shard-dg1:          NOTRUN -> [SKIP][12] ([i915#3281]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gem_bad_reloc@negative-reloc-lut.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-mtlp:         NOTRUN -> [SKIP][13] ([i915#3555])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [PASS][14] -> [INCOMPLETE][15] ([i915#7297])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg2-2/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-dg2:          NOTRUN -> [SKIP][16] ([i915#7697]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-dg1:          NOTRUN -> [SKIP][17] ([fdo#109314])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_persistence@engines-cleanup:
    - shard-snb:          NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1099])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-snb5/igt@gem_ctx_persistence@engines-cleanup.html

  * igt@gem_ctx_persistence@heartbeat-stop:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#8555]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
    - shard-dg2:          NOTRUN -> [SKIP][20] ([i915#5882]) +9 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][21] ([i915#5882]) +5 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#280])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#280]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_balancer@bonded-false-hang:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#4812]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@gem_exec_balancer@bonded-false-hang.html

  * igt@gem_exec_balancer@bonded-pair:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#4771])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@gem_exec_balancer@bonded-pair.html

  * igt@gem_exec_balancer@bonded-sync:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#4771])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@gem_exec_balancer@bonded-sync.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#4036])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-mtlp:         NOTRUN -> [SKIP][28] ([i915#6334])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@many-4k-zero:
    - shard-tglu:         NOTRUN -> [FAIL][29] ([i915#9606])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@gem_exec_capture@many-4k-zero.html

  * igt@gem_exec_fair@basic-none:
    - shard-dg1:          NOTRUN -> [SKIP][30] ([i915#3539] / [i915#4852]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gem_exec_fair@basic-none.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][31] ([i915#2842]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace:
    - shard-mtlp:         NOTRUN -> [SKIP][32] ([i915#4473] / [i915#4771]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@gem_exec_fair@basic-pace.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][33] ([i915#2842]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#3539]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gem_exec_fair@basic-pace-solo.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-rkl:          [PASS][35] -> [FAIL][36] ([i915#2842]) +2 other tests fail
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-rkl-6/igt@gem_exec_fair@basic-pace@vecs0.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-3/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fence@submit:
    - shard-mtlp:         NOTRUN -> [SKIP][37] ([i915#4812]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gem_exec_fence@submit.html

  * igt@gem_exec_flush@basic-wb-ro-before-default:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#3539] / [i915#4852]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@gem_exec_flush@basic-wb-ro-before-default.html

  * igt@gem_exec_gttfill@multigpu-basic:
    - shard-mtlp:         NOTRUN -> [SKIP][39] ([i915#7697]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@gem_exec_gttfill@multigpu-basic.html

  * igt@gem_exec_params@secure-non-root:
    - shard-dg2:          NOTRUN -> [SKIP][40] ([fdo#112283]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gem_exec_params@secure-non-root.html
    - shard-rkl:          NOTRUN -> [SKIP][41] ([fdo#112283])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@gem_exec_params@secure-non-root.html

  * igt@gem_exec_reloc@basic-active:
    - shard-dg2:          NOTRUN -> [SKIP][42] ([i915#3281]) +11 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][43] ([i915#3281]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gem_exec_reloc@basic-write-wc-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][44] ([i915#3281]) +14 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gem_exec_reloc@basic-write-wc-noreloc.html

  * igt@gem_exec_schedule@preempt-queue-chain:
    - shard-mtlp:         NOTRUN -> [SKIP][45] ([i915#4537] / [i915#4812]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@gem_exec_schedule@preempt-queue-chain.html

  * igt@gem_exec_suspend@basic-s4-devices@smem:
    - shard-rkl:          NOTRUN -> [ABORT][46] ([i915#7975] / [i915#8213]) +1 other test abort
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-4/igt@gem_exec_suspend@basic-s4-devices@smem.html

  * igt@gem_fence_thrash@bo-copy:
    - shard-dg2:          NOTRUN -> [SKIP][47] ([i915#4860]) +4 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@gem_fence_thrash@bo-copy.html

  * igt@gem_fence_thrash@bo-write-verify-x:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#4860])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gem_fence_thrash@bo-write-verify-x.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-mtlp:         NOTRUN -> [SKIP][49] ([i915#4860])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#4613] / [i915#7582])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@massive-random:
    - shard-mtlp:         NOTRUN -> [SKIP][51] ([i915#4613]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@gem_lmem_swapping@massive-random.html

  * igt@gem_lmem_swapping@random:
    - shard-glk:          NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#4613]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-glk4/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-rkl:          NOTRUN -> [SKIP][53] ([i915#4613]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_lmem_swapping@verify-random-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][54] ([i915#4613])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@gem_lmem_swapping@verify-random-ccs.html

  * igt@gem_media_fill@media-fill:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#8289])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@gem_media_fill@media-fill.html

  * igt@gem_mmap_gtt@cpuset-medium-copy-odd:
    - shard-mtlp:         NOTRUN -> [SKIP][56] ([i915#4077]) +16 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html

  * igt@gem_mmap_gtt@hang:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#4077]) +23 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gem_mmap_gtt@hang.html

  * igt@gem_mmap_gtt@pf-nonblock:
    - shard-dg1:          NOTRUN -> [SKIP][58] ([i915#4077]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gem_mmap_gtt@pf-nonblock.html

  * igt@gem_mmap_wc@write:
    - shard-mtlp:         NOTRUN -> [SKIP][59] ([i915#4083]) +4 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@gem_mmap_wc@write.html

  * igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
    - shard-dg1:          NOTRUN -> [SKIP][60] ([i915#4083]) +5 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html

  * igt@gem_mmap_wc@write-prefaulted:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#4083]) +6 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@gem_mmap_wc@write-prefaulted.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-dg1:          NOTRUN -> [SKIP][62] ([i915#3282]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-dg2:          NOTRUN -> [SKIP][63] ([i915#3282]) +9 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_pread@display:
    - shard-mtlp:         NOTRUN -> [SKIP][64] ([i915#3282]) +3 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@gem_pread@display.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-tglu:         NOTRUN -> [SKIP][65] ([i915#4270]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@display-protected-crc:
    - shard-rkl:          NOTRUN -> [SKIP][66] ([i915#4270]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-mtlp:         NOTRUN -> [SKIP][67] ([i915#4270]) +3 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-dg2:          NOTRUN -> [SKIP][68] ([i915#4270]) +2 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_readwrite@beyond-eob:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#3282]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@gem_readwrite@beyond-eob.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][70] ([i915#8428]) +5 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#8411])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#4079])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_set_tiling_vs_gtt:
    - shard-dg1:          NOTRUN -> [SKIP][73] ([i915#4079])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gem_set_tiling_vs_gtt.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-mtlp:         NOTRUN -> [SKIP][74] ([i915#4079]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#4885]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_spin_batch@spin-all-new:
    - shard-dg2:          NOTRUN -> [FAIL][76] ([i915#5889])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@gem_spin_batch@spin-all-new.html

  * igt@gem_unfence_active_buffers:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#4879])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][78] ([i915#3297]) +5 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][79] ([i915#3297])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#3297] / [i915#4880])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-1/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#3297])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gem_userptr_blits@sd-probe:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#3297] / [i915#4958])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@gem_userptr_blits@sd-probe.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-mtlp:         NOTRUN -> [SKIP][83] ([i915#3297]) +3 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen7_exec_parse@basic-allocation:
    - shard-dg1:          NOTRUN -> [SKIP][84] ([fdo#109289])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gen7_exec_parse@basic-allocation.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([fdo#109289]) +8 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@gen7_exec_parse@bitmasks.html

  * igt@gen7_exec_parse@oacontrol-tracking:
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([fdo#109289]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@gen7_exec_parse@oacontrol-tracking.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-tglu:         NOTRUN -> [SKIP][87] ([i915#2527] / [i915#2856])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-dg1:          NOTRUN -> [SKIP][88] ([i915#2527])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-mtlp:         NOTRUN -> [SKIP][89] ([i915#2856]) +2 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#2527]) +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#2856]) +4 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][92] -> [INCOMPLETE][93] ([i915#9820] / [i915#9849])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-rkl-6/igt@i915_module_load@reload-with-fault-injection.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_module_load@resize-bar:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#6412])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@i915_module_load@resize-bar.html

  * igt@i915_pipe_stress@stress-xrgb8888-ytiled:
    - shard-mtlp:         NOTRUN -> [SKIP][95] ([i915#8436])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-tglu:         NOTRUN -> [SKIP][96] ([i915#6590])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([fdo#109293] / [fdo#109506])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_pm_rpm@gem-mmap-type@gtt-smem0:
    - shard-mtlp:         NOTRUN -> [SKIP][98] ([i915#8431])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@i915_pm_rpm@gem-mmap-type@gtt-smem0.html

  * igt@i915_pm_rps@basic-api:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#6621])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@i915_pm_rps@basic-api.html

  * igt@i915_pm_rps@reset:
    - shard-mtlp:         NOTRUN -> [FAIL][100] ([i915#8346])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@i915_pm_rps@reset.html

  * igt@i915_pm_rps@thresholds-idle@gt0:
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#8925]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@i915_pm_rps@thresholds-idle@gt0.html

  * igt@i915_pm_rps@thresholds-park@gt0:
    - shard-mtlp:         NOTRUN -> [SKIP][102] ([i915#8925])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@i915_pm_rps@thresholds-park@gt0.html

  * igt@i915_pm_rps@thresholds-park@gt1:
    - shard-mtlp:         NOTRUN -> [SKIP][103] ([i915#3555] / [i915#8925])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@i915_pm_rps@thresholds-park@gt1.html

  * igt@i915_power@sanity:
    - shard-mtlp:         NOTRUN -> [SKIP][104] ([i915#7984])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@i915_power@sanity.html

  * igt@i915_query@query-topology-known-pci-ids:
    - shard-mtlp:         NOTRUN -> [SKIP][105] ([fdo#109303])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@i915_query@query-topology-known-pci-ids.html
    - shard-dg2:          NOTRUN -> [SKIP][106] ([fdo#109303])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@i915_query@query-topology-known-pci-ids.html

  * igt@i915_query@query-topology-unsupported:
    - shard-rkl:          NOTRUN -> [SKIP][107] ([fdo#109302])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@i915_query@query-topology-unsupported.html

  * igt@i915_selftest@mock@memory_region:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][108] ([i915#9311])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@i915_selftest@mock@memory_region.html

  * igt@intel_hwmon@hwmon-read:
    - shard-mtlp:         NOTRUN -> [SKIP][109] ([i915#7707])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#4212])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][111] ([i915#4212])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#4215] / [i915#5190])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][113] -> [FAIL][114] ([i915#2521])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-glk7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-glk1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][115] ([i915#8709]) +7 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][116] ([i915#6228])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#9531])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][118] ([i915#4538] / [i915#5286])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-mtlp:         NOTRUN -> [FAIL][119] ([i915#5138])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-tglu:         NOTRUN -> [SKIP][120] ([i915#5286])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][121] ([i915#5286]) +3 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-snb:          NOTRUN -> [SKIP][122] ([fdo#109271]) +38 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-snb5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [PASS][123] -> [FAIL][124] ([i915#5138])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-mtlp:         NOTRUN -> [SKIP][125] ([fdo#111614]) +5 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([fdo#111614] / [i915#3638])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([fdo#111614]) +6 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][128] ([i915#3638]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-tglu:         NOTRUN -> [SKIP][129] ([fdo#111614])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-mtlp:         NOTRUN -> [SKIP][130] ([i915#6187]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#5190]) +23 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([fdo#111615])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-mtlp:         NOTRUN -> [SKIP][133] ([fdo#111615]) +9 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#4538] / [i915#5190]) +9 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([fdo#110723]) +3 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg1:          NOTRUN -> [SKIP][136] ([fdo#111615])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_joiner@2x-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][137] ([i915#2705])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_big_joiner@2x-modeset.html

  * igt@kms_big_joiner@basic:
    - shard-mtlp:         NOTRUN -> [SKIP][138] ([i915#2705])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y-tiled-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][139] ([i915#5354] / [i915#6095]) +14 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_ccs@pipe-a-crc-primary-basic-y-tiled-ccs.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-tglu:         NOTRUN -> [SKIP][140] ([i915#5354] / [i915#6095]) +10 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_ccs@pipe-b-bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y-tiled-gen12-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#5354]) +129 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-y-tiled-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][142] ([i915#5354] / [i915#6095]) +50 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_ccs@pipe-c-crc-primary-basic-y-tiled-ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
    - shard-glk:          NOTRUN -> [SKIP][143] ([fdo#109271]) +151 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-glk4/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@pipe-d-bad-rotation-90-4-tiled-dg2-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][144] ([i915#5354]) +18 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_ccs@pipe-d-bad-rotation-90-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-y-tiled-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][145] ([i915#5354] / [i915#6095]) +10 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_ccs@pipe-d-missing-ccs-buffer-y-tiled-ccs.html

  * igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#7213]) +3 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2.html

  * igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#4087]) +3 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html

  * igt@kms_chamelium_audio@hdmi-audio:
    - shard-dg2:          NOTRUN -> [SKIP][148] ([i915#7828]) +17 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@kms_chamelium_audio@hdmi-audio.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([fdo#111827])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg1:          NOTRUN -> [SKIP][150] ([fdo#111827])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-dg2:          NOTRUN -> [SKIP][151] ([fdo#111827])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-mtlp:         NOTRUN -> [SKIP][152] ([fdo#111827])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
    - shard-tglu:         NOTRUN -> [SKIP][153] ([i915#7828])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html

  * igt@kms_chamelium_frames@vga-frame-dump:
    - shard-dg1:          NOTRUN -> [SKIP][154] ([i915#7828]) +1 other test skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_chamelium_frames@vga-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#7828]) +3 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_chamelium_hpd@vga-hpd:
    - shard-mtlp:         NOTRUN -> [SKIP][156] ([i915#7828]) +9 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@kms_chamelium_hpd@vga-hpd.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][157] ([i915#7118]) +1 other test skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@content-type-change:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#9424])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-4/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#3299]) +1 other test skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-mtlp:         NOTRUN -> [SKIP][160] ([i915#8063] / [i915#9433])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@uevent:
    - shard-dg1:          NOTRUN -> [SKIP][161] ([i915#7116])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-tglu:         NOTRUN -> [SKIP][162] ([i915#3555])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-onscreen-32x10:
    - shard-mtlp:         NOTRUN -> [SKIP][163] ([i915#3555] / [i915#8814]) +3 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_cursor_crc@cursor-onscreen-32x10.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#3359]) +3 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-128x42:
    - shard-mtlp:         NOTRUN -> [SKIP][165] ([i915#8814]) +3 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-dg2:          NOTRUN -> [SKIP][166] ([i915#3555]) +12 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-mtlp:         NOTRUN -> [SKIP][167] ([i915#3359]) +1 other test skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][168] ([fdo#111825]) +5 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][169] ([i915#9809]) +5 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][170] ([i915#4213]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - shard-dg2:          NOTRUN -> [SKIP][171] ([i915#4103] / [i915#4213])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][172] ([fdo#109274] / [i915#5354]) +7 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg1:          NOTRUN -> [SKIP][173] ([i915#4103] / [i915#4213])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-mtlp:         NOTRUN -> [SKIP][174] ([i915#9833])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][175] ([i915#9227])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#9723])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][177] ([i915#9723])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-13/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#9833])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-mtlp:         NOTRUN -> [SKIP][179] ([i915#8588])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][180] ([i915#3804])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg1:          NOTRUN -> [SKIP][181] ([i915#3555]) +1 other test skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_dp_aux_dev:
    - shard-rkl:          NOTRUN -> [SKIP][182] ([i915#1257])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_dp_aux_dev.html

  * igt@kms_draw_crc@draw-method-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][183] ([i915#8812]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_draw_crc@draw-method-mmap-wc.html

  * igt@kms_dsc@dsc-basic:
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#3555] / [i915#3840])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-4/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-tglu:         NOTRUN -> [SKIP][185] ([i915#3555] / [i915#3840])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-dg2:          NOTRUN -> [SKIP][186] ([i915#3555] / [i915#3840])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-mtlp:         NOTRUN -> [SKIP][187] ([i915#3555] / [i915#3840] / [i915#9053])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2:          NOTRUN -> [SKIP][188] ([i915#3469])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@display-4x:
    - shard-mtlp:         NOTRUN -> [SKIP][189] ([i915#1839]) +1 other test skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@kms_feature_discovery@display-4x.html

  * igt@kms_fence_pin_leak:
    - shard-mtlp:         NOTRUN -> [SKIP][190] ([i915#4881])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_fence_pin_leak.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][191] ([i915#3637]) +10 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][192] ([fdo#111767] / [i915#3637])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-dg2:          NOTRUN -> [SKIP][193] ([fdo#109274]) +10 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][194] ([fdo#109274] / [fdo#111767])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][195] ([fdo#109274] / [i915#3637])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][196] ([i915#8381]) +1 other test skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][197] ([i915#2672])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][198] ([i915#2672]) +2 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][199] ([i915#3555] / [i915#8810]) +2 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][200] ([i915#2587] / [i915#2672])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][201] ([i915#2587] / [i915#2672])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][202] ([i915#2672]) +2 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][203] ([i915#8810]) +1 other test skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][204] ([i915#2672] / [i915#3555]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [FAIL][205] ([i915#6880])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][206] ([i915#8708]) +8 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][207] ([fdo#109280]) +8 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-snb:          [PASS][208] -> [SKIP][209] ([fdo#109271]) +12 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][210] ([i915#1825]) +33 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
    - shard-dg1:          NOTRUN -> [SKIP][211] ([fdo#111825]) +10 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][212] ([fdo#111825] / [i915#1825]) +20 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][213] ([i915#8708]) +41 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][214] ([i915#3458]) +3 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-dg2:          NOTRUN -> [SKIP][215] ([i915#10070])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][216] ([fdo#110189]) +3 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][217] ([i915#3023]) +13 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][218] ([i915#3458]) +22 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][219] ([i915#8708]) +1 other test skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@static-toggle:
    - shard-mtlp:         NOTRUN -> [SKIP][220] ([i915#3555] / [i915#8228]) +1 other test skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][221] ([i915#3555] / [i915#8228]) +2 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg1:          NOTRUN -> [SKIP][222] ([i915#1839]) +1 other test skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
    - shard-rkl:          NOTRUN -> [SKIP][223] ([fdo#109289]) +2 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html

  * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][224] ([i915#4573]) +1 other test fail
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-glk8/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-x@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][225] ([i915#3582]) +7 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_plane_lowres@tiling-x@pipe-a-edp-1.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-mtlp:         NOTRUN -> [SKIP][226] ([i915#3555] / [i915#8821])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-mtlp:         NOTRUN -> [SKIP][227] ([i915#3555] / [i915#8806])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_plane_multiple@tiling-yf.html
    - shard-dg2:          NOTRUN -> [SKIP][228] ([i915#3555] / [i915#8806])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][229] ([i915#9423]) +11 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][230] ([i915#9423]) +3 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][231] ([i915#9423]) +3 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#5176] / [i915#9423]) +1 other test skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][233] ([i915#5176] / [i915#9423]) +3 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-12/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][234] ([i915#5235]) +12 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b-edp-1.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][235] ([i915#5235]) +7 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][236] ([i915#5235] / [i915#9423]) +19 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][237] ([i915#5235]) +11 other tests skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][238] ([i915#3555] / [i915#5235]) +2 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d-edp-1.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg1:          NOTRUN -> [SKIP][239] ([i915#9685])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-dpms-negative:
    - shard-mtlp:         NOTRUN -> [SKIP][240] ([i915#9293])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_pm_dc@dc5-dpms-negative.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         NOTRUN -> [FAIL][241] ([i915#9295])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-mtlp:         NOTRUN -> [FAIL][242] ([i915#9298])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-8/igt@kms_pm_dc@dc6-psr.html
    - shard-dg2:          NOTRUN -> [SKIP][243] ([i915#9685]) +1 other test skip
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][244] ([i915#9340])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg2:          NOTRUN -> [SKIP][245] ([i915#8430])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [PASS][246] -> [SKIP][247] ([i915#9519]) +1 other test skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-rkl-1/igt@kms_pm_rpm@dpms-non-lpsp.html
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-7/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][248] ([i915#9519]) +1 other test skip
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-mtlp:         NOTRUN -> [SKIP][249] ([i915#9519])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_pm_rpm@modeset-non-lpsp.html
    - shard-dg2:          [PASS][250] -> [SKIP][251] ([i915#9519])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg2-3/igt@kms_pm_rpm@modeset-non-lpsp.html
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][252] ([i915#6524])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-dg2:          NOTRUN -> [SKIP][253] ([i915#6524] / [i915#6805])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-rkl:          NOTRUN -> [SKIP][254] ([fdo#111068] / [i915#9683])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
    - shard-tglu:         NOTRUN -> [SKIP][255] ([fdo#111068] / [i915#9683])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg1:          NOTRUN -> [SKIP][256] ([fdo#111068] / [i915#9683])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2:          NOTRUN -> [SKIP][257] ([i915#9683]) +5 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-mtlp:         NOTRUN -> [SKIP][258] ([i915#4235]) +3 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-dg1:          NOTRUN -> [SKIP][259] ([i915#4884])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][260] ([i915#4235] / [i915#5190]) +1 other test skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg1:          NOTRUN -> [SKIP][261] ([fdo#111615] / [i915#5289])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-dg2:          NOTRUN -> [SKIP][262] ([i915#4235])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-rkl:          NOTRUN -> [SKIP][263] ([i915#3555]) +1 other test skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-rkl:          NOTRUN -> [SKIP][264] ([i915#8623])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@flipline:
    - shard-mtlp:         NOTRUN -> [SKIP][265] ([i915#3555] / [i915#8808]) +1 other test skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@kms_vrr@flipline.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg1:          NOTRUN -> [SKIP][266] ([i915#2437])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][267] ([i915#2437] / [i915#9412])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-glk:          NOTRUN -> [SKIP][268] ([fdo#109271] / [i915#2437])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-glk3/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2:          NOTRUN -> [SKIP][269] ([i915#2437])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-mtlp:         NOTRUN -> [SKIP][270] ([i915#2437]) +1 other test skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][271] ([i915#2436])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf@global-sseu-config-invalid:
    - shard-mtlp:         NOTRUN -> [SKIP][272] ([i915#7387])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@perf@global-sseu-config-invalid.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-mtlp:         NOTRUN -> [SKIP][273] ([i915#8850])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@perf_pmu@cpu-hotplug.html

  * igt@perf_pmu@event-wait@rcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][274] ([i915#3555] / [i915#8807])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@perf_pmu@event-wait@rcs0.html

  * igt@perf_pmu@faulting-read@gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][275] ([i915#8440])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@perf_pmu@faulting-read@gtt.html

  * igt@perf_pmu@module-unload:
    - shard-dg2:          NOTRUN -> [FAIL][276] ([i915#5793])
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@perf_pmu@module-unload.html

  * igt@prime_udl:
    - shard-mtlp:         NOTRUN -> [SKIP][277] ([fdo#109291])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@prime_udl.html

  * igt@prime_vgem@basic-read:
    - shard-dg2:          NOTRUN -> [SKIP][278] ([i915#3291] / [i915#3708])
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@coherency-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][279] ([i915#3708] / [i915#4077]) +1 other test skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-6/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-dg2:          NOTRUN -> [SKIP][280] ([i915#3708])
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-10/igt@prime_vgem@fence-flip-hang.html

  * igt@prime_vgem@fence-write-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][281] ([i915#3708]) +2 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-mtlp:         NOTRUN -> [SKIP][282] ([i915#9917])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@sriov_basic@bind-unbind-vf.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - shard-dg2:          NOTRUN -> [SKIP][283] ([i915#9917])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@syncobj_timeline@invalid-wait-zero-handles:
    - shard-dg2:          NOTRUN -> [FAIL][284] ([i915#9781])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@syncobj_timeline@invalid-wait-zero-handles.html

  * igt@syncobj_wait@invalid-wait-zero-handles:
    - shard-glk:          NOTRUN -> [FAIL][285] ([i915#9779])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-glk3/igt@syncobj_wait@invalid-wait-zero-handles.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-mtlp:         NOTRUN -> [SKIP][286] ([i915#4818])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-2/igt@tools_test@sysfs_l3_parity.html

  * igt@v3d/v3d_submit_cl@job-perfmon:
    - shard-tglu:         NOTRUN -> [SKIP][287] ([fdo#109315] / [i915#2575]) +2 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@v3d/v3d_submit_cl@job-perfmon.html

  * igt@v3d/v3d_submit_cl@simple-flush-cache:
    - shard-dg2:          NOTRUN -> [SKIP][288] ([i915#2575]) +19 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-3/igt@v3d/v3d_submit_cl@simple-flush-cache.html

  * igt@v3d/v3d_submit_cl@single-in-sync:
    - shard-rkl:          NOTRUN -> [SKIP][289] ([fdo#109315]) +8 other tests skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@v3d/v3d_submit_cl@single-in-sync.html

  * igt@v3d/v3d_submit_csd@bad-pad:
    - shard-dg1:          NOTRUN -> [SKIP][290] ([i915#2575]) +2 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@v3d/v3d_submit_csd@bad-pad.html

  * igt@v3d/v3d_wait_bo@map-bo-0ns:
    - shard-mtlp:         NOTRUN -> [SKIP][291] ([i915#2575]) +12 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@v3d/v3d_wait_bo@map-bo-0ns.html

  * igt@vc4/vc4_purgeable_bo@access-purged-bo-mem:
    - shard-mtlp:         NOTRUN -> [SKIP][292] ([i915#7711]) +8 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@vc4/vc4_purgeable_bo@access-purged-bo-mem.html

  * igt@vc4/vc4_tiling@get-bad-flags:
    - shard-rkl:          NOTRUN -> [SKIP][293] ([i915#7711]) +4 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-4/igt@vc4/vc4_tiling@get-bad-flags.html

  * igt@vc4/vc4_wait_bo@bad-bo:
    - shard-dg1:          NOTRUN -> [SKIP][294] ([i915#7711]) +2 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-16/igt@vc4/vc4_wait_bo@bad-bo.html

  * igt@vc4/vc4_wait_bo@used-bo-1ns:
    - shard-tglu:         NOTRUN -> [SKIP][295] ([i915#2575]) +1 other test skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-9/igt@vc4/vc4_wait_bo@used-bo-1ns.html

  * igt@vc4/vc4_wait_seqno@bad-seqno-1ns:
    - shard-dg2:          NOTRUN -> [SKIP][296] ([i915#7711]) +15 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-5/igt@vc4/vc4_wait_seqno@bad-seqno-1ns.html

  
#### Possible fixes ####

  * igt@gem_eio@reset-stress:
    - shard-dg1:          [FAIL][297] ([i915#5784]) -> [PASS][298]
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg1-18/igt@gem_eio@reset-stress.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-18/igt@gem_eio@reset-stress.html

  * igt@gem_exec_capture@pi@ccs1:
    - shard-dg2:          [INCOMPLETE][299] -> [PASS][300]
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg2-3/igt@gem_exec_capture@pi@ccs1.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-7/igt@gem_exec_capture@pi@ccs1.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-rkl:          [FAIL][301] ([i915#2842]) -> [PASS][302]
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-rkl-2/igt@gem_exec_fair@basic-none@vcs0.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-2/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         [FAIL][303] ([i915#2842]) -> [PASS][304]
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - shard-dg2:          [INCOMPLETE][305] ([i915#9275]) -> [PASS][306]
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg2-6/igt@gem_exec_suspend@basic-s0@smem.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-1/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [DMESG-WARN][307] ([i915#4936] / [i915#5493]) -> [PASS][308]
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
    - shard-dg1:          [FAIL][309] ([i915#3591]) -> [PASS][310]
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][311] ([i915#7790]) -> [PASS][312]
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-snb1/igt@i915_pm_rps@reset.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-snb4/igt@i915_pm_rps@reset.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [FAIL][313] ([i915#5138]) -> [PASS][314]
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_cursor_legacy@single-move@all-pipes:
    - shard-mtlp:         [DMESG-WARN][315] -> [PASS][316]
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-mtlp-4/igt@kms_cursor_legacy@single-move@all-pipes.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-7/igt@kms_cursor_legacy@single-move@all-pipes.html

  * igt@kms_flip@flip-vs-modeset-vs-hang@a-hdmi-a1:
    - shard-rkl:          [INCOMPLETE][317] -> [PASS][318]
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-rkl-2/igt@kms_flip@flip-vs-modeset-vs-hang@a-hdmi-a1.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-5/igt@kms_flip@flip-vs-modeset-vs-hang@a-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-snb:          [SKIP][319] ([fdo#109271]) -> [PASS][320] +12 other tests pass
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-dg2:          [SKIP][321] ([i915#9519]) -> [PASS][322]
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg2-10/igt@kms_pm_rpm@dpms-non-lpsp.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg2-2/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-4:
    - shard-dg1:          [FAIL][323] ([i915#9196]) -> [PASS][324]
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-dg1-16/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-4.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-dg1-14/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-4.html

  * igt@perf_pmu@busy-double-start@ccs0:
    - shard-mtlp:         [FAIL][325] ([i915#4349]) -> [PASS][326]
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-mtlp-7/igt@perf_pmu@busy-double-start@ccs0.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@perf_pmu@busy-double-start@ccs0.html

  * igt@perf_pmu@most-busy-idle-check-all@rcs0:
    - shard-rkl:          [FAIL][327] ([i915#4349]) -> [PASS][328]
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-rkl-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html

  
#### Warnings ####

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-mtlp:         [ABORT][329] -> [ABORT][330] ([i915#9820])
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-mtlp-6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_content_protection@atomic:
    - shard-snb:          [SKIP][331] ([fdo#109271]) -> [INCOMPLETE][332] ([i915#8816])
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-snb1/igt@kms_content_protection@atomic.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-snb7/igt@kms_content_protection@atomic.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          [SKIP][333] ([fdo#110189] / [i915#3955]) -> [SKIP][334] ([i915#3955])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-rkl-5/igt@kms_fbcon_fbt@psr.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-7/igt@kms_fbcon_fbt@psr.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][335] ([i915#3955]) -> [SKIP][336] ([fdo#110189] / [i915#3955])
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14145/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#10070]: https://gitlab.freedesktop.org/drm/intel/issues/10070
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
  [i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
  [i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122
  [i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
  [i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
  [i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
  [i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
  [i915#8063]: https://gitlab.freedesktop.org/drm/intel/issues/8063
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289
  [i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430
  [i915#8431]: https://gitlab.freedesktop.org/drm/intel/issues/8431
  [i915#8436]: https://gitlab.freedesktop.org/drm/intel/issues/8436
  [i915#8440]: https://gitlab.freedesktop.org/drm/intel/issues/8440
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
  [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
  [i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
  [i915#8807]: https://gitlab.freedesktop.org/drm/intel/issues/8807
  [i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
  [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
  [i915#8816]: https://gitlab.freedesktop.org/drm/intel/issues/8816
  [i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
  [i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
  [i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
  [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
  [i915#9293]: https://gitlab.freedesktop.org/drm/intel/issues/9293
  [i915#9295]: https://gitlab.freedesktop.org/drm/intel/issues/9295
  [i915#9298]: https://gitlab.freedesktop.org/drm/intel/issues/9298
  [i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
  [i915#9340]: https://gitlab.freedesktop.org/drm/intel/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/intel/issues/9531
  [i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606
  [i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9779]: https://gitlab.freedesktop.org/drm/intel/issues/9779
  [i915#9781]: https://gitlab.freedesktop.org/drm/intel/issues/9781
  [i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
  [i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
  [i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
  [i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833
  [i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
  [i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917


Build changes
-------------

  * Linux: CI_DRM_14145 -> Patchwork_128193v3

  CI-20190529: 20190529
  CI_DRM_14145: ad8fc2d4a396b1123c48340004d8c35dd0320817 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7683: 7683
  Patchwork_128193v3: ad8fc2d4a396b1123c48340004d8c35dd0320817 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v3/index.html

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