From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6732BC433FE for ; Tue, 11 Oct 2022 07:34:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 64B2610E7CD; Tue, 11 Oct 2022 07:34:12 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE19A10E7D4 for ; Tue, 11 Oct 2022 07:34:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665473647; x=1697009647; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=94G/bHJp7NPFW6NIqdXJB81uUPV5YBu1eaGWweX+0oY=; b=LVIsE8YQebxgbBPnYwdR7bv/m9W2ZYIh/V2GDGf/9iCIzk8qQBf9dLsx q1/i7n+6TtZNJ0+5uidthUI8N2Ocr56ld+137UqMe+Fd/nguXc4XOGgIq lMJ7S9cfIAaWkaSngb/FE5Q2DJhJltZBwF2utr8ZZnbVUozkPUxekh80r nWweKGWcNkBEfspYwI+T/59q0F47YaCxHbMfHziZnMrvO2yu7rIdLW8xp SgVmk+vqN1qRmZhzYeYW1x7wJrH+uXW3mXESgstc/9ZAsbxaZwQYNQN3M uFptLV/N10yZc5Ld8ZWk6xBEAV0E0x7VnjY8sLb5gzYEZCH9aY1wXUxI3 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="287697683" X-IronPort-AV: E=Sophos;i="5.95,175,1661842800"; d="scan'208";a="287697683" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 00:34:07 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="871409715" X-IronPort-AV: E=Sophos;i="5.95,175,1661842800"; d="scan'208";a="871409715" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.187.14]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 00:34:06 -0700 Date: Tue, 11 Oct 2022 00:34:05 -0700 Message-ID: <87o7ui24r6.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Jani Nikula In-Reply-To: <87tu4aygcl.fsf@intel.com> References: <87tu4aygcl.fsf@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Don't do display work on platforms without display X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 11 Oct 2022 00:22:34 -0700, Jani Nikula wrote: > Hi Jani, > On Mon, 10 Oct 2022, Ashutosh Dixit wrote: > > Do display work only on platforms with display. This avoids holding the > > runtime PM wakeref for an additional 100+ ms after GT has been parked. > > > > Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7025 > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 36 +++++++++++++++------------ > > 1 file changed, 20 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c > > index f553e2173bdad..26aa2e979a148 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c > > @@ -70,19 +70,21 @@ static int __gt_unpark(struct intel_wakeref *wf) > > > > GT_TRACE(gt, "\n"); > > > > - /* > > - * It seems that the DMC likes to transition between the DC states a lot > > - * when there are no connected displays (no active power domains) during > > - * command submission. > > - * > > - * This activity has negative impact on the performance of the chip with > > - * huge latencies observed in the interrupt handler and elsewhere. > > - * > > - * Work around it by grabbing a GT IRQ power domain whilst there is any > > - * GT activity, preventing any DC state transitions. > > - */ > > - gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ); > > - GEM_BUG_ON(!gt->awake); > > + if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) { > > Feels like something's wrong if you need both of those. Don't think so: /* Only valid when HAS_DISPLAY() is true */ #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \ !(dev_priv)->params.disable_display && \ !intel_opregion_headless_sku(dev_priv)) Maybe inside display code INTEL_DISPLAY_ENABLED is sufficient since code paths have previously invoked HAS_DISPLAY, but not in non-display code. Thanks. -- Ashutosh > > + /* > > + * It seems that the DMC likes to transition between the DC states a lot > > + * when there are no connected displays (no active power domains) during > > + * command submission. > > + * > > + * This activity has negative impact on the performance of the chip with > > + * huge latencies observed in the interrupt handler and elsewhere. > > + * > > + * Work around it by grabbing a GT IRQ power domain whilst there is any > > + * GT activity, preventing any DC state transitions. > > + */ > > + gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ); > > + GEM_BUG_ON(!gt->awake); > > + } > > > > intel_rc6_unpark(>->rc6); > > intel_rps_unpark(>->rps); > > @@ -115,9 +117,11 @@ static int __gt_park(struct intel_wakeref *wf) > > /* Everything switched off, flush any residual interrupt just in case */ > > intel_synchronize_irq(i915); > > > > - /* Defer dropping the display power well for 100ms, it's slow! */ > > - GEM_BUG_ON(!wakeref); > > - intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); > > + if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) { > > + /* Defer dropping the display power well for 100ms, it's slow! */ > > + GEM_BUG_ON(!wakeref); > > + intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); > > + } > > > > return 0; > > } > > -- > Jani Nikula, Intel Open Source Graphics Center