From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77057ECAAA3 for ; Thu, 25 Aug 2022 23:59:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6571510E46A; Thu, 25 Aug 2022 23:59:20 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7933D10E46A for ; Thu, 25 Aug 2022 23:59:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661471957; x=1693007957; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=Q7eHvi3l3UnY55Y+QaFYnh9j65Otrn4bIcOIGI9ZnJw=; b=S7WbSKAEqljQvY4QICApFmJehApT8Hi8QPLs7kwm/fLoiW4C8Qh/lC44 rscqLZPrzVtj7JVP294bMHYob5JRZULiPlWg4r0R67ekpd5Nn0W//5oeu SqABDksTelGHZor8utqNZptuJj/eGRVVwBwVhlstE8aKjuAeziS/XM/8m sVqwwBghKw2rFk8mebxfoQxPJ5lVrjn9S9Wwrz1jgnfzSCpQlkrVzwRU1 EGBjw9ZRV6a9RIYjCsxr222hX9V+Gsvbwm7WodatP3D2q6FJos9xI7m3N yIqKB6RA5NhQ3hc7DjzkOxC0SAepC9qRNhJL3w4Bpw611wuXB3Fa8sKSr w==; X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="281355131" X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="281355131" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 16:59:16 -0700 X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="938540628" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.252.130.121]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 16:59:16 -0700 Date: Thu, 25 Aug 2022 16:59:15 -0700 Message-ID: <87o7w7kh7w.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Rodrigo Vivi In-Reply-To: <20220825222315.58696-1-rodrigo.vivi@intel.com> References: <20220825222315.58696-1-rodrigo.vivi@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH] drm/i915/slpc: Set rps' min and max frequencies even with SLPC. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Sushma Venkatesh Reddy Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 25 Aug 2022 15:23:15 -0700, Rodrigo Vivi wrote: > > We need to inform PCODE of a desired ring frequencies so PCODE update > the memory frequencies to us. rps->min_freq and rps->max_freq are the > frequencies used in that request. However they were unset when SLPC was > enabled and PCODE never updated the memory freq. > > Let's at least for now get these freq set up so we can inform PCODE. Hi Rodrigo, Great find. Though may I propose a more direct patch below for fixing this: +++++++++++++++++++++++++++++++++++++++++++++ diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c index 14fe65812e42..a1791b6c7e04 100644 --- a/drivers/gpu/drm/i915/gt/intel_llc.c +++ b/drivers/gpu/drm/i915/gt/intel_llc.c @@ -49,6 +49,7 @@ static unsigned int cpu_max_MHz(void) static bool get_ia_constants(struct intel_llc *llc, struct ia_constants *consts) { + struct intel_guc_slpc *slpc = &llc_to_gt(llc)->uc.guc.slpc; struct drm_i915_private *i915 = llc_to_gt(llc)->i915; struct intel_rps *rps = &llc_to_gt(llc)->rps; @@ -65,8 +66,14 @@ static bool get_ia_constants(struct intel_llc *llc, /* convert DDR frequency from units of 266.6MHz to bandwidth */ consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3); - consts->min_gpu_freq = rps->min_freq; - consts->max_gpu_freq = rps->max_freq; + if (intel_uc_uses_guc_slpc(&llc_to_gt(llc)->uc)) { + consts->min_gpu_freq = slpc->min_freq; + consts->max_gpu_freq = slpc->rp0_freq; + } else { + consts->min_gpu_freq = rps->min_freq; + consts->max_gpu_freq = rps->max_freq; + } + if (GRAPHICS_VER(i915) >= 9) { /* Convert GT frequency to 50 HZ units */ consts->min_gpu_freq /= GEN9_FREQ_SCALER; +++++++++++++++++++++++++++++++++++++++++++++ I have only compile tested the patch but it looks like everything is set up so the patch above should work. The call stack for slpc initialization is the following (I am writing here due to the rather opaque uc macros): intel_gt_resume -> intel_gt_init_hw -> intel_uc_init_hw/__uc_init_hw -> intel_guc_slpc_enable -> slpc_get_rp_values As we can see intel_llc_enable() is called after intel_gt_init_hw() in intel_gt_resume() so SLPC params should be set up. What you have is fine too, I can R-b that if you prefer that. Thanks. -- Ashutosh > Cc: Ashutosh Dixit > Tested-by: Sushma Venkatesh Reddy > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/gt/intel_rps.c | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 8c289a032103..58a82978d5df 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -1128,6 +1128,20 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c > } > } > > +static void rps_basic_init_for_slpc(struct intel_rps *rps) > +{ > + struct intel_rps_freq_caps caps; > + > + /* > + * Even with SLPC we need to initialize at least a basic min and max > + * frequency so we can inform pcode a desired IA ring frequency in > + * gen6_update_ring_freq > + */ > + gen6_rps_get_freq_caps(rps, &caps); > + rps->min_freq = caps.min_freq; > + rps->max_freq = caps.rp0_freq; > +} > + > static void gen6_rps_init(struct intel_rps *rps) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > @@ -1970,8 +1984,10 @@ void intel_rps_init(struct intel_rps *rps) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > > - if (rps_uses_slpc(rps)) > + if (rps_uses_slpc(rps)) { > + rps_basic_init_for_slpc(rps); > return; > + } > > if (IS_CHERRYVIEW(i915)) > chv_rps_init(rps); > -- > 2.37.1 >