From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64E4BC433EF for ; Thu, 26 May 2022 19:10:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B6B5710E28C; Thu, 26 May 2022 19:10:15 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22D5910E28C for ; Thu, 26 May 2022 19:10:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653592214; x=1685128214; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=HJZkkGvK1AV+cvlFk7NgE4s2k7cPH7GHX3dQaCIPuto=; b=JGT37Winj/w8CcIO0Cz0hOLzOzVfsSw6QWCW3BO7fVUJZZUcKHmI+D4I 1QmXv7ftZ4jIIj9pjq5NH0BF+Ke3KbWJU3Mxat5WeEbeXnnZ6UKMhbfGk 9XBZgeNPj4KFMSn8whEDZ4aOAqd60EPgek6HsvoKTwgxXqT14FJBV+BNm yRTBdp7z3C/DWeQrtytX9bGPm2vWj4YPSGNOOvQsbfDqeeoz47YKifn7w vqSA67WkgUaPld2Cnbrm3oWXQHf43vNc1I5d4qMswI9gu41jWESrHIk9S 81c8j4Xo2fZUEIjicHQbeNOicKJerza7ukuhr9LHQeelbX3qi/fJi7uKC Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10359"; a="334902449" X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="334902449" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2022 12:10:08 -0700 X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="579006861" Received: from adixit-mobl1.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.229.76]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2022 12:10:07 -0700 Date: Thu, 26 May 2022 12:10:06 -0700 Message-ID: <87o7zk6rg1.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Andi Shyti In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915/gt: Expose per-gt RPS defaults in sysfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 10 May 2022 03:58:13 -0700, Andi Shyti wrote: > > Hi Ashutosh, Hi Andi, > > > +static ssize_t > > > +default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) > > > +{ > > > + struct intel_gt *gt = kobj_to_gt(kobj->parent); > > > + > > > + return sysfs_emit(buf, "%d\n", gt->rps_defaults.min_freq); > > I guess this is %u. Fixed in v2. > > > +} > > > + > > > +static struct kobj_attribute default_min_freq_mhz = > > > +__ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL); > > > + > > > +static ssize_t > > > +default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) > > > +{ > > > + struct intel_gt *gt = kobj_to_gt(kobj->parent); > > > + > > > + return sysfs_emit(buf, "%d\n", gt->rps_defaults.max_freq); > > > +} > > > + > > > +static struct kobj_attribute default_max_freq_mhz = > > > +__ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL); > > > + > > > +static ssize_t > > > +default_boost_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) > > > +{ > > > + struct intel_gt *gt = kobj_to_gt(kobj->parent); > > > + > > > + return sysfs_emit(buf, "%d\n", gt->rps_defaults.boost_freq); > > > +} > > > + > > > +static struct kobj_attribute default_boost_freq_mhz = > > > +__ATTR(rps_boost_freq_mhz, 0444, default_boost_freq_mhz_show, NULL); > > > + > > > +static const struct attribute * const rps_defaults_attrs[] = { > > > + &default_min_freq_mhz.attr, > > > + &default_max_freq_mhz.attr, > > > + &default_boost_freq_mhz.attr, > > > + NULL > > > +}; > > Do you think this in the default group of kobj_gt_type like the > gt_id? gt_id I think fits well in the category of a "default" attribute for a gt. I am not sure if these attributes similarly qualify as "default" attributes (for the .defaults sysfs), what do you think? That is why I have followed what is done in the engine sysfs which also does not use default attributes. But we can revisit based on your comments. > > [...] > > > > +struct intel_rps_defaults { > > > + u32 min_freq; > > > + u32 max_freq; > > > + u32 boost_freq; > > > +}; > > > + > > > enum intel_submission_method { > > > INTEL_SUBMISSION_RING, > > > INTEL_SUBMISSION_ELSP, > > > @@ -227,6 +233,10 @@ struct intel_gt { > > > /* gt/gtN sysfs */ > > > struct kobject sysfs_gt; > > > + > > > + /* sysfs defaults per gt */ > > > + struct intel_rps_defaults rps_defaults; > > more of a matter of taste, but this looks natural to me to be in > rps rather then in the gt. In v2 I have changed the name of this from 'struct intel_rps_defaults' to 'struct gt_defaults'. So the idea is to have a central place in the gt where any "module" (RPS, PM, ...) can store their defaults which are then exposed via sysfs files in gt/gtN/.defaults directory. There are multiple ways of doing this but this is what I've done in this series, basically to keep things simple. Thanks. -- Ashutosh