* [PATCH] drm/dp: Avoid needless delay while link training
@ 2017-09-26 9:49 Lee, Shawn C
2017-09-26 9:45 ` Jani Nikula
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Lee, Shawn C @ 2017-09-26 9:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Cooper Chiou
DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (0000Eh)
bit7 to indicate Extended Receiver Capability. A DPRX with DPCD
Rev. 1.4 (or higher) must have an Extended Receiver Capability field.
Driver have to clear bit7 when retrieve interval value and avoid to
wait for needless delay.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Signed-off-by: Shawn Lee <shawn.c.lee@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 18 ++++++++++++------
include/drm/drm_dp_helper.h | 1 +
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 08af8d6b844b..5a01c84b7f8f 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -118,19 +118,25 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
}
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
-void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
- if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u8 interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_INTERVAL_MASK;
+
+ if (interval == 0)
udelay(100);
else
- mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+ mdelay(interval * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
-void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
- if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u8 interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_INTERVAL_MASK;
+
+ if (interval == 0)
udelay(400);
else
- mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+ mdelay(interval * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 2c412a15cfa1..12d4cf48096c 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -118,6 +118,7 @@
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
+#define DP_TRAINING_AUX_RD_INTERVAL_MASK (0x7f << 0)
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/dp: Avoid needless delay while link training
2017-09-26 9:49 [PATCH] drm/dp: Avoid needless delay while link training Lee, Shawn C
@ 2017-09-26 9:45 ` Jani Nikula
2017-09-28 2:44 ` Lee, Shawn C
2017-09-26 11:19 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-09-26 15:22 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Jani Nikula @ 2017-09-26 9:45 UTC (permalink / raw)
To: Lee, Shawn C, intel-gfx; +Cc: Cooper Chiou
On Tue, 26 Sep 2017, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
> DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (0000Eh)
> bit7 to indicate Extended Receiver Capability. A DPRX with DPCD
> Rev. 1.4 (or higher) must have an Extended Receiver Capability field.
> Driver have to clear bit7 when retrieve interval value and avoid to
> wait for needless delay.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
>
> Signed-off-by: Shawn Lee <shawn.c.lee@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 18 ++++++++++++------
> include/drm/drm_dp_helper.h | 1 +
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 08af8d6b844b..5a01c84b7f8f 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -118,19 +118,25 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
> }
> EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
>
> -void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
> +void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> + u8 interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_INTERVAL_MASK;
> +
> + if (interval == 0)
> udelay(100);
> else
> - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
> + mdelay(interval * 4);
DP 1.4 seems to change this to 100 us for main-link clock recovery, but
let's leave that to another patch, another day...
> }
> EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
>
> -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
> +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> + u8 interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_INTERVAL_MASK;
> +
> + if (interval == 0)
> udelay(400);
> else
> - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
> + mdelay(interval * 4);
> }
> EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 2c412a15cfa1..12d4cf48096c 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -118,6 +118,7 @@
> # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
>
> #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
> +#define DP_TRAINING_AUX_RD_INTERVAL_MASK (0x7f << 0)
Please indent this like all other content definitions in this file,
i.e. space between "#" and "define".
Please add
# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* 1.4 */
while at it.
Other than that, LGTM.
BR,
Jani.
>
> #define DP_ADAPTER_CAP 0x00f /* 1.2 */
> # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/dp: Avoid needless delay while link training
2017-09-26 9:45 ` Jani Nikula
@ 2017-09-28 2:44 ` Lee, Shawn C
0 siblings, 0 replies; 5+ messages in thread
From: Lee, Shawn C @ 2017-09-28 2:44 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org; +Cc: Chiou, Cooper
>On Tue, 26 Sep 2017, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
>> DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (0000Eh)
>> bit7 to indicate Extended Receiver Capability. A DPRX with DPCD Rev.
>> 1.4 (or higher) must have an Extended Receiver Capability field.
>> Driver have to clear bit7 when retrieve interval value and avoid to
>> wait for needless delay.
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Cooper Chiou <cooper.chiou@intel.com>
>>
>> Signed-off-by: Shawn Lee <shawn.c.lee@intel.com>
>> ---
>> drivers/gpu/drm/drm_dp_helper.c | 18 ++++++++++++------
>> include/drm/drm_dp_helper.h | 1 +
>> 2 files changed, 13 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>> b/drivers/gpu/drm/drm_dp_helper.c index 08af8d6b844b..5a01c84b7f8f
>> 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -118,19 +118,25 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const
>> u8 link_status[DP_LINK_STATUS_SI }
>> EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
>>
>> -void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
>> - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
>> +void drm_dp_link_train_clock_recovery_delay(const u8
>> +dpcd[DP_RECEIVER_CAP_SIZE]) {
>> + u8 interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
>> +DP_TRAINING_AUX_RD_INTERVAL_MASK;
>> +
>> + if (interval == 0)
>> udelay(100);
>> else
>> - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
>> + mdelay(interval * 4);
>
>DP 1.4 seems to change this to 100 us for main-link clock recovery, but let's leave that to another patch, another day...
>
OK. Let's wait for DP 1.4 spec finalize it and commit the latest change later.
>> }
>> EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
>>
>> -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
>> - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
>> +void drm_dp_link_train_channel_eq_delay(const u8
>> +dpcd[DP_RECEIVER_CAP_SIZE]) {
>> + u8 interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
>> +DP_TRAINING_AUX_RD_INTERVAL_MASK;
>> +
>> + if (interval == 0)
>> udelay(400);
>> else
>> - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
>> + mdelay(interval * 4);
>> }
>> EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>>
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index 2c412a15cfa1..12d4cf48096c 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -118,6 +118,7 @@
>> # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
>>
>> #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
>> +#define DP_TRAINING_AUX_RD_INTERVAL_MASK (0x7f << 0)
>
>Please indent this like all other content definitions in this file, i.e. space between "#" and "define".
>
>Please add
>
># define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* 1.4 */
I will do the change as you mention in next commit.
>while at it.
>
>Other than that, LGTM.
>
>BR,
>Jani.
>
>>
>> #define DP_ADAPTER_CAP 0x00f /* 1.2 */
>> # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
>
>--
>Jani Nikula, Intel Open Source Technology Center
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/dp: Avoid needless delay while link training
2017-09-26 9:49 [PATCH] drm/dp: Avoid needless delay while link training Lee, Shawn C
2017-09-26 9:45 ` Jani Nikula
@ 2017-09-26 11:19 ` Patchwork
2017-09-26 15:22 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-09-26 11:19 UTC (permalink / raw)
To: Lee, Shawn C; +Cc: intel-gfx
== Series Details ==
Series: drm/dp: Avoid needless delay while link training
URL : https://patchwork.freedesktop.org/series/30891/
State : success
== Summary ==
Series 30891v1 drm/dp: Avoid needless delay while link training
https://patchwork.freedesktop.org/api/1.0/series/30891/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
pass -> FAIL (fi-kbl-7500u) fdo#102514
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (fi-cfl-s) fdo#102294
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (fi-glk-1) fdo#102777 +1
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:444s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:417s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:514s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:506s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:495s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:494s
fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:545s
fi-cnl-y total:289 pass:257 dwarn:0 dfail:0 fail:5 skip:27 time:645s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:420s
fi-glk-1 total:289 pass:258 dwarn:2 dfail:0 fail:0 skip:29 time:567s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:421s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:405s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:489s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:459s
fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:456s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:587s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:545s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:451s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:745s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:487s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:558s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:411s
874d8edd93781dc18b7d604b22ff3eba7897efc3 drm-tip: 2017y-09m-26d-09h-55m-22s UTC integration manifest
2059b44eaab3 drm/dp: Avoid needless delay while link training
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5813/
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^ permalink raw reply [flat|nested] 5+ messages in thread* ✓ Fi.CI.IGT: success for drm/dp: Avoid needless delay while link training
2017-09-26 9:49 [PATCH] drm/dp: Avoid needless delay while link training Lee, Shawn C
2017-09-26 9:45 ` Jani Nikula
2017-09-26 11:19 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-09-26 15:22 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-09-26 15:22 UTC (permalink / raw)
To: Lee, Shawn C; +Cc: intel-gfx
== Series Details ==
Series: drm/dp: Avoid needless delay while link training
URL : https://patchwork.freedesktop.org/series/30891/
State : success
== Summary ==
shard-hsw total:2429 pass:1325 dwarn:4 dfail:0 fail:17 skip:1083 time:9960s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5813/shards.html
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2017-09-26 9:49 [PATCH] drm/dp: Avoid needless delay while link training Lee, Shawn C
2017-09-26 9:45 ` Jani Nikula
2017-09-28 2:44 ` Lee, Shawn C
2017-09-26 11:19 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-09-26 15:22 ` ✓ Fi.CI.IGT: " Patchwork
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