From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915: Use a macro to express the range of valid gens for reg_read Date: Mon, 31 Mar 2014 13:47:12 +0300 Message-ID: <87ob0mejbj.fsf@intel.com> References: <1396261448-30300-1-git-send-email-damien.lespiau@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 40F946E226 for ; Mon, 31 Mar 2014 03:46:41 -0700 (PDT) In-Reply-To: <1396261448-30300-1-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 31 Mar 2014, Damien Lespiau wrote: > The reg_read whitelist has a gen bitmask to code the gens we're allowing > the register to be read on. Until now, it was a litteral, but we can be > a bit more expressive. s/litteral/literal/ Reviewed-by: Jani Nikula > > To ease the review, a small test program: > > $ cat bit-range.c > #include > #include > > #define U32_C(x) x ## U > #define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l)) > #define GEN_RANGE(l, h) GENMASK(h, l) > > int main(int argc, char **argv) > { > printf("0x%08x\n", GEN_RANGE(1, 1)); > printf("0x%08x\n", GEN_RANGE(1, 2)); > printf("0x%08x\n", GEN_RANGE(4, 4)); > printf("0x%08x\n", GEN_RANGE(4, 5)); > printf("0x%08x\n", GEN_RANGE(1, 31)); > printf("0x%08x\n", GEN_RANGE(4, 8)); > > return 0; > } > $ ./bit-range > 0x00000002 > 0x00000006 > 0x00000010 > 0x00000030 > 0xfffffffe > 0x000001f0 > > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/intel_uncore.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 823d699..e2aa964 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -860,12 +860,15 @@ void intel_uncore_fini(struct drm_device *dev) > intel_uncore_forcewake_reset(dev, false); > } > > +#define GEN_RANGE(l, h) GENMASK(h, l) > + > static const struct register_whitelist { > uint64_t offset; > uint32_t size; > - uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ > + /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ > + uint32_t gen_bitmask; > } whitelist[] = { > - { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 }, > + { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) }, > }; > > int i915_reg_read_ioctl(struct drm_device *dev, > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center