From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 11/13] drm/i915: Reject commands that would store to global HWS page Date: Wed, 05 Feb 2014 17:39:47 +0200 Message-ID: <87ob2l1scc.fsf@intel.com> References: <1385484699-51596-1-git-send-email-bradley.d.volkin@intel.com> <1391032514-19136-1-git-send-email-bradley.d.volkin@intel.com> <1391032514-19136-12-git-send-email-bradley.d.volkin@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F709FCF70 for ; Wed, 5 Feb 2014 07:36:17 -0800 (PST) In-Reply-To: <1391032514-19136-12-git-send-email-bradley.d.volkin@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: bradley.d.volkin@intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote: > From: Brad Volkin > > PIPE_CONTROL and MI_FLUSH_DW have bits that would write to the > hardware status page. The driver stores request tracking info > there, so don't let userspace overwrite it. > > Signed-off-by: Brad Volkin > --- > drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++++++++++++++++++++++++++---- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 27 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c > index 26072a2..b93df1c 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -141,7 +141,8 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = { > }, > { > .offset = 1, > - .mask = PIPE_CONTROL_GLOBAL_GTT_IVB, > + .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | > + PIPE_CONTROL_STORE_DATA_INDEX), > .expected = 0, > .condition_offset = 1, > .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK > @@ -192,8 +193,15 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = { > .expected = 0, > .condition_offset = 0, > .condition_mask = MI_FLUSH_DW_OP_MASK > + }, > + { > + .offset = 0, > + .mask = MI_FLUSH_DW_STORE_INDEX, > + .expected = 0, > + .condition_offset = 0, > + .condition_mask = MI_FLUSH_DW_OP_MASK > }}, > - .bits_count = 2 ), > + .bits_count = 3 ), I'm disliking this separate .bits_count more at every change... > CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, > .bits = {{ > .offset = 0, > @@ -231,8 +239,15 @@ static const struct drm_i915_cmd_descriptor vecs_cmds[] = { > .expected = 0, > .condition_offset = 0, > .condition_mask = MI_FLUSH_DW_OP_MASK > + }, > + { > + .offset = 0, > + .mask = MI_FLUSH_DW_STORE_INDEX, > + .expected = 0, > + .condition_offset = 0, > + .condition_mask = MI_FLUSH_DW_OP_MASK > }}, > - .bits_count = 2 ), > + .bits_count = 3 ), > CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, > .bits = {{ > .offset = 0, > @@ -264,8 +279,15 @@ static const struct drm_i915_cmd_descriptor blt_cmds[] = { > .expected = 0, > .condition_offset = 0, > .condition_mask = MI_FLUSH_DW_OP_MASK > + }, > + { > + .offset = 0, > + .mask = MI_FLUSH_DW_STORE_INDEX, > + .expected = 0, > + .condition_offset = 0, > + .condition_mask = MI_FLUSH_DW_OP_MASK > }}, > - .bits_count = 2 ), > + .bits_count = 3 ), > CMD( COLOR_BLT, S2D, !F, 0x3F, S ), > CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), > }; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ff263f4..5f77cb6 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -324,6 +324,7 @@ > #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) > #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ > #define PIPE_CONTROL_MMIO_WRITE (1<<23) > +#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) > #define PIPE_CONTROL_CS_STALL (1<<20) > #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) > #define PIPE_CONTROL_QW_WRITE (1<<14) > -- > 1.8.5.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center