From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 3/8] drm/i915: correctly set the DDI_FUNC_CTL bpc field Date: Thu, 09 Aug 2012 12:55:41 +0300 Message-ID: <87obmke6ea.fsf@intel.com> References: <1344446134-3704-1-git-send-email-przanoni@gmail.com> <1344446134-3704-4-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 869DFA0E5B for ; Thu, 9 Aug 2012 02:52:05 -0700 (PDT) In-Reply-To: <1344446134-3704-4-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni , intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, 08 Aug 2012, Paulo Zanoni wrote: > From: Paulo Zanoni > > Correctly erase the values previously set and also check for 6pbc and > 10bpc. 6 *bpc*. But is the 6 or 10 bpc usage below correct anyway, as the spec says they are not supported by HDMI or DVI? (Either way, the erase part of the patch is valid.) BR, Jani. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++++++++------ > 2 files changed, 21 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 896b279..f3fafb8 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4308,6 +4308,7 @@ > #define PIPE_DDI_MODE_SELECT_DP_SST (2<<24) > #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) > #define PIPE_DDI_MODE_SELECT_FDI (4<<24) > +#define PIPE_DDI_BPC_MASK (7<<20) > #define PIPE_DDI_BPC_8 (0<<20) > #define PIPE_DDI_BPC_10 (1<<20) > #define PIPE_DDI_BPC_6 (2<<20) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 1fbd67c..8b38359 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -725,14 +725,28 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, > /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */ > temp = I915_READ(DDI_FUNC_CTL(pipe)); > temp &= ~PIPE_DDI_PORT_MASK; > - temp &= ~PIPE_DDI_BPC_12; > + temp &= ~PIPE_DDI_BPC_MASK; > temp &= ~PIPE_DDI_MODE_SELECT_MASK; > temp &= ~(PIPE_DDI_PVSYNC | PIPE_DDI_PHSYNC); > - temp |= PIPE_DDI_SELECT_PORT(port) | > - ((intel_crtc->bpp > 24) ? > - PIPE_DDI_BPC_12 : > - PIPE_DDI_BPC_8) | > - PIPE_DDI_FUNC_ENABLE; > + temp |= PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port); > + > + switch (intel_crtc->bpp) { > + case 18: > + temp |= PIPE_DDI_BPC_6; > + break; > + case 24: > + temp |= PIPE_DDI_BPC_8; > + break; > + case 30: > + temp |= PIPE_DDI_BPC_10; > + break; > + case 36: > + temp |= PIPE_DDI_BPC_12; > + break; > + default: > + WARN(1, "%d bpp unsupported by pipe DDI function\n", > + intel_crtc->bpp); > + } > > if (intel_hdmi->has_hdmi_sink) > temp |= PIPE_DDI_MODE_SELECT_HDMI; > -- > 1.7.11.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx