From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B47DBC61DA4 for ; Thu, 16 Mar 2023 00:53:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D939210E308; Thu, 16 Mar 2023 00:53:33 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5961210E009; Thu, 16 Mar 2023 00:53:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678928012; x=1710464012; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=yhwEQimFrYWEhFDGPxx+84lA66S5QbFm7+P6fNNyaUI=; b=BfCHlsjR2QwY0LV8wlUlKTtl7ChKeQyY/Wl391Hlnp1FTstvxwCQz4Jw +U8S7XPo8oRNsH4DNcCLuT7T3/N+eKZkjVOskasbi29Ak9i6Ku1cD9sI4 kQkC2i4qoVVBc4jpxpIZ2Zcpit+nek2DwL4yOm/WaFHJxf9MdCNdfq/5z WGY/gMlgujMlvj7TttQxBf1jGJeFzRvhjTeI8txIshtMA1sK8rUm88yHc 9vXvnlARaqiQcULllddoi8cp4rRnXbQd94bdnH46Qb5dRG2sk/QXK4+90 oCYbPV0BLit+envIdWB3kPgxWvEGhCD57CDOFUzZ+QBpz/9pOrZilzDqn Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10650"; a="339391775" X-IronPort-AV: E=Sophos;i="5.98,262,1673942400"; d="scan'208";a="339391775" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Mar 2023 17:53:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10650"; a="672945396" X-IronPort-AV: E=Sophos;i="5.98,262,1673942400"; d="scan'208";a="672945396" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.13.197]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Mar 2023 17:53:31 -0700 Date: Wed, 15 Mar 2023 17:53:31 -0700 Message-ID: <87pm99wm7o.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Tvrtko Ursulin In-Reply-To: <44cf9bcf-ee64-3340-9836-27babb0b1b9c@linux.intel.com> References: <20230310005943.1029333-1-ashutosh.dixit@intel.com> <20230310005943.1029333-2-ashutosh.dixit@intel.com> <44cf9bcf-ee64-3340-9836-27babb0b1b9c@linux.intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/pmu: Use functions common with sysfs to read actual freq X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 15 Mar 2023 02:43:30 -0700, Tvrtko Ursulin wrote: > > On 10/03/2023 00:59, Ashutosh Dixit wrote: > > Expose intel_rps_read_actual_frequency_fw to read the actual freq without > > taking forcewake for use by PMU. The code is refactored to use a common set > > of functions across sysfs and PMU. Using common functions with sysfs in PMU > > solves the issues of missing support for MTL and missing support for older > > generations (prior to Gen6). It also future proofs the PMU where sometimes > > code has been updated for sysfs and PMU has been missed. > > > > v2: Remove runtime_pm_if_in_use from read_actual_frequency_fw (Tvrtko) > > > > Fixes: 22009b6dad66 ("drm/i915/mtl: Modify CAGF functions for MTL") > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8280 > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/i915/gt/intel_rps.c | 34 ++++++++++++++++------------- > > drivers/gpu/drm/i915/gt/intel_rps.h | 2 +- > > drivers/gpu/drm/i915/i915_pmu.c | 10 ++++----- > > 3 files changed, 24 insertions(+), 22 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > > index 4d0dc9de23f9..9d9ac35691fc 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > > @@ -2046,16 +2046,6 @@ void intel_rps_sanitize(struct intel_rps *rps) > > rps_disable_interrupts(rps); > > } > > -u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) > > -{ > > - struct drm_i915_private *i915 = rps_to_i915(rps); > > - i915_reg_t rpstat; > > - > > - rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > > - > > - return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); > > -} > > - > > u32 intel_rps_read_rpstat(struct intel_rps *rps) > > { > > struct drm_i915_private *i915 = rps_to_i915(rps); > > @@ -2089,10 +2079,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > > return cagf; > > } > > -static u32 read_cagf(struct intel_rps *rps) > > +static u32 __read_cagf(struct intel_rps *rps, bool take_fw) > > { > > struct drm_i915_private *i915 = rps_to_i915(rps); > > struct intel_uncore *uncore = rps_to_uncore(rps); > > + i915_reg_t r = INVALID_MMIO_REG; > > u32 freq; > > /* > > @@ -2100,22 +2091,30 @@ static u32 read_cagf(struct intel_rps *rps) > > * registers will return 0 freq when GT is in RC6 > > */ > > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { > > - freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); > > + r = MTL_MIRROR_TARGET_WP1; > > } else if (GRAPHICS_VER(i915) >= 12) { > > - freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > > + r = GEN12_RPSTAT1; > > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > > vlv_punit_get(i915); > > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > > vlv_punit_put(i915); > > + goto exit; > > Alternatively you could avoid the goto by making the read below conditional > on r being set. One more conditional though for avoiding gotos.. up to you. Done. > > > } else if (GRAPHICS_VER(i915) >= 6) { > > - freq = intel_uncore_read(uncore, GEN6_RPSTAT1); > > + r = GEN6_RPSTAT1; > > } else { > > - freq = intel_uncore_read(uncore, MEMSTAT_ILK); > > + r = MEMSTAT_ILK; > > } > > + freq = take_fw ? intel_uncore_read(uncore, r) : > > intel_uncore_read_fw(uncore, r); > > +exit: > > return intel_rps_get_cagf(rps, freq); > > } > > +static u32 read_cagf(struct intel_rps *rps) > > +{ > > + return __read_cagf(rps, true); > > +} > > There is only one caller so up to you if you think a helper is needed or > not. There are other callers too in i915/gt/selftest_rps.c so need to retain it. > > > + > > u32 intel_rps_read_actual_frequency(struct intel_rps *rps) > > { > > struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; > > @@ -2128,6 +2127,11 @@ u32 intel_rps_read_actual_frequency(struct intel_rps *rps) > > return freq; > > } > > +u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps) > > +{ > > + return intel_gpu_freq(rps, __read_cagf(rps, false)); > > +} > > + > > u32 intel_rps_read_punit_req(struct intel_rps *rps) > > { > > struct intel_uncore *uncore = rps_to_uncore(rps); > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h > > index c622962c6bef..2d5b3ef58606 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rps.h > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.h > > @@ -39,6 +39,7 @@ int intel_gpu_freq(struct intel_rps *rps, int val); > > int intel_freq_opcode(struct intel_rps *rps, int val); > > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1); > > u32 intel_rps_read_actual_frequency(struct intel_rps *rps); > > +u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps); > > u32 intel_rps_get_requested_frequency(struct intel_rps *rps); > > u32 intel_rps_get_min_frequency(struct intel_rps *rps); > > u32 intel_rps_get_min_raw_freq(struct intel_rps *rps); > > @@ -52,7 +53,6 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); > > u32 intel_rps_read_punit_req(struct intel_rps *rps); > > u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); > > u32 intel_rps_read_rpstat(struct intel_rps *rps); > > -u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); > > void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); > > void intel_rps_raise_unslice(struct intel_rps *rps); > > void intel_rps_lower_unslice(struct intel_rps *rps); > > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > > index a76c5ce9513d..7ece883a7d95 100644 > > --- a/drivers/gpu/drm/i915/i915_pmu.c > > +++ b/drivers/gpu/drm/i915/i915_pmu.c > > @@ -392,14 +392,12 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) > > * case we assume the system is running at the intended > > * frequency. Fortunately, the read should rarely fail! > > */ > > - val = intel_rps_read_rpstat_fw(rps); > > - if (val) > > - val = intel_rps_get_cagf(rps, val); > > I think you can un-export this one now. Done. As bonus unexported intel_rps_read_punit_req too. > With that looks okay to me, with or without the other stuff: > > Reviewed-by: Tvrtko Ursulin Thanks. -- Ashutosh > > > - else > > - val = rps->cur_freq; > > + val = intel_rps_read_actual_frequency_fw(rps); > > + if (!val) > > + val = intel_gpu_freq(rps, rps->cur_freq); > > add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT], > > - intel_gpu_freq(rps, val), period_ns / 1000); > > + val, period_ns / 1000); > > } > > if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) {