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From: Jani Nikula <jani.nikula@intel.com>
To: Vandita Kulkarni <vandita.kulkarni@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: --cc=uma.shankar@intel.com, ville.syrjala@intel.com
Subject: Re: [RFC-v2 1/9] drm/i915/dsi: Define command mode registers
Date: Tue, 12 Nov 2019 18:25:10 +0200	[thread overview]
Message-ID: <87pnhx2hax.fsf@intel.com> (raw)
In-Reply-To: <20191111111029.9126-2-vandita.kulkarni@intel.com>

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Adding all the register definitions needed
> for mipi dsi command mode.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

There may have been a few naming nitpicks I could've had, but meh.

Pushed to dinq, thanks for the patch.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 78 +++++++++++++++++++++++++++++----
>  1 file changed, 70 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a607ea520829..2ffcc21670b7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5036,14 +5036,20 @@ enum {
>  #define   BLM_PCH_POLARITY			(1 << 29)
>  #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
>  
> -#define UTIL_PIN_CTL		_MMIO(0x48400)
> -#define   UTIL_PIN_ENABLE	(1 << 31)
> -
> -#define   UTIL_PIN_PIPE(x)     ((x) << 29)
> -#define   UTIL_PIN_PIPE_MASK   (3 << 29)
> -#define   UTIL_PIN_MODE_PWM    (1 << 24)
> -#define   UTIL_PIN_MODE_MASK   (0xf << 24)
> -#define   UTIL_PIN_POLARITY    (1 << 22)
> +#define UTIL_PIN_CTL			_MMIO(0x48400)
> +#define   UTIL_PIN_ENABLE		(1 << 31)
> +#define   UTIL_PIN_PIPE_MASK		(3 << 29)
> +#define   UTIL_PIN_PIPE(x)		((x) << 29)
> +#define   UTIL_PIN_MODE_MASK		(0xf << 24)
> +#define   UTIL_PIN_MODE_DATA		(0 << 24)
> +#define   UTIL_PIN_MODE_PWM		(1 << 24)
> +#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
> +#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
> +#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
> +#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
> +#define   UTIL_PIN_POLARITY		(1 << 22)
> +#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
> +#define   UTIL_PIN_INPUT_DATA		(1 << 16)
>  
>  /* BXT backlight register definition. */
>  #define _BXT_BLC_PWM_CTL1			0xC8250
> @@ -7500,11 +7506,15 @@ enum {
>  #define GEN8_DE_PORT_IMR _MMIO(0x44444)
>  #define GEN8_DE_PORT_IIR _MMIO(0x44448)
>  #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> +#define  DSI1_NON_TE			(1 << 31)
> +#define  DSI0_NON_TE			(1 << 30)
>  #define  ICL_AUX_CHANNEL_E		(1 << 29)
>  #define  CNL_AUX_CHANNEL_F		(1 << 28)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> +#define  DSI1_TE			(1 << 24)
> +#define  DSI0_TE			(1 << 23)
>  #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
>  #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
>  #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
> @@ -10770,6 +10780,57 @@ enum skl_power_gate {
>  #define  ICL_ESC_CLK_DIV_SHIFT			0
>  #define DSI_MAX_ESC_CLK			20000		/* in KHz */
>  
> +#define _DSI_CMD_FRMCTL_0		0x6b034
> +#define _DSI_CMD_FRMCTL_1		0x6b834
> +#define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
> +						   _DSI_CMD_FRMCTL_0,\
> +						   _DSI_CMD_FRMCTL_1)
> +#define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
> +#define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
> +#define   DSI_NULL_PACKET_ENABLE		(1 << 28)
> +#define   DSI_FRAME_IN_PROGRESS			(1 << 0)
> +
> +#define _DSI_INTR_MASK_REG_0		0x6b070
> +#define _DSI_INTR_MASK_REG_1		0x6b870
> +#define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
> +						   _DSI_INTR_MASK_REG_0,\
> +						   _DSI_INTR_MASK_REG_1)
> +
> +#define _DSI_INTR_IDENT_REG_0		0x6b074
> +#define _DSI_INTR_IDENT_REG_1		0x6b874
> +#define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
> +						   _DSI_INTR_IDENT_REG_0,\
> +						   _DSI_INTR_IDENT_REG_1)
> +#define   DSI_TE_EVENT				(1 << 31)
> +#define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
> +#define   DSI_TX_DATA				(1 << 29)
> +#define   DSI_ULPS_ENTRY_DONE			(1 << 28)
> +#define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
> +#define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
> +#define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
> +#define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
> +#define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
> +#define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
> +#define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
> +#define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
> +#define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
> +#define   DSI_FRAME_UPDATE_DONE			(1 << 16)
> +#define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
> +#define   DSI_INVALID_TX_LENGTH			(1 << 13)
> +#define   DSI_INVALID_VC			(1 << 12)
> +#define   DSI_INVALID_DATA_TYPE			(1 << 11)
> +#define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
> +#define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
> +#define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
> +#define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
> +#define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
> +#define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
> +#define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
> +#define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
> +#define   DSI_EOT_SYNC_ERROR			(1 << 2)
> +#define   DSI_SOT_SYNC_ERROR			(1 << 1)
> +#define   DSI_SOT_ERROR				(1 << 0)
> +
>  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
>  #define GEN4_TIMESTAMP		_MMIO(0x2358)
>  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
> @@ -11374,6 +11435,7 @@ enum skl_power_gate {
>  #define  CMD_MODE_TE_GATE		(0x1 << 28)
>  #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
>  #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
> +#define  TE_SOURCE_GPIO			(1 << 27)
>  #define  LINK_READY			(1 << 20)
>  #define  PIX_FMT_MASK			(0x3 << 16)
>  #define  PIX_FMT_SHIFT			16

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@intel.com>
To: Vandita Kulkarni <vandita.kulkarni@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: --cc=uma.shankar@intel.com, ville.syrjala@intel.com
Subject: Re: [Intel-gfx] [RFC-v2 1/9] drm/i915/dsi: Define command mode registers
Date: Tue, 12 Nov 2019 18:25:10 +0200	[thread overview]
Message-ID: <87pnhx2hax.fsf@intel.com> (raw)
Message-ID: <20191112162510.9fKTO3EzQBueGmKwcAgDqQaOPG8HxAezR_-H51eBFPo@z> (raw)
In-Reply-To: <20191111111029.9126-2-vandita.kulkarni@intel.com>

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Adding all the register definitions needed
> for mipi dsi command mode.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

There may have been a few naming nitpicks I could've had, but meh.

Pushed to dinq, thanks for the patch.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 78 +++++++++++++++++++++++++++++----
>  1 file changed, 70 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a607ea520829..2ffcc21670b7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5036,14 +5036,20 @@ enum {
>  #define   BLM_PCH_POLARITY			(1 << 29)
>  #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
>  
> -#define UTIL_PIN_CTL		_MMIO(0x48400)
> -#define   UTIL_PIN_ENABLE	(1 << 31)
> -
> -#define   UTIL_PIN_PIPE(x)     ((x) << 29)
> -#define   UTIL_PIN_PIPE_MASK   (3 << 29)
> -#define   UTIL_PIN_MODE_PWM    (1 << 24)
> -#define   UTIL_PIN_MODE_MASK   (0xf << 24)
> -#define   UTIL_PIN_POLARITY    (1 << 22)
> +#define UTIL_PIN_CTL			_MMIO(0x48400)
> +#define   UTIL_PIN_ENABLE		(1 << 31)
> +#define   UTIL_PIN_PIPE_MASK		(3 << 29)
> +#define   UTIL_PIN_PIPE(x)		((x) << 29)
> +#define   UTIL_PIN_MODE_MASK		(0xf << 24)
> +#define   UTIL_PIN_MODE_DATA		(0 << 24)
> +#define   UTIL_PIN_MODE_PWM		(1 << 24)
> +#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
> +#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
> +#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
> +#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
> +#define   UTIL_PIN_POLARITY		(1 << 22)
> +#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
> +#define   UTIL_PIN_INPUT_DATA		(1 << 16)
>  
>  /* BXT backlight register definition. */
>  #define _BXT_BLC_PWM_CTL1			0xC8250
> @@ -7500,11 +7506,15 @@ enum {
>  #define GEN8_DE_PORT_IMR _MMIO(0x44444)
>  #define GEN8_DE_PORT_IIR _MMIO(0x44448)
>  #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> +#define  DSI1_NON_TE			(1 << 31)
> +#define  DSI0_NON_TE			(1 << 30)
>  #define  ICL_AUX_CHANNEL_E		(1 << 29)
>  #define  CNL_AUX_CHANNEL_F		(1 << 28)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> +#define  DSI1_TE			(1 << 24)
> +#define  DSI0_TE			(1 << 23)
>  #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
>  #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
>  #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
> @@ -10770,6 +10780,57 @@ enum skl_power_gate {
>  #define  ICL_ESC_CLK_DIV_SHIFT			0
>  #define DSI_MAX_ESC_CLK			20000		/* in KHz */
>  
> +#define _DSI_CMD_FRMCTL_0		0x6b034
> +#define _DSI_CMD_FRMCTL_1		0x6b834
> +#define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
> +						   _DSI_CMD_FRMCTL_0,\
> +						   _DSI_CMD_FRMCTL_1)
> +#define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
> +#define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
> +#define   DSI_NULL_PACKET_ENABLE		(1 << 28)
> +#define   DSI_FRAME_IN_PROGRESS			(1 << 0)
> +
> +#define _DSI_INTR_MASK_REG_0		0x6b070
> +#define _DSI_INTR_MASK_REG_1		0x6b870
> +#define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
> +						   _DSI_INTR_MASK_REG_0,\
> +						   _DSI_INTR_MASK_REG_1)
> +
> +#define _DSI_INTR_IDENT_REG_0		0x6b074
> +#define _DSI_INTR_IDENT_REG_1		0x6b874
> +#define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
> +						   _DSI_INTR_IDENT_REG_0,\
> +						   _DSI_INTR_IDENT_REG_1)
> +#define   DSI_TE_EVENT				(1 << 31)
> +#define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
> +#define   DSI_TX_DATA				(1 << 29)
> +#define   DSI_ULPS_ENTRY_DONE			(1 << 28)
> +#define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
> +#define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
> +#define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
> +#define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
> +#define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
> +#define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
> +#define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
> +#define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
> +#define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
> +#define   DSI_FRAME_UPDATE_DONE			(1 << 16)
> +#define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
> +#define   DSI_INVALID_TX_LENGTH			(1 << 13)
> +#define   DSI_INVALID_VC			(1 << 12)
> +#define   DSI_INVALID_DATA_TYPE			(1 << 11)
> +#define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
> +#define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
> +#define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
> +#define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
> +#define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
> +#define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
> +#define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
> +#define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
> +#define   DSI_EOT_SYNC_ERROR			(1 << 2)
> +#define   DSI_SOT_SYNC_ERROR			(1 << 1)
> +#define   DSI_SOT_ERROR				(1 << 0)
> +
>  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
>  #define GEN4_TIMESTAMP		_MMIO(0x2358)
>  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
> @@ -11374,6 +11435,7 @@ enum skl_power_gate {
>  #define  CMD_MODE_TE_GATE		(0x1 << 28)
>  #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
>  #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
> +#define  TE_SOURCE_GPIO			(1 << 27)
>  #define  LINK_READY			(1 << 20)
>  #define  PIX_FMT_MASK			(0x3 << 16)
>  #define  PIX_FMT_SHIFT			16

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-11-12 16:25 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-11 11:10 [RFC-v2 0/9] Add support for mipi dsi cmd mode Vandita Kulkarni
2019-11-11 11:10 ` [Intel-gfx] " Vandita Kulkarni
2019-11-11 11:10 ` [RFC-v2 1/9] drm/i915/dsi: Define command mode registers Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-12 16:25   ` Jani Nikula [this message]
2019-11-12 16:25     ` Jani Nikula
2019-11-11 11:10 ` [RFC-v2 2/9] drm/i915/dsi: Configure transcoder operation for command mode Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-12 16:23   ` Jani Nikula
2019-11-12 16:23     ` [Intel-gfx] " Jani Nikula
2019-11-11 11:10 ` [RFC-v2 3/9] drm/i915/dsi: Add vblank calculation " Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-11 11:10 ` [RFC-v2 4/9] drm/i915/dsi: Add cmd mode flags in display mode private flags Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-12 16:27   ` Jani Nikula
2019-11-12 16:27     ` [Intel-gfx] " Jani Nikula
2019-11-11 11:10 ` [RFC-v2 5/9] drm/i915/dsi: Add check for periodic command mode Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-11 11:10 ` [RFC-v2 6/9] drm/i915/dsi: Use private flags to indicate TE in cmd mode Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-11 11:10 ` [RFC-v2 7/9] drm/i915/dsi: Configure TE interrupt for " Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-12 14:59   ` Jani Nikula
2019-11-12 14:59     ` [Intel-gfx] " Jani Nikula
2019-11-11 11:10 ` [RFC-v2 8/9] drm/i915/dsi: Add TE handler for dsi " Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-12 15:10   ` Jani Nikula
2019-11-12 15:10     ` [Intel-gfx] " Jani Nikula
2019-11-11 11:10 ` [RFC-v2 9/9] drm/i915/dsi: Initiate fame request in " Vandita Kulkarni
2019-11-11 11:10   ` [Intel-gfx] " Vandita Kulkarni
2019-11-11 17:20 ` ✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi " Patchwork
2019-11-11 17:20   ` [Intel-gfx] " Patchwork
2019-11-11 17:23 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-11-11 17:23   ` [Intel-gfx] " Patchwork
2019-11-11 17:53 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-11 17:53   ` [Intel-gfx] " Patchwork
2019-11-12  5:52 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-12  5:52   ` [Intel-gfx] " Patchwork

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