From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing Date: Mon, 26 May 2014 15:52:42 +0300 Message-ID: <87ppj0itwl.fsf@intel.com> References: <1400488878-23130-1-git-send-email-imre.deak@intel.com> <1400488878-23130-2-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F61B6E26E for ; Mon, 26 May 2014 05:53:17 -0700 (PDT) In-Reply-To: <1400488878-23130-2-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 19 May 2014, Imre Deak wrote: > So far we used the wrong opcodes to access the DSI registers, so the > register writes during DSI programming didn't actually succeed and left > the registers unchanged. This wasn't a problem for the initial modeset, > where the BIOS-programmed values happened to work, but after resuming > from s0ix these registers are reset and failing to program them results > in a blank screen. Shobhit, this was already merged, did you have a chance to test it? Jani. > > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_sideband.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c > index f3909d5..01d841e 100644 > --- a/drivers/gpu/drm/i915/intel_sideband.c > +++ b/drivers/gpu/drm/i915/intel_sideband.c > @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, > u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) > { > u32 val = 0; > - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP, > + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, > reg, &val); > return val; > } > > void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) > { > - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP, > + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, > reg, &val); > } > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center