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d="scan'208";a="80055434" Received: from mwiniars-desk2.ger.corp.intel.com (HELO localhost) ([10.245.246.85]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2024 02:55:21 -0700 From: Jani Nikula To: Arun R Murthy , intel-gfx@lists.freedesktop.org Cc: Arun R Murthy Subject: Re: [PATCH 1/5] drm/i915/display: Add support for histogram In-Reply-To: <20240705095551.1244154-2-arun.r.murthy@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20240705095551.1244154-1-arun.r.murthy@intel.com> <20240705095551.1244154-2-arun.r.murthy@intel.com> Date: Wed, 07 Aug 2024 12:55:18 +0300 Message-ID: <87r0b04pyx.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 05 Jul 2024, Arun R Murthy wrote: > +/* GLOBAL_HIST related registers */ > +#define _DPST_CTL_A 0x490C0 > +#define _DPST_CTL_B 0x491C0 > +#define DPST_CTL(pipe) _MMIO_PIPE(pipe, _DPST_CTL_A, _DPST_CTL_B) > +#define DPST_CTL_IE_HIST_EN REG_BIT(31) > +#define DPST_CTL_RESTORE REG_BIT(28) > +#define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) > +#define DPST_CTL_HIST_MODE REG_BIT(24) > +#define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) > +#define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) > +#define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) > +#define DPST_CTL_BIN_REG_FUNC_SEL REG_BIT(11) > +#define DPST_CTL_BIN_REG_FUNC_TC REG_FIELD_PREP(DPST_CTL_BIN_REG_FUNC_SEL, 0) > +#define DPST_CTL_BIN_REG_FUNC_IE REG_FIELD_PREP(DPST_CTL_BIN_REG_FUNC_SEL, 1) > +#define DPST_CTL_BIN_REG_MASK REG_GENMASK(6, 0) > +#define DPST_CTL_BIN_REG_CLEAR REG_FIELD_PREP(DPST_CTL_BIN_REG_MASK, 0) > +#define DPST_CTL_IE_TABLE_VALUE_FORMAT_2INT_8FRAC REG_FIELD_PREP(DPST_CTL_IE_TABLE_VALUE_FORMAT, 1) > +#define DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC REG_FIELD_PREP(DPST_CTL_IE_TABLE_VALUE_FORMAT, 0) > +#define DPST_CTL_HIST_MODE_YUV REG_FIELD_PREP(DPST_CTL_HIST_MODE, 0) > +#define DPST_CTL_HIST_MODE_HSV REG_FIELD_PREP(DPST_CTL_HIST_MODE, 1) > + > +#define _DPST_GUARD_A 0x490C8 > +#define _DPST_GUARD_B 0x491C8 > +#define DPST_GUARD(pipe) _MMIO_PIPE(pipe, _DPST_GUARD_A, _DPST_GUARD_B) > +#define DPST_GUARD_HIST_INT_EN REG_BIT(31) > +#define DPST_GUARD_HIST_EVENT_STATUS REG_BIT(30) > +#define DPST_GUARD_INTERRUPT_DELAY_MASK REG_GENMASK(29, 22) > +#define DPST_GUARD_INTERRUPT_DELAY(val) REG_FIELD_PREP(DPST_GUARD_INTERRUPT_DELAY_MASK, val) > +#define DPST_GUARD_THRESHOLD_GB_MASK REG_GENMASK(21, 0) > +#define DPST_GUARD_THRESHOLD_GB(val) REG_FIELD_PREP(DPST_GUARD_THRESHOLD_GB_MASK, val) > + > +#define _DPST_BIN_A 0x490C4 > +#define _DPST_BIN_B 0x491C4 > +#define DPST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B) > +#define DPST_BIN_DATA_MASK REG_GENMASK(23, 0) > +#define DPST_BIN_BUSY REG_BIT(31) PS. The big comment about formatting register definitions at the top of i915_reg.h still applies. -- Jani Nikula, Intel