From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>,
Zhi Wang <zhi.wang.linux@gmail.com>
Subject: Re: [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define
Date: Mon, 13 May 2024 13:23:54 +0300 [thread overview]
Message-ID: <87r0e6f1s5.fsf@intel.com> (raw)
In-Reply-To: <20240510152329.24098-7-ville.syrjala@linux.intel.com>
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 24 ++++++++++-----------
> drivers/gpu/drm/i915/gvt/reg.h | 2 --
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++-----------
> 3 files changed, 24 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 6b02612ddef5..6f633035618e 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>
> MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index e8a56faafe95..90d8eb1761a3 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -57,8 +57,6 @@
>
> #define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
>
> -#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
> -
> #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
>
> #define REG50080_FLIP_TYPE_MASK 0x3
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index cf45342a6db0..ad3bf60855bc 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
> MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
> MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4)));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
> MMIO_D(_MMIO(_PLANE_CTL_3_A));
> MMIO_D(_MMIO(_PLANE_CTL_3_B));
> MMIO_D(_MMIO(0x72380));
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-05-13 10:24 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
2024-05-10 15:23 ` [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC() Ville Syrjala
2024-05-13 9:50 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h Ville Syrjala
2024-05-13 10:07 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h Ville Syrjala
2024-05-13 10:10 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers Ville Syrjala
2024-05-13 10:13 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define Ville Syrjala
2024-05-13 10:21 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define Ville Syrjala
2024-05-13 10:23 ` Jani Nikula [this message]
2024-05-10 15:23 ` [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines Ville Syrjala
2024-05-13 10:25 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines Ville Syrjala
2024-05-13 10:30 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines Ville Syrjala
2024-05-13 10:32 ` Jani Nikula
2024-05-13 16:58 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions Ville Syrjala
2024-05-13 11:28 ` Jani Nikula
2024-05-13 16:13 ` Ville Syrjälä
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
2024-05-13 20:30 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits Ville Syrjala
2024-05-13 10:38 ` Jani Nikula
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines Ville Syrjala
2024-05-13 10:40 ` Jani Nikula
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations Ville Syrjala
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
2024-05-13 20:41 ` Jani Nikula
2024-05-13 20:43 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val() Ville Syrjala
2024-05-13 20:43 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write() Ville Syrjala
2024-05-13 20:46 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers Ville Syrjala
2024-05-13 20:52 ` Jani Nikula
2024-05-15 11:17 ` Ville Syrjälä
2024-05-10 16:28 ` ✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff Patchwork
2024-05-11 20:02 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-05-13 18:39 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: skl+ plane register stuff (rev6) Patchwork
2024-05-13 18:39 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-13 18:55 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-14 2:01 ` ✗ Fi.CI.IGT: failure " Patchwork
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