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d="scan'208";a="30135399" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.246.7]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2024 03:23:57 -0700 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Cc: Zhenyu Wang , Zhi Wang Subject: Re: [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define In-Reply-To: <20240510152329.24098-7-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20240510152329.24098-1-ville.syrjala@linux.intel.com> <20240510152329.24098-7-ville.syrjala@linux.intel.com> Date: Mon, 13 May 2024 13:23:54 +0300 Message-ID: <87r0e6f1s5.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing. > > Cc: Zhenyu Wang > CC: Zhi Wang > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/gvt/handlers.c | 24 ++++++++++----------- > drivers/gpu/drm/i915/gvt/reg.h | 2 -- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++----------- > 3 files changed, 24 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/g= vt/handlers.c > index 6b02612ddef5..6f633035618e 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *g= vt) > MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); > MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); >=20=20 > - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); >=20=20 > - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); >=20=20 > - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); >=20=20 > MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); >=20=20 > diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/re= g.h > index e8a56faafe95..90d8eb1761a3 100644 > --- a/drivers/gpu/drm/i915/gvt/reg.h > +++ b/drivers/gpu/drm/i915/gvt/reg.h > @@ -57,8 +57,6 @@ >=20=20 > #define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) >=20=20 > -#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) *= 0x100) > - > #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 += (pipe)) >=20=20 > #define REG50080_FLIP_TYPE_MASK 0x3 > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/dr= m/i915/intel_gvt_mmio_table.c > index cf45342a6db0..ad3bf60855bc 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt= _mmio_table_iter *iter) > MMIO_D(PLANE_AUX_DIST(PIPE_C, 1)); > MMIO_D(PLANE_AUX_DIST(PIPE_C, 2)); > MMIO_D(PLANE_AUX_DIST(PIPE_C, 3)); > - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4))); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); > MMIO_D(_MMIO(_PLANE_CTL_3_A)); > MMIO_D(_MMIO(_PLANE_CTL_3_B)); > MMIO_D(_MMIO(0x72380)); --=20 Jani Nikula, Intel