From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E47C1C6FD1D for ; Thu, 30 Mar 2023 22:49:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E358B10F084; Thu, 30 Mar 2023 22:49:27 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35EE310F084 for ; Thu, 30 Mar 2023 22:49:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680216566; x=1711752566; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=PfjzrwtVLA2zhsiZQcwfHtQyLdnJ8fq6f1CLXFWn4/8=; b=mtqRbhK1+S6BK9hAdGthbYx0PRDz7svj6yAX0zfsiZymGqQkD+GebxCm cPuOprctNCQR+p4aIKRltXSmkzNv3xkSg5obX7lWH54t/deQlE1b1BZ3p j7LpUVlb49iUSWbZtla4pP7CMbMlXXfKMw3+JS8f7dMJpoHsHOxUUYHHw +4yJJdBraXKMj9dWtcVW7xWUKmI7XM9kM8XWRZtN48J9IQxbhT3CZK0xa Le8l0CHU7LDlNQ5ayX0UOcuhu+aPFRcHl9xW4TzGT5zYV6rptOau/fnlT pFFGnuvL3x/bVrfSSYhazG5Uo3x2T3DGabYLE9f8wIoESRu+dfdqqhe5a g==; X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="329828656" X-IronPort-AV: E=Sophos;i="5.98,306,1673942400"; d="scan'208";a="329828656" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2023 15:49:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="930912591" X-IronPort-AV: E=Sophos;i="5.98,306,1673942400"; d="scan'208";a="930912591" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.16.72]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2023 15:49:25 -0700 Date: Thu, 30 Mar 2023 15:28:26 -0700 Message-ID: <87r0t5dgc5.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Tvrtko Ursulin In-Reply-To: <1036f396-f5d6-82bd-27ff-66146b115184@linux.intel.com> References: <20230330004103.1295413-1-umesh.nerlige.ramappa@intel.com> <20230330004103.1295413-6-umesh.nerlige.ramappa@intel.com> <1036f396-f5d6-82bd-27ff-66146b115184@linux.intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 5/9] drm/i915/pmu: Prepare for multi-tile non-engine counters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 30 Mar 2023 05:39:04 -0700, Tvrtko Ursulin wrote: > Hi Tvrtko, > > diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h > > index 1b04c79907e8..a708e44a227e 100644 > > --- a/drivers/gpu/drm/i915/i915_pmu.h > > +++ b/drivers/gpu/drm/i915/i915_pmu.h > > @@ -38,13 +38,16 @@ enum { > > __I915_NUM_PMU_SAMPLERS > > }; > > +#define I915_PMU_MAX_GTS (4) /* FIXME */ > > 3-4 years since writing this I have no idea what I meant by this > FIXME. Should have put a better comment.. :( It was early platform > enablement times so it was somewhat passable, but now I think we need to > figure out what I actually meant. Maybe removing the comment is fine. > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > index dba7c5a5b25e..bbab7f3dbeb4 100644 > > --- a/include/uapi/drm/i915_drm.h > > +++ b/include/uapi/drm/i915_drm.h > > @@ -280,7 +280,17 @@ enum drm_i915_pmu_engine_sample { > > #define I915_PMU_ENGINE_SEMA(class, instance) \ > > __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) > > -#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + > > (x)) > > +/* > > + * Top 8 bits of every non-engine counter are GT id. > > + * FIXME: __I915_PMU_GT_SHIFT will be changed to 56 > > + */ > > I asked before and don't think I got an answer: Why is 4 bits not enough > for gt id? The comment is not my code I am pretty sure. Both of the above FIXME's are the work of yours truly :-) (added during PRELIM work). Anyway given that now i915 will not support new product generations I think we can just drop the FIXME's. Otherwise I was saying since we are only using a few bottom bits, why not future proof things a bit and allow for num_gt's to expand beyond 16. So for now just drop the FIXME's for i915, revisit if needed with xe. Thanks. -- Ashutosh