From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE45EC433F5 for ; Wed, 9 Feb 2022 13:35:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C26210E130; Wed, 9 Feb 2022 13:35:46 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2A94110E130 for ; Wed, 9 Feb 2022 13:35:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644413745; x=1675949745; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=ymLlqP0npZDxHpjYOctdR8gU1I0ytHZI6kzqmu4qOyM=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 5/7] drm/i915: Extract hsw_ips_get_config() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 09 Feb 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Pull the IPS state readout into hsw_ips.c. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/hsw_ips.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/i915/display/hsw_ips.h | 1 + > drivers/gpu/drm/i915/display/intel_display.c | 14 +------------- > 3 files changed, 22 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i91= 5/display/hsw_ips.c > index fb34ef615025..38014e0cc9ad 100644 > --- a/drivers/gpu/drm/i915/display/hsw_ips.c > +++ b/drivers/gpu/drm/i915/display/hsw_ips.c > @@ -249,3 +249,23 @@ int hsw_ips_compute_config(struct intel_atomic_state= *state, >=20=20 > return 0; > } > + > +void hsw_ips_get_config(struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); > + struct drm_i915_private *i915 =3D to_i915(crtc->base.dev); > + > + if (!hsw_crtc_supports_ips(crtc)) > + return; > + > + if (IS_HASWELL(i915)) { > + crtc_state->ips_enabled =3D intel_de_read(i915, IPS_CTL) & IPS_ENABLE; > + } else { > + /* > + * We cannot readout IPS state on broadwell, set to > + * true so we can set it to a defined state on first > + * commit. > + */ > + crtc_state->ips_enabled =3D true; > + } > +} > diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i91= 5/display/hsw_ips.h > index d63bdef5100a..4564dee497d7 100644 > --- a/drivers/gpu/drm/i915/display/hsw_ips.h > +++ b/drivers/gpu/drm/i915/display/hsw_ips.h > @@ -21,5 +21,6 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc); > bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_stat= e); > int hsw_ips_compute_config(struct intel_atomic_state *state, > struct intel_crtc *crtc); > +void hsw_ips_get_config(struct intel_crtc_state *crtc_state); >=20=20 > #endif /* __HSW_IPS_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/d= rm/i915/display/intel_display.c > index 134527981e2b..cdfee4ba1166 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -4191,19 +4191,7 @@ static bool hsw_get_pipe_config(struct intel_crtc = *crtc, > ilk_get_pfit_config(pipe_config); > } >=20=20 > - if (hsw_crtc_supports_ips(crtc)) { > - if (IS_HASWELL(dev_priv)) > - pipe_config->ips_enabled =3D intel_de_read(dev_priv, > - IPS_CTL) & IPS_ENABLE; > - else { > - /* > - * We cannot readout IPS state on broadwell, set to > - * true so we can set it to a defined state on first > - * commit. > - */ > - pipe_config->ips_enabled =3D true; > - } > - } > + hsw_ips_get_config(pipe_config); >=20=20 > if (pipe_config->cpu_transcoder !=3D TRANSCODER_EDP && > !transcoder_is_dsi(pipe_config->cpu_transcoder)) { --=20 Jani Nikula, Intel Open Source Graphics Center