From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11978C433EF for ; Tue, 12 Oct 2021 09:13:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A64CF60EFE for ; Tue, 12 Oct 2021 09:13:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A64CF60EFE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F343C89ECB; Tue, 12 Oct 2021 09:13:35 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0A72889ECB for ; Tue, 12 Oct 2021 09:13:34 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10134"; a="207205851" X-IronPort-AV: E=Sophos;i="5.85,367,1624345200"; d="scan'208";a="207205851" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2021 02:13:34 -0700 X-IronPort-AV: E=Sophos;i="5.85,367,1624345200"; d="scan'208";a="490884623" Received: from pakumpul-mobl1.ger.corp.intel.com (HELO localhost) ([10.249.40.207]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2021 02:13:33 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: Ville =?utf-8?B?U3lyasOkbMOk?= In-Reply-To: <20211011182144.22074-1-jani.nikula@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20211011182144.22074-1-jani.nikula@intel.com> Date: Tue, 12 Oct 2021 12:13:29 +0300 Message-ID: <87r1cqzjuu.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: abstract intel_dp_lane_max_vswing_reached() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 11 Oct 2021, Jani Nikula wrote: > Add per-lane abstraction for max vswing reached to make follow-up > cleaner, as this one reverses the conditions. > > v2: both conditions need to be true, reverse (Ville) > > Cc: Ville Syrj=C3=A4l=C3=A4 > Signed-off-by: Jani Nikula Pushed both with Ville's IRC r-b, thanks for the review. BR, Jani. > --- > .../drm/i915/display/intel_dp_link_training.c | 42 +++++++++++-------- > 1 file changed, 25 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/driv= ers/gpu/drm/i915/display/intel_dp_link_training.c > index 1a943ae38a6b..1d4bcb91cd3b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -515,29 +515,37 @@ intel_dp_update_link_train(struct intel_dp *intel_d= p, > return ret =3D=3D crtc_state->lane_count; > } >=20=20 > +/* > + * FIXME: The DP spec is very confusing here, also the Link CTS spec see= ms to > + * have self contradicting tests around this area. > + * > + * In lieu of better ideas let's just stop when we've reached the max su= pported > + * vswing with its max pre-emphasis, which is either 2+1 or 3+0 dependin= g on > + * whether vswing level 3 is supported or not. > + */ > +static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) > +{ > + u8 v =3D (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> > + DP_TRAIN_VOLTAGE_SWING_SHIFT; > + u8 p =3D (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> > + DP_TRAIN_PRE_EMPHASIS_SHIFT; > + > + if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) =3D=3D 0) > + return false; > + > + if (v + p !=3D 3) > + return false; > + > + return true; > +} > + > static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state) > { > int lane; >=20=20 > - /* > - * FIXME: The DP spec is very confusing here, also the Link CTS > - * spec seems to have self contradicting tests around this area. > - * > - * In lieu of better ideas let's just stop when we've reached the > - * max supported vswing with its max pre-emphasis, which is either > - * 2+1 or 3+0 depending on whether vswing level 3 is supported or not. > - */ > for (lane =3D 0; lane < crtc_state->lane_count; lane++) { > - u8 v =3D (intel_dp->train_set[lane] & DP_TRAIN_VOLTAGE_SWING_MASK) >> > - DP_TRAIN_VOLTAGE_SWING_SHIFT; > - u8 p =3D (intel_dp->train_set[lane] & DP_TRAIN_PRE_EMPHASIS_MASK) >> > - DP_TRAIN_PRE_EMPHASIS_SHIFT; > - > - if ((intel_dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) =3D=3D 0) > - return false; > - > - if (v + p !=3D 3) > + if (!intel_dp_lane_max_vswing_reached(intel_dp->train_set[lane])) > return false; > } --=20 Jani Nikula, Intel Open Source Graphics Center