From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42B41C433F5 for ; Wed, 8 Sep 2021 09:33:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D70B261153 for ; Wed, 8 Sep 2021 09:33:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D70B261153 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FF1D6E092; Wed, 8 Sep 2021 09:33:30 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 208796E092 for ; Wed, 8 Sep 2021 09:33:29 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10100"; a="281450740" X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="281450740" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 02:33:28 -0700 X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="538472872" Received: from mdoerbec-mobl1.ger.corp.intel.com (HELO localhost) ([10.249.33.106]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 02:33:26 -0700 From: Jani Nikula To: Dave Airlie , intel-gfx@lists.freedesktop.org Cc: Dave Airlie , Ville =?utf-8?B?U3lyasOkbMOk?= In-Reply-To: <20210908003944.2972024-4-airlied@gmail.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20210908003944.2972024-1-airlied@gmail.com> <20210908003944.2972024-4-airlied@gmail.com> Date: Wed, 08 Sep 2021 12:33:23 +0300 Message-ID: <87r1dz76os.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Subject: Re: [Intel-gfx] [PATCH 03/21] drm/i915/wm: move the update watermark wrapper to display side. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 08 Sep 2021, Dave Airlie wrote: > From: Dave Airlie > > A vague goal is to have the vfunc table be the api between > wm and display, not having direction function calls cross > the boundary. > > This aligns the legacy update_wm with the newer vfuncs. > > The comment probably needs to live somewhere else, it seems > like it should live in the pm side though not the display side, > but I brought it along for the ride. > --- > drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_pm.c | 39 ------------------- > drivers/gpu/drm/i915/intel_pm.h | 1 - > 3 files changed, 40 insertions(+), 40 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index d95283bf2631..b495371c1889 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c We haven't been axing stuff out of intel_display.c so we could add somethign else back! ;) A new file for watermarks or display pm? Ville? BR, Jani. > @@ -125,6 +125,46 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); > static void intel_modeset_setup_hw_state(struct drm_device *dev, > struct drm_modeset_acquire_ctx *ctx); > > + > +/** > + * intel_update_watermarks - update FIFO watermark values based on current modes > + * @crtc: the #intel_crtc on which to compute the WM > + * > + * Calculate watermark values for the various WM regs based on current mode > + * and plane configuration. > + * > + * There are several cases to deal with here: > + * - normal (i.e. non-self-refresh) > + * - self-refresh (SR) mode > + * - lines are large relative to FIFO size (buffer can hold up to 2) > + * - lines are small relative to FIFO size (buffer can hold more than 2 > + * lines), so need to account for TLB latency > + * > + * The normal calculation is: > + * watermark = dotclock * bytes per pixel * latency > + * where latency is platform & configuration dependent (we assume pessimal > + * values here). > + * > + * The SR calculation is: > + * watermark = (trunc(latency/line time)+1) * surface width * > + * bytes per pixel > + * where > + * line time = htotal / dotclock > + * surface width = hdisplay for normal plane and 64 for cursor > + * and latency is assumed to be high, as above. > + * > + * The final value programmed to the register should always be rounded up, > + * and include an extra 2 entries to account for clock crossings. > + * > + * We don't use the sprite, so we can ignore that. And on Crestline we have > + * to set the non-SR watermarks to 8. > + */ > +static void intel_update_watermarks(struct drm_i915_private *dev_priv) > +{ > + if (dev_priv->display.update_wm) > + dev_priv->display.update_wm(dev_priv); > +} > + > /* returns HPLL frequency in kHz */ > int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) > { > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 406baa49e6ad..4054c6f7a2f9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7132,45 +7132,6 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv) > !(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS); > } > > -/** > - * intel_update_watermarks - update FIFO watermark values based on current modes > - * @crtc: the #intel_crtc on which to compute the WM > - * > - * Calculate watermark values for the various WM regs based on current mode > - * and plane configuration. > - * > - * There are several cases to deal with here: > - * - normal (i.e. non-self-refresh) > - * - self-refresh (SR) mode > - * - lines are large relative to FIFO size (buffer can hold up to 2) > - * - lines are small relative to FIFO size (buffer can hold more than 2 > - * lines), so need to account for TLB latency > - * > - * The normal calculation is: > - * watermark = dotclock * bytes per pixel * latency > - * where latency is platform & configuration dependent (we assume pessimal > - * values here). > - * > - * The SR calculation is: > - * watermark = (trunc(latency/line time)+1) * surface width * > - * bytes per pixel > - * where > - * line time = htotal / dotclock > - * surface width = hdisplay for normal plane and 64 for cursor > - * and latency is assumed to be high, as above. > - * > - * The final value programmed to the register should always be rounded up, > - * and include an extra 2 entries to account for clock crossings. > - * > - * We don't use the sprite, so we can ignore that. And on Crestline we have > - * to set the non-SR watermarks to 8. > - */ > -void intel_update_watermarks(struct drm_i915_private *dev_priv) > -{ > - if (dev_priv->display.update_wm) > - dev_priv->display.update_wm(dev_priv); > -} > - > void intel_enable_ipc(struct drm_i915_private *dev_priv) > { > u32 val; > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h > index 99bce0b4f5fb..990cdcaf85ce 100644 > --- a/drivers/gpu/drm/i915/intel_pm.h > +++ b/drivers/gpu/drm/i915/intel_pm.h > @@ -29,7 +29,6 @@ struct skl_wm_level; > void intel_init_clock_gating(struct drm_i915_private *dev_priv); > void intel_suspend_hw(struct drm_i915_private *dev_priv); > int ilk_wm_max_level(const struct drm_i915_private *dev_priv); > -void intel_update_watermarks(struct drm_i915_private *dev_priv); > void intel_init_pm(struct drm_i915_private *dev_priv); > void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); > void intel_pm_setup(struct drm_i915_private *dev_priv); -- Jani Nikula, Intel Open Source Graphics Center