* [PATCH 01/17] drm/i915: small isolated c99 types to kernel types switch
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-16 9:17 ` Chris Wilson
2019-01-17 0:27 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 02/17] drm/i915/crt: switch to kernel types Jani Nikula
` (21 subsequent siblings)
22 siblings, 2 replies; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Minor checkpatch fixes sprinkled on top of the changed lines.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 14 +++++++-------
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 8 ++++----
drivers/gpu/drm/i915/i915_gpu_error.c | 10 +++++-----
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_atomic.c | 4 ++--
drivers/gpu/drm/i915/intel_atomic_plane.c | 4 ++--
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/intel_dpio_phy.c | 18 +++++++++---------
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++++++------
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 12 ++++++------
drivers/gpu/drm/i915/intel_hdcp.c | 4 ++--
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_pipe_crc.c | 18 +++++++++---------
drivers/gpu/drm/i915/intel_psr.c | 6 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++++----------
18 files changed, 72 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 80264cb9ca7f..d15f7200c0e7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -710,8 +710,8 @@ void i915_gem_object_free(struct drm_i915_gem_object *obj)
static int
i915_gem_create(struct drm_file *file,
struct drm_i915_private *dev_priv,
- uint64_t size,
- uint32_t *handle_p)
+ u64 size,
+ u32 *handle_p)
{
struct drm_i915_gem_object *obj;
int ret;
@@ -1570,8 +1570,8 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
{
struct drm_i915_gem_set_domain *args = data;
struct drm_i915_gem_object *obj;
- uint32_t read_domains = args->read_domains;
- uint32_t write_domain = args->write_domain;
+ u32 read_domains = args->read_domains;
+ u32 write_domain = args->write_domain;
int err;
/* Only handle setting domains to types used by the CPU. */
@@ -1753,7 +1753,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
if (IS_ERR((void *)addr))
return addr;
- args->addr_ptr = (uint64_t) addr;
+ args->addr_ptr = (u64)addr;
return 0;
}
@@ -2155,8 +2155,8 @@ static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
int
i915_gem_mmap_gtt(struct drm_file *file,
struct drm_device *dev,
- uint32_t handle,
- uint64_t *offset)
+ u32 handle,
+ u64 *offset)
{
struct drm_i915_gem_object *obj;
int ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index f7947d89cf45..46e259661294 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -555,8 +555,8 @@ void i915_gem_restore_fences(struct drm_i915_private *dev_priv)
void
i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
{
- uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
- uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+ u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
+ u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
/*
@@ -579,7 +579,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
} else {
- uint32_t dimm_c0, dimm_c1;
+ u32 dimm_c0, dimm_c1;
dimm_c0 = I915_READ(MAD_DIMM_C0);
dimm_c1 = I915_READ(MAD_DIMM_C1);
dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
@@ -611,7 +611,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if (IS_MOBILE(dev_priv) ||
IS_I915G(dev_priv) || IS_I945G(dev_priv)) {
- uint32_t dcc;
+ u32 dcc;
/* On 9xx chipsets, channel interleave by the CPU is
* determined by DCC. For single-channel, neither the CPU
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5eaf586c4d48..1f8e80e31b49 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1082,7 +1082,7 @@ i915_error_object_create(struct drm_i915_private *i915,
/* The error capture is special as tries to run underneath the normal
* locking rules - so we use the raw version of the i915_gem_active lookup.
*/
-static inline uint32_t
+static inline u32
__active_get_seqno(struct i915_gem_active *active)
{
struct i915_request *request;
@@ -1153,11 +1153,11 @@ static u32 capture_error_bo(struct drm_i915_error_buffer *err,
*
* It's only a small step better than a random number in its current form.
*/
-static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
- struct i915_gpu_state *error,
- int *engine_id)
+static u32 i915_error_generate_code(struct drm_i915_private *dev_priv,
+ struct i915_gpu_state *error,
+ int *engine_id)
{
- uint32_t error_code = 0;
+ u32 error_code = 0;
int i;
/* IPEHR would be an ideal way to detect errors, as it's the gross
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index faff6cf1aaa1..727118301f91 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3021,7 +3021,7 @@ static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
(addr >= 0x182300 && addr <= 0x1823A4);
}
-static uint32_t mask_reg_value(u32 reg, u32 val)
+static u32 mask_reg_value(u32 reg, u32 val)
{
/* HALF_SLICE_CHICKEN2 is programmed with a the
* WaDisableSTUnitPowerOptimization workaround. Make sure the value
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fad5a9e8b44d..9a1340cfda6c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -117,14 +117,14 @@
*/
typedef struct {
- uint32_t reg;
+ u32 reg;
} i915_reg_t;
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
#define INVALID_MMIO_REG _MMIO(0)
-static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
+static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
{
return reg.reg;
}
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index d8dbc9980281..16263add3cdd 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -46,7 +46,7 @@
int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
const struct drm_connector_state *state,
struct drm_property *property,
- uint64_t *val)
+ u64 *val)
{
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -78,7 +78,7 @@ int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
struct drm_connector_state *state,
struct drm_property *property,
- uint64_t val)
+ u64 val)
{
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 683a75dad4fb..9a2fdc77ebcb 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -311,7 +311,7 @@ int
intel_plane_atomic_get_property(struct drm_plane *plane,
const struct drm_plane_state *state,
struct drm_property *property,
- uint64_t *val)
+ u64 *val)
{
DRM_DEBUG_KMS("Unknown property [PROP:%d:%s]\n",
property->base.id, property->name);
@@ -334,7 +334,7 @@ int
intel_plane_atomic_set_property(struct drm_plane *plane,
struct drm_plane_state *state,
struct drm_property *property,
- uint64_t val)
+ u64 val)
{
DRM_DEBUG_KMS("Unknown property [PROP:%d:%s]\n",
property->base.id, property->name);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index a19699023db1..f90041cb336d 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -247,7 +247,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
int ret;
- uint32_t temp;
+ u32 temp;
/* MST encoders are bound to a crtc, not to a connector,
* force the mapping here for get_hw_state.
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 3c7f10d17658..95cb8b154f87 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -413,7 +413,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
}
if (phy_info->rcomp_phy != -1) {
- uint32_t grc_code;
+ u32 grc_code;
bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
@@ -445,7 +445,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
{
const struct bxt_ddi_phy_info *phy_info;
- uint32_t val;
+ u32 val;
phy_info = bxt_get_phy_info(dev_priv, phy);
@@ -515,7 +515,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
{
const struct bxt_ddi_phy_info *phy_info;
- uint32_t mask;
+ u32 mask;
bool ok;
phy_info = bxt_get_phy_info(dev_priv, phy);
@@ -567,8 +567,8 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
#undef _CHK
}
-uint8_t
-bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count)
+u8
+bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
{
switch (lane_count) {
case 1:
@@ -585,7 +585,7 @@ bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count)
}
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
- uint8_t lane_lat_optim_mask)
+ u8 lane_lat_optim_mask)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
@@ -610,7 +610,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
}
}
-uint8_t
+u8
bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -618,7 +618,7 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
enum dpio_phy phy;
enum dpio_channel ch;
int lane;
- uint8_t mask;
+ u8 mask;
bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
@@ -739,7 +739,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
enum pipe pipe = crtc->pipe;
- uint32_t val;
+ u32 val;
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
if (reset)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index bf4dae2649ab..59216dd8bfa1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -799,15 +799,15 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
return mcr_s_ss_select;
}
-static inline uint32_t
+static inline u32
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
int subslice, i915_reg_t reg)
{
- uint32_t mcr_slice_subslice_mask;
- uint32_t mcr_slice_subslice_select;
- uint32_t default_mcr_s_ss_select;
- uint32_t mcr;
- uint32_t ret;
+ u32 mcr_slice_subslice_mask;
+ u32 mcr_slice_subslice_select;
+ u32 default_mcr_s_ss_select;
+ u32 mcr;
+ u32 ret;
enum forcewake_domains fw_domains;
if (INTEL_GEN(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index ccd5e110a19c..ec72be4b7a7b 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -594,7 +594,7 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv,
}
static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
- uint32_t pixel_format)
+ u32 pixel_format)
{
switch (pixel_format) {
case DRM_FORMAT_XRGB8888:
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 9b39975c8389..3b9285130ef5 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -127,8 +127,8 @@ static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
enum pipe pipe, bool enable)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
- DE_PIPEB_FIFO_UNDERRUN;
+ u32 bit = (pipe == PIPE_A) ?
+ DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
if (enable)
ilk_enable_display_irq(dev_priv, bit);
@@ -140,7 +140,7 @@ static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- uint32_t err_int = I915_READ(GEN7_ERR_INT);
+ u32 err_int = I915_READ(GEN7_ERR_INT);
lockdep_assert_held(&dev_priv->irq_lock);
@@ -193,8 +193,8 @@ static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
bool enable)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- uint32_t bit = (pch_transcoder == PIPE_A) ?
- SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
+ u32 bit = (pch_transcoder == PIPE_A) ?
+ SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
if (enable)
ibx_enable_display_interrupt(dev_priv, bit);
@@ -206,7 +206,7 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pch_transcoder = crtc->pipe;
- uint32_t serr_int = I915_READ(SERR_INT);
+ u32 serr_int = I915_READ(SERR_INT);
lockdep_assert_held(&dev_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 3fcb3b775948..ce7ba3a9c000 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -838,8 +838,8 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state)
{
- uint64_t old_cp = old_state->content_protection;
- uint64_t new_cp = new_state->content_protection;
+ u64 old_cp = old_state->content_protection;
+ u64 new_cp = new_state->content_protection;
struct drm_crtc_state *crtc_state;
if (!new_state->crtc) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 608458b92db3..1d4bebcd4c8b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2608,7 +2608,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
{
struct drm_i915_gem_object *ctx_obj;
struct i915_vma *vma;
- uint32_t context_size;
+ u32 context_size;
struct intel_ring *ring;
struct i915_timeline *timeline;
int ret;
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 56d614b02302..a8554dc4f196 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -44,7 +44,7 @@ static const char * const pipe_crc_sources[] = {
};
static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
- uint32_t *val)
+ u32 *val)
{
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
@@ -120,7 +120,7 @@ static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source *source,
- uint32_t *val)
+ u32 *val)
{
bool need_stable_symbols = false;
@@ -165,7 +165,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
* - DisplayPort scrambling: used for EMI reduction
*/
if (need_stable_symbols) {
- uint32_t tmp = I915_READ(PORT_DFT2_G4X);
+ u32 tmp = I915_READ(PORT_DFT2_G4X);
tmp |= DC_BALANCE_RESET_VLV;
switch (pipe) {
@@ -190,7 +190,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source *source,
- uint32_t *val)
+ u32 *val)
{
bool need_stable_symbols = false;
@@ -244,7 +244,7 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
* - DisplayPort scrambling: used for EMI reduction
*/
if (need_stable_symbols) {
- uint32_t tmp = I915_READ(PORT_DFT2_G4X);
+ u32 tmp = I915_READ(PORT_DFT2_G4X);
WARN_ON(!IS_G4X(dev_priv));
@@ -265,7 +265,7 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- uint32_t tmp = I915_READ(PORT_DFT2_G4X);
+ u32 tmp = I915_READ(PORT_DFT2_G4X);
switch (pipe) {
case PIPE_A:
@@ -289,7 +289,7 @@ static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- uint32_t tmp = I915_READ(PORT_DFT2_G4X);
+ u32 tmp = I915_READ(PORT_DFT2_G4X);
if (pipe == PIPE_A)
tmp &= ~PIPE_A_SCRAMBLE_RESET;
@@ -304,7 +304,7 @@ static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
}
static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
- uint32_t *val)
+ u32 *val)
{
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
@@ -392,7 +392,7 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source *source,
- uint32_t *val,
+ u32 *val,
bool set_wa)
{
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0f6b2b4702e3..8dbf26c212cc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -230,7 +230,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
{
- uint8_t dprx = 0;
+ u8 dprx = 0;
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
&dprx) != 1)
@@ -240,7 +240,7 @@ static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
{
- uint8_t alpm_caps = 0;
+ u8 alpm_caps = 0;
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
&alpm_caps) != 1)
@@ -384,7 +384,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 aux_clock_divider, aux_ctl;
int i;
- static const uint8_t aux_msg[] = {
+ static const u8 aux_msg[] = {
[0] = DP_AUX_NATIVE_WRITE << 4,
[1] = DP_SET_POWER >> 8,
[2] = DP_SET_POWER & 0xff,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 3c1366c58cf3..616f6bbb18ad 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -28,7 +28,7 @@ struct i915_sched_attr;
* workarounds!
*/
#define CACHELINE_BYTES 64
-#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
+#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
struct intel_hw_status_page {
struct i915_vma *vma;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 79f00610860b..a017a4232c0f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -903,10 +903,10 @@ void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
* back on and register state is restored. This is guaranteed by the MMIO write
* to DC_STATE_EN blocking until the state is restored.
*/
-static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
+static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
{
- uint32_t val;
- uint32_t mask;
+ u32 val;
+ u32 mask;
if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
state &= dev_priv->csr.allowed_dc_mask;
@@ -1538,7 +1538,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
{
enum dpio_phy phy;
enum pipe pipe;
- uint32_t tmp;
+ u32 tmp;
WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
@@ -3328,10 +3328,10 @@ sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
return 1;
}
-static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
- int enable_dc)
+static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
+ int enable_dc)
{
- uint32_t mask;
+ u32 mask;
int requested_dc;
int max_dc;
@@ -3596,7 +3596,7 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
static void icl_mbus_init(struct drm_i915_private *dev_priv)
{
- uint32_t val;
+ u32 val;
val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
MBUS_ABOX_BT_CREDIT_POOL2(16) |
@@ -3907,7 +3907,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* current lane status.
*/
if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
- uint32_t status = I915_READ(DPLL(PIPE_A));
+ u32 status = I915_READ(DPLL(PIPE_A));
unsigned int mask;
mask = status & DPLL_PORTB_READY_MASK;
@@ -3938,7 +3938,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
}
if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
- uint32_t status = I915_READ(DPIO_PHY_STATUS);
+ u32 status = I915_READ(DPIO_PHY_STATUS);
unsigned int mask;
mask = status & DPLL_PORTD_READY_MASK;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 01/17] drm/i915: small isolated c99 types to kernel types switch
2019-01-16 9:15 ` [PATCH 01/17] drm/i915: small isolated c99 types to kernel types switch Jani Nikula
@ 2019-01-16 9:17 ` Chris Wilson
2019-01-17 0:27 ` Souza, Jose
1 sibling, 0 replies; 46+ messages in thread
From: Chris Wilson @ 2019-01-16 9:17 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Quoting Jani Nikula (2019-01-16 09:15:19)
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch fixes sprinkled on top of the changed lines.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Of course it messes up adjacent line lengths in place, small price to
pay.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 01/17] drm/i915: small isolated c99 types to kernel types switch
2019-01-16 9:15 ` [PATCH 01/17] drm/i915: small isolated c99 types to kernel types switch Jani Nikula
2019-01-16 9:17 ` Chris Wilson
@ 2019-01-17 0:27 ` Souza, Jose
1 sibling, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:27 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 24348 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch fixes sprinkled on top of the changed lines.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 14 +++++++-------
> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 8 ++++----
> drivers/gpu/drm/i915/i915_gpu_error.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_atomic.c | 4 ++--
> drivers/gpu/drm/i915/intel_atomic_plane.c | 4 ++--
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/intel_dpio_phy.c | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_hdcp.c | 4 ++--
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/intel_pipe_crc.c | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_psr.c | 6 +++---
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++++----------
> 18 files changed, 72 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index 80264cb9ca7f..d15f7200c0e7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -710,8 +710,8 @@ void i915_gem_object_free(struct
> drm_i915_gem_object *obj)
> static int
> i915_gem_create(struct drm_file *file,
> struct drm_i915_private *dev_priv,
> - uint64_t size,
> - uint32_t *handle_p)
> + u64 size,
> + u32 *handle_p)
> {
> struct drm_i915_gem_object *obj;
> int ret;
> @@ -1570,8 +1570,8 @@ i915_gem_set_domain_ioctl(struct drm_device
> *dev, void *data,
> {
> struct drm_i915_gem_set_domain *args = data;
> struct drm_i915_gem_object *obj;
> - uint32_t read_domains = args->read_domains;
> - uint32_t write_domain = args->write_domain;
> + u32 read_domains = args->read_domains;
> + u32 write_domain = args->write_domain;
> int err;
>
> /* Only handle setting domains to types used by the CPU. */
> @@ -1753,7 +1753,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev,
> void *data,
> if (IS_ERR((void *)addr))
> return addr;
>
> - args->addr_ptr = (uint64_t) addr;
> + args->addr_ptr = (u64)addr;
>
> return 0;
> }
> @@ -2155,8 +2155,8 @@ static void
> i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
> int
> i915_gem_mmap_gtt(struct drm_file *file,
> struct drm_device *dev,
> - uint32_t handle,
> - uint64_t *offset)
> + u32 handle,
> + u64 *offset)
> {
> struct drm_i915_gem_object *obj;
> int ret;
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index f7947d89cf45..46e259661294 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -555,8 +555,8 @@ void i915_gem_restore_fences(struct
> drm_i915_private *dev_priv)
> void
> i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
> {
> - uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> - uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> + u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> + u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>
> if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
> /*
> @@ -579,7 +579,7 @@ i915_gem_detect_bit_6_swizzle(struct
> drm_i915_private *dev_priv)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> }
> } else {
> - uint32_t dimm_c0, dimm_c1;
> + u32 dimm_c0, dimm_c1;
> dimm_c0 = I915_READ(MAD_DIMM_C0);
> dimm_c1 = I915_READ(MAD_DIMM_C1);
> dimm_c0 &= MAD_DIMM_A_SIZE_MASK |
> MAD_DIMM_B_SIZE_MASK;
> @@ -611,7 +611,7 @@ i915_gem_detect_bit_6_swizzle(struct
> drm_i915_private *dev_priv)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> } else if (IS_MOBILE(dev_priv) ||
> IS_I915G(dev_priv) || IS_I945G(dev_priv)) {
> - uint32_t dcc;
> + u32 dcc;
>
> /* On 9xx chipsets, channel interleave by the CPU is
> * determined by DCC. For single-channel, neither the
> CPU
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 5eaf586c4d48..1f8e80e31b49 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1082,7 +1082,7 @@ i915_error_object_create(struct
> drm_i915_private *i915,
> /* The error capture is special as tries to run underneath the
> normal
> * locking rules - so we use the raw version of the i915_gem_active
> lookup.
> */
> -static inline uint32_t
> +static inline u32
> __active_get_seqno(struct i915_gem_active *active)
> {
> struct i915_request *request;
> @@ -1153,11 +1153,11 @@ static u32 capture_error_bo(struct
> drm_i915_error_buffer *err,
> *
> * It's only a small step better than a random number in its current
> form.
> */
> -static uint32_t i915_error_generate_code(struct drm_i915_private
> *dev_priv,
> - struct i915_gpu_state *error,
> - int *engine_id)
> +static u32 i915_error_generate_code(struct drm_i915_private
> *dev_priv,
> + struct i915_gpu_state *error,
> + int *engine_id)
> {
> - uint32_t error_code = 0;
> + u32 error_code = 0;
> int i;
>
> /* IPEHR would be an ideal way to detect errors, as it's the
> gross
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index faff6cf1aaa1..727118301f91 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3021,7 +3021,7 @@ static bool chv_is_valid_mux_addr(struct
> drm_i915_private *dev_priv, u32 addr)
> (addr >= 0x182300 && addr <= 0x1823A4);
> }
>
> -static uint32_t mask_reg_value(u32 reg, u32 val)
> +static u32 mask_reg_value(u32 reg, u32 val)
> {
> /* HALF_SLICE_CHICKEN2 is programmed with a the
> * WaDisableSTUnitPowerOptimization workaround. Make sure the
> value
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index fad5a9e8b44d..9a1340cfda6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -117,14 +117,14 @@
> */
>
> typedef struct {
> - uint32_t reg;
> + u32 reg;
> } i915_reg_t;
>
> #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
>
> #define INVALID_MMIO_REG _MMIO(0)
>
> -static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
> +static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
> {
> return reg.reg;
> }
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> b/drivers/gpu/drm/i915/intel_atomic.c
> index d8dbc9980281..16263add3cdd 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -46,7 +46,7 @@
> int intel_digital_connector_atomic_get_property(struct drm_connector
> *connector,
> const struct
> drm_connector_state *state,
> struct drm_property
> *property,
> - uint64_t *val)
> + u64 *val)
> {
> struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -78,7 +78,7 @@ int
> intel_digital_connector_atomic_get_property(struct drm_connector
> *connector,
> int intel_digital_connector_atomic_set_property(struct drm_connector
> *connector,
> struct
> drm_connector_state *state,
> struct drm_property
> *property,
> - uint64_t val)
> + u64 val)
> {
> struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 683a75dad4fb..9a2fdc77ebcb 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -311,7 +311,7 @@ int
> intel_plane_atomic_get_property(struct drm_plane *plane,
> const struct drm_plane_state *state,
> struct drm_property *property,
> - uint64_t *val)
> + u64 *val)
> {
> DRM_DEBUG_KMS("Unknown property [PROP:%d:%s]\n",
> property->base.id, property->name);
> @@ -334,7 +334,7 @@ int
> intel_plane_atomic_set_property(struct drm_plane *plane,
> struct drm_plane_state *state,
> struct drm_property *property,
> - uint64_t val)
> + u64 val)
> {
> DRM_DEBUG_KMS("Unknown property [PROP:%d:%s]\n",
> property->base.id, property->name);
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index a19699023db1..f90041cb336d 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -247,7 +247,7 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> int ret;
> - uint32_t temp;
> + u32 temp;
>
> /* MST encoders are bound to a crtc, not to a connector,
> * force the mapping here for get_hw_state.
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 3c7f10d17658..95cb8b154f87 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -413,7 +413,7 @@ static void _bxt_ddi_phy_init(struct
> drm_i915_private *dev_priv,
> }
>
> if (phy_info->rcomp_phy != -1) {
> - uint32_t grc_code;
> + u32 grc_code;
>
> bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
>
> @@ -445,7 +445,7 @@ static void _bxt_ddi_phy_init(struct
> drm_i915_private *dev_priv,
> void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum
> dpio_phy phy)
> {
> const struct bxt_ddi_phy_info *phy_info;
> - uint32_t val;
> + u32 val;
>
> phy_info = bxt_get_phy_info(dev_priv, phy);
>
> @@ -515,7 +515,7 @@ bool bxt_ddi_phy_verify_state(struct
> drm_i915_private *dev_priv,
> enum dpio_phy phy)
> {
> const struct bxt_ddi_phy_info *phy_info;
> - uint32_t mask;
> + u32 mask;
> bool ok;
>
> phy_info = bxt_get_phy_info(dev_priv, phy);
> @@ -567,8 +567,8 @@ bool bxt_ddi_phy_verify_state(struct
> drm_i915_private *dev_priv,
> #undef _CHK
> }
>
> -uint8_t
> -bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count)
> +u8
> +bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
> {
> switch (lane_count) {
> case 1:
> @@ -585,7 +585,7 @@ bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t
> lane_count)
> }
>
> void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
> - uint8_t lane_lat_optim_mask)
> + u8 lane_lat_optim_mask)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> @@ -610,7 +610,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct
> intel_encoder *encoder,
> }
> }
>
> -uint8_t
> +u8
> bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -618,7 +618,7 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct
> intel_encoder *encoder)
> enum dpio_phy phy;
> enum dpio_channel ch;
> int lane;
> - uint8_t mask;
> + u8 mask;
>
> bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
>
> @@ -739,7 +739,7 @@ void chv_data_lane_soft_reset(struct
> intel_encoder *encoder,
> enum dpio_channel ch =
> vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> enum pipe pipe = crtc->pipe;
> - uint32_t val;
> + u32 val;
>
> val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> if (reset)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bf4dae2649ab..59216dd8bfa1 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -799,15 +799,15 @@ u32 intel_calculate_mcr_s_ss_select(struct
> drm_i915_private *dev_priv)
> return mcr_s_ss_select;
> }
>
> -static inline uint32_t
> +static inline u32
> read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> int subslice, i915_reg_t reg)
> {
> - uint32_t mcr_slice_subslice_mask;
> - uint32_t mcr_slice_subslice_select;
> - uint32_t default_mcr_s_ss_select;
> - uint32_t mcr;
> - uint32_t ret;
> + u32 mcr_slice_subslice_mask;
> + u32 mcr_slice_subslice_select;
> + u32 default_mcr_s_ss_select;
> + u32 mcr;
> + u32 ret;
> enum forcewake_domains fw_domains;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index ccd5e110a19c..ec72be4b7a7b 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -594,7 +594,7 @@ static bool stride_is_valid(struct
> drm_i915_private *dev_priv,
> }
>
> static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
> - uint32_t pixel_format)
> + u32 pixel_format)
> {
> switch (pixel_format) {
> case DRM_FORMAT_XRGB8888:
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 9b39975c8389..3b9285130ef5 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -127,8 +127,8 @@ static void
> ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
> enum pipe pipe, bool
> enable)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
> - DE_PIPEB_FIFO_UNDERRUN;
> + u32 bit = (pipe == PIPE_A) ?
> + DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
>
> if (enable)
> ilk_enable_display_irq(dev_priv, bit);
> @@ -140,7 +140,7 @@ static void ivybridge_check_fifo_underruns(struct
> intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> - uint32_t err_int = I915_READ(GEN7_ERR_INT);
> + u32 err_int = I915_READ(GEN7_ERR_INT);
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -193,8 +193,8 @@ static void
> ibx_set_fifo_underrun_reporting(struct drm_device *dev,
> bool enable)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - uint32_t bit = (pch_transcoder == PIPE_A) ?
> - SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
> + u32 bit = (pch_transcoder == PIPE_A) ?
> + SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
>
> if (enable)
> ibx_enable_display_interrupt(dev_priv, bit);
> @@ -206,7 +206,7 @@ static void cpt_check_pch_fifo_underruns(struct
> intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pch_transcoder = crtc->pipe;
> - uint32_t serr_int = I915_READ(SERR_INT);
> + u32 serr_int = I915_READ(SERR_INT);
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
> b/drivers/gpu/drm/i915/intel_hdcp.c
> index 3fcb3b775948..ce7ba3a9c000 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -838,8 +838,8 @@ void intel_hdcp_atomic_check(struct drm_connector
> *connector,
> struct drm_connector_state *old_state,
> struct drm_connector_state *new_state)
> {
> - uint64_t old_cp = old_state->content_protection;
> - uint64_t new_cp = new_state->content_protection;
> + u64 old_cp = old_state->content_protection;
> + u64 new_cp = new_state->content_protection;
> struct drm_crtc_state *crtc_state;
>
> if (!new_state->crtc) {
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 608458b92db3..1d4bebcd4c8b 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2608,7 +2608,7 @@ static int
> execlists_context_deferred_alloc(struct i915_gem_context *ctx,
> {
> struct drm_i915_gem_object *ctx_obj;
> struct i915_vma *vma;
> - uint32_t context_size;
> + u32 context_size;
> struct intel_ring *ring;
> struct i915_timeline *timeline;
> int ret;
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index 56d614b02302..a8554dc4f196 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -44,7 +44,7 @@ static const char * const pipe_crc_sources[] = {
> };
>
> static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
> - uint32_t *val)
> + u32 *val)
> {
> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> *source = INTEL_PIPE_CRC_SOURCE_PIPE;
> @@ -120,7 +120,7 @@ static int i9xx_pipe_crc_auto_source(struct
> drm_i915_private *dev_priv,
> static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> enum intel_pipe_crc_source *source,
> - uint32_t *val)
> + u32 *val)
> {
> bool need_stable_symbols = false;
>
> @@ -165,7 +165,7 @@ static int vlv_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> * - DisplayPort scrambling: used for EMI reduction
> */
> if (need_stable_symbols) {
> - uint32_t tmp = I915_READ(PORT_DFT2_G4X);
> + u32 tmp = I915_READ(PORT_DFT2_G4X);
>
> tmp |= DC_BALANCE_RESET_VLV;
> switch (pipe) {
> @@ -190,7 +190,7 @@ static int vlv_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> enum intel_pipe_crc_source *source,
> - uint32_t *val)
> + u32 *val)
> {
> bool need_stable_symbols = false;
>
> @@ -244,7 +244,7 @@ static int i9xx_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> * - DisplayPort scrambling: used for EMI reduction
> */
> if (need_stable_symbols) {
> - uint32_t tmp = I915_READ(PORT_DFT2_G4X);
> + u32 tmp = I915_READ(PORT_DFT2_G4X);
>
> WARN_ON(!IS_G4X(dev_priv));
>
> @@ -265,7 +265,7 @@ static int i9xx_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> static void vlv_undo_pipe_scramble_reset(struct drm_i915_private
> *dev_priv,
> enum pipe pipe)
> {
> - uint32_t tmp = I915_READ(PORT_DFT2_G4X);
> + u32 tmp = I915_READ(PORT_DFT2_G4X);
>
> switch (pipe) {
> case PIPE_A:
> @@ -289,7 +289,7 @@ static void vlv_undo_pipe_scramble_reset(struct
> drm_i915_private *dev_priv,
> static void g4x_undo_pipe_scramble_reset(struct drm_i915_private
> *dev_priv,
> enum pipe pipe)
> {
> - uint32_t tmp = I915_READ(PORT_DFT2_G4X);
> + u32 tmp = I915_READ(PORT_DFT2_G4X);
>
> if (pipe == PIPE_A)
> tmp &= ~PIPE_A_SCRAMBLE_RESET;
> @@ -304,7 +304,7 @@ static void g4x_undo_pipe_scramble_reset(struct
> drm_i915_private *dev_priv,
> }
>
> static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
> - uint32_t *val)
> + u32 *val)
> {
> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> *source = INTEL_PIPE_CRC_SOURCE_PIPE;
> @@ -392,7 +392,7 @@ static void hsw_pipe_A_crc_wa(struct
> drm_i915_private *dev_priv,
> static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> enum intel_pipe_crc_source *source,
> - uint32_t *val,
> + u32 *val,
> bool set_wa)
> {
> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 0f6b2b4702e3..8dbf26c212cc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -230,7 +230,7 @@ void intel_psr_irq_handler(struct
> drm_i915_private *dev_priv, u32 psr_iir)
>
> static bool intel_dp_get_colorimetry_status(struct intel_dp
> *intel_dp)
> {
> - uint8_t dprx = 0;
> + u8 dprx = 0;
>
> if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_DPRX_FEATURE_ENUMERATION_LIST,
> &dprx) != 1)
> @@ -240,7 +240,7 @@ static bool
> intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>
> static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
> {
> - uint8_t alpm_caps = 0;
> + u8 alpm_caps = 0;
>
> if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
> &alpm_caps) != 1)
> @@ -384,7 +384,7 @@ static void hsw_psr_setup_aux(struct intel_dp
> *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u32 aux_clock_divider, aux_ctl;
> int i;
> - static const uint8_t aux_msg[] = {
> + static const u8 aux_msg[] = {
> [0] = DP_AUX_NATIVE_WRITE << 4,
> [1] = DP_SET_POWER >> 8,
> [2] = DP_SET_POWER & 0xff,
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 3c1366c58cf3..616f6bbb18ad 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -28,7 +28,7 @@ struct i915_sched_attr;
> * workarounds!
> */
> #define CACHELINE_BYTES 64
> -#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
> +#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
>
> struct intel_hw_status_page {
> struct i915_vma *vma;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 79f00610860b..a017a4232c0f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -903,10 +903,10 @@ void gen9_sanitize_dc_state(struct
> drm_i915_private *dev_priv)
> * back on and register state is restored. This is guaranteed by the
> MMIO write
> * to DC_STATE_EN blocking until the state is restored.
> */
> -static void gen9_set_dc_state(struct drm_i915_private *dev_priv,
> uint32_t state)
> +static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32
> state)
> {
> - uint32_t val;
> - uint32_t mask;
> + u32 val;
> + u32 mask;
>
> if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
> state &= dev_priv->csr.allowed_dc_mask;
> @@ -1538,7 +1538,7 @@ static void
> chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> {
> enum dpio_phy phy;
> enum pipe pipe;
> - uint32_t tmp;
> + u32 tmp;
>
> WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
> power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
> @@ -3328,10 +3328,10 @@ sanitize_disable_power_well_option(const
> struct drm_i915_private *dev_priv,
> return 1;
> }
>
> -static uint32_t get_allowed_dc_mask(const struct drm_i915_private
> *dev_priv,
> - int enable_dc)
> +static u32 get_allowed_dc_mask(const struct drm_i915_private
> *dev_priv,
> + int enable_dc)
> {
> - uint32_t mask;
> + u32 mask;
> int requested_dc;
> int max_dc;
>
> @@ -3596,7 +3596,7 @@ static void icl_dbuf_disable(struct
> drm_i915_private *dev_priv)
>
> static void icl_mbus_init(struct drm_i915_private *dev_priv)
> {
> - uint32_t val;
> + u32 val;
>
> val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
> MBUS_ABOX_BT_CREDIT_POOL2(16) |
> @@ -3907,7 +3907,7 @@ static void chv_phy_control_init(struct
> drm_i915_private *dev_priv)
> * current lane status.
> */
> if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
> - uint32_t status = I915_READ(DPLL(PIPE_A));
> + u32 status = I915_READ(DPLL(PIPE_A));
> unsigned int mask;
>
> mask = status & DPLL_PORTB_READY_MASK;
> @@ -3938,7 +3938,7 @@ static void chv_phy_control_init(struct
> drm_i915_private *dev_priv)
> }
>
> if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
> - uint32_t status = I915_READ(DPIO_PHY_STATUS);
> + u32 status = I915_READ(DPIO_PHY_STATUS);
> unsigned int mask;
>
> mask = status & DPLL_PORTD_READY_MASK;
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 02/17] drm/i915/crt: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
2019-01-16 9:15 ` [PATCH 01/17] drm/i915: small isolated c99 types to kernel types switch Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:19 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 03/17] drm/i915/sdvo: " Jani Nikula
` (20 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_crt.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 081c333f30d2..c2e799a5e63e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -631,19 +631,19 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
}
static enum drm_connector_status
-intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
+intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
{
struct drm_device *dev = crt->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- uint32_t save_bclrpat;
- uint32_t save_vtotal;
- uint32_t vtotal, vactive;
- uint32_t vsample;
- uint32_t vblank, vblank_start, vblank_end;
- uint32_t dsl;
+ u32 save_bclrpat;
+ u32 save_vtotal;
+ u32 vtotal, vactive;
+ u32 vsample;
+ u32 vblank, vblank_start, vblank_end;
+ u32 dsl;
i915_reg_t bclrpat_reg, vtotal_reg,
vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
- uint8_t st00;
+ u8 st00;
enum drm_connector_status status;
DRM_DEBUG_KMS("starting load-detect on CRT\n");
@@ -669,7 +669,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
I915_WRITE(bclrpat_reg, 0x500050);
if (!IS_GEN(dev_priv, 2)) {
- uint32_t pipeconf = I915_READ(pipeconf_reg);
+ u32 pipeconf = I915_READ(pipeconf_reg);
I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
POSTING_READ(pipeconf_reg);
/* Wait for next Vblank to substitue
@@ -690,8 +690,8 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
* Yes, this will flicker
*/
if (vblank_start <= vactive && vblank_end >= vtotal) {
- uint32_t vsync = I915_READ(vsync_reg);
- uint32_t vsync_start = (vsync & 0xffff) + 1;
+ u32 vsync = I915_READ(vsync_reg);
+ u32 vsync_start = (vsync & 0xffff) + 1;
vblank_start = vsync_start;
I915_WRITE(vblank_reg,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 02/17] drm/i915/crt: switch to kernel types
2019-01-16 9:15 ` [PATCH 02/17] drm/i915/crt: switch to kernel types Jani Nikula
@ 2019-01-17 0:19 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:19 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 2424 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel
> types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_crt.c | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 081c333f30d2..c2e799a5e63e 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -631,19 +631,19 @@ static bool intel_crt_detect_ddc(struct
> drm_connector *connector)
> }
>
> static enum drm_connector_status
> -intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
> +intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
> {
> struct drm_device *dev = crt->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - uint32_t save_bclrpat;
> - uint32_t save_vtotal;
> - uint32_t vtotal, vactive;
> - uint32_t vsample;
> - uint32_t vblank, vblank_start, vblank_end;
> - uint32_t dsl;
> + u32 save_bclrpat;
> + u32 save_vtotal;
> + u32 vtotal, vactive;
> + u32 vsample;
> + u32 vblank, vblank_start, vblank_end;
> + u32 dsl;
> i915_reg_t bclrpat_reg, vtotal_reg,
> vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
> - uint8_t st00;
> + u8 st00;
> enum drm_connector_status status;
>
> DRM_DEBUG_KMS("starting load-detect on CRT\n");
> @@ -669,7 +669,7 @@ intel_crt_load_detect(struct intel_crt *crt,
> uint32_t pipe)
> I915_WRITE(bclrpat_reg, 0x500050);
>
> if (!IS_GEN(dev_priv, 2)) {
> - uint32_t pipeconf = I915_READ(pipeconf_reg);
> + u32 pipeconf = I915_READ(pipeconf_reg);
> I915_WRITE(pipeconf_reg, pipeconf |
> PIPECONF_FORCE_BORDER);
> POSTING_READ(pipeconf_reg);
> /* Wait for next Vblank to substitue
> @@ -690,8 +690,8 @@ intel_crt_load_detect(struct intel_crt *crt,
> uint32_t pipe)
> * Yes, this will flicker
> */
> if (vblank_start <= vactive && vblank_end >= vtotal) {
> - uint32_t vsync = I915_READ(vsync_reg);
> - uint32_t vsync_start = (vsync & 0xffff) + 1;
> + u32 vsync = I915_READ(vsync_reg);
> + u32 vsync_start = (vsync & 0xffff) + 1;
>
> vblank_start = vsync_start;
> I915_WRITE(vblank_reg,
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 03/17] drm/i915/sdvo: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
2019-01-16 9:15 ` [PATCH 01/17] drm/i915: small isolated c99 types to kernel types switch Jani Nikula
2019-01-16 9:15 ` [PATCH 02/17] drm/i915/crt: switch to kernel types Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:21 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 04/17] drm/i915/lspcon: " Jani Nikula
` (19 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_sdvo.c | 78 +++++++++++++++----------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index df2d830a7405..e7b0884ba5a5 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -76,7 +76,7 @@ struct intel_sdvo {
i915_reg_t sdvo_reg;
/* Active outputs controlled by this SDVO output */
- uint16_t controlled_output;
+ u16 controlled_output;
/*
* Capabilities of the SDVO device returned by
@@ -91,12 +91,12 @@ struct intel_sdvo {
* For multiple function SDVO device,
* this is for current attached outputs.
*/
- uint16_t attached_output;
+ u16 attached_output;
/*
* Hotplug activation bits for this device
*/
- uint16_t hotplug_active;
+ u16 hotplug_active;
enum port port;
@@ -104,19 +104,19 @@ struct intel_sdvo {
bool has_hdmi_audio;
/* DDC bus used by this SDVO encoder */
- uint8_t ddc_bus;
+ u8 ddc_bus;
/*
* the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
*/
- uint8_t dtd_sdvo_flags;
+ u8 dtd_sdvo_flags;
};
struct intel_sdvo_connector {
struct intel_connector base;
/* Mark the type of connector */
- uint16_t output_flag;
+ u16 output_flag;
/* This contains all current supported TV format */
u8 tv_format_supported[TV_FORMAT_NUM];
@@ -184,7 +184,7 @@ to_intel_sdvo_connector(struct drm_connector *connector)
container_of((conn_state), struct intel_sdvo_connector_state, base.base)
static bool
-intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
+intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags);
static bool
intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
struct intel_sdvo_connector *intel_sdvo_connector,
@@ -746,9 +746,9 @@ static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
static bool
intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
struct intel_sdvo_connector *intel_sdvo_connector,
- uint16_t clock,
- uint16_t width,
- uint16_t height)
+ u16 clock,
+ u16 width,
+ u16 height)
{
struct intel_sdvo_preferred_input_timing_args args;
@@ -791,9 +791,9 @@ static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val
static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
const struct drm_display_mode *mode)
{
- uint16_t width, height;
- uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
- uint16_t h_sync_offset, v_sync_offset;
+ u16 width, height;
+ u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
+ u16 h_sync_offset, v_sync_offset;
int mode_clock;
memset(dtd, 0, sizeof(*dtd));
@@ -898,13 +898,13 @@ static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
}
static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
- uint8_t mode)
+ u8 mode)
{
return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
}
static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
- uint8_t mode)
+ u8 mode)
{
return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
}
@@ -913,11 +913,11 @@ static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
{
int i, j;
- uint8_t set_buf_index[2];
- uint8_t av_split;
- uint8_t buf_size;
- uint8_t buf[48];
- uint8_t *pos;
+ u8 set_buf_index[2];
+ u8 av_split;
+ u8 buf_size;
+ u8 buf[48];
+ u8 *pos;
intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
@@ -940,11 +940,11 @@ static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
#endif
static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
- unsigned if_index, uint8_t tx_rate,
- const uint8_t *data, unsigned length)
+ unsigned int if_index, u8 tx_rate,
+ const u8 *data, unsigned int length)
{
- uint8_t set_buf_index[2] = { if_index, 0 };
- uint8_t hbuf_size, tmp[8];
+ u8 set_buf_index[2] = { if_index, 0 };
+ u8 hbuf_size, tmp[8];
int i;
if (!intel_sdvo_set_value(intel_sdvo,
@@ -984,7 +984,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
{
const struct drm_display_mode *adjusted_mode =
&pipe_config->base.adjusted_mode;
- uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
+ u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
union hdmi_infoframe frame;
int ret;
ssize_t len;
@@ -1017,7 +1017,7 @@ static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
const struct drm_connector_state *conn_state)
{
struct intel_sdvo_tv_format format;
- uint32_t format_map;
+ u32 format_map;
format_map = 1 << conn_state->tv.mode;
memset(&format, 0, sizeof(format));
@@ -1208,7 +1208,7 @@ static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
const struct drm_connector_state *conn_state = &sdvo_state->base.base;
struct intel_sdvo_connector *intel_sdvo_conn =
to_intel_sdvo_connector(conn_state->connector);
- uint16_t val;
+ u16 val;
if (intel_sdvo_conn->left)
UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
@@ -1692,10 +1692,10 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in
return true;
}
-static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
+static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
{
struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
- uint16_t hotplug;
+ u16 hotplug;
if (!I915_HAS_HOTPLUG(dev_priv))
return 0;
@@ -1826,7 +1826,7 @@ intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
static enum drm_connector_status
intel_sdvo_detect(struct drm_connector *connector, bool force)
{
- uint16_t response;
+ u16 response;
struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
enum drm_connector_status ret;
@@ -1977,7 +1977,7 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
const struct drm_connector_state *conn_state = connector->state;
struct intel_sdvo_sdtv_resolution_request tv_res;
- uint32_t reply = 0, format_map = 0;
+ u32 reply = 0, format_map = 0;
int i;
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
@@ -2062,7 +2062,7 @@ static int
intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
const struct drm_connector_state *state,
struct drm_property *property,
- uint64_t *val)
+ u64 *val)
{
struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
@@ -2121,7 +2121,7 @@ static int
intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
struct drm_connector_state *state,
struct drm_property *property,
- uint64_t val)
+ u64 val)
{
struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
@@ -2270,7 +2270,7 @@ static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
static void
intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
{
- uint16_t mask = 0;
+ u16 mask = 0;
unsigned int num_bits;
/*
@@ -2671,7 +2671,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
}
static bool
-intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
+intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags)
{
/* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
@@ -2747,7 +2747,7 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
{
struct drm_device *dev = intel_sdvo->base.base.dev;
struct intel_sdvo_tv_format format;
- uint32_t format_map, i;
+ u32 format_map, i;
if (!intel_sdvo_set_target_output(intel_sdvo, type))
return false;
@@ -2814,7 +2814,7 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
struct drm_connector_state *conn_state = connector->state;
struct intel_sdvo_connector_state *sdvo_state =
to_intel_sdvo_connector_state(conn_state);
- uint16_t response, data_value[2];
+ u16 response, data_value[2];
/* when horizontal overscan is supported, Add the left/right property */
if (enhancements.overscan_h) {
@@ -2925,7 +2925,7 @@ intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
{
struct drm_device *dev = intel_sdvo->base.base.dev;
struct drm_connector *connector = &intel_sdvo_connector->base.base;
- uint16_t response, data_value[2];
+ u16 response, data_value[2];
ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
@@ -2939,7 +2939,7 @@ static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
{
union {
struct intel_sdvo_enhancements_reply reply;
- uint16_t response;
+ u16 response;
} enhancements;
BUILD_BUG_ON(sizeof(enhancements) != 2);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 03/17] drm/i915/sdvo: switch to kernel types
2019-01-16 9:15 ` [PATCH 03/17] drm/i915/sdvo: " Jani Nikula
@ 2019-01-17 0:21 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:21 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 10519 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel
> types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_sdvo.c | 78 +++++++++++++++------------
> ----
> 1 file changed, 39 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
> b/drivers/gpu/drm/i915/intel_sdvo.c
> index df2d830a7405..e7b0884ba5a5 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -76,7 +76,7 @@ struct intel_sdvo {
> i915_reg_t sdvo_reg;
>
> /* Active outputs controlled by this SDVO output */
> - uint16_t controlled_output;
> + u16 controlled_output;
>
> /*
> * Capabilities of the SDVO device returned by
> @@ -91,12 +91,12 @@ struct intel_sdvo {
> * For multiple function SDVO device,
> * this is for current attached outputs.
> */
> - uint16_t attached_output;
> + u16 attached_output;
>
> /*
> * Hotplug activation bits for this device
> */
> - uint16_t hotplug_active;
> + u16 hotplug_active;
>
> enum port port;
>
> @@ -104,19 +104,19 @@ struct intel_sdvo {
> bool has_hdmi_audio;
>
> /* DDC bus used by this SDVO encoder */
> - uint8_t ddc_bus;
> + u8 ddc_bus;
>
> /*
> * the sdvo flag gets lost in round trip: dtd->adjusted_mode-
> >dtd
> */
> - uint8_t dtd_sdvo_flags;
> + u8 dtd_sdvo_flags;
> };
>
> struct intel_sdvo_connector {
> struct intel_connector base;
>
> /* Mark the type of connector */
> - uint16_t output_flag;
> + u16 output_flag;
>
> /* This contains all current supported TV format */
> u8 tv_format_supported[TV_FORMAT_NUM];
> @@ -184,7 +184,7 @@ to_intel_sdvo_connector(struct drm_connector
> *connector)
> container_of((conn_state), struct intel_sdvo_connector_state,
> base.base)
>
> static bool
> -intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t
> flags);
> +intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags);
> static bool
> intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
> struct intel_sdvo_connector
> *intel_sdvo_connector,
> @@ -746,9 +746,9 @@ static bool intel_sdvo_get_input_timing(struct
> intel_sdvo *intel_sdvo,
> static bool
> intel_sdvo_create_preferred_input_timing(struct intel_sdvo
> *intel_sdvo,
> struct intel_sdvo_connector
> *intel_sdvo_connector,
> - uint16_t clock,
> - uint16_t width,
> - uint16_t height)
> + u16 clock,
> + u16 width,
> + u16 height)
> {
> struct intel_sdvo_preferred_input_timing_args args;
>
> @@ -791,9 +791,9 @@ static bool intel_sdvo_set_clock_rate_mult(struct
> intel_sdvo *intel_sdvo, u8 val
> static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
> const struct drm_display_mode
> *mode)
> {
> - uint16_t width, height;
> - uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
> - uint16_t h_sync_offset, v_sync_offset;
> + u16 width, height;
> + u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
> + u16 h_sync_offset, v_sync_offset;
> int mode_clock;
>
> memset(dtd, 0, sizeof(*dtd));
> @@ -898,13 +898,13 @@ static bool intel_sdvo_check_supp_encode(struct
> intel_sdvo *intel_sdvo)
> }
>
> static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
> - uint8_t mode)
> + u8 mode)
> {
> return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE,
> &mode, 1);
> }
>
> static bool intel_sdvo_set_colorimetry(struct intel_sdvo
> *intel_sdvo,
> - uint8_t mode)
> + u8 mode)
> {
> return intel_sdvo_set_value(intel_sdvo,
> SDVO_CMD_SET_COLORIMETRY, &mode, 1);
> }
> @@ -913,11 +913,11 @@ static bool intel_sdvo_set_colorimetry(struct
> intel_sdvo *intel_sdvo,
> static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
> {
> int i, j;
> - uint8_t set_buf_index[2];
> - uint8_t av_split;
> - uint8_t buf_size;
> - uint8_t buf[48];
> - uint8_t *pos;
> + u8 set_buf_index[2];
> + u8 av_split;
> + u8 buf_size;
> + u8 buf[48];
> + u8 *pos;
>
> intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT,
> &av_split, 1);
>
> @@ -940,11 +940,11 @@ static void intel_sdvo_dump_hdmi_buf(struct
> intel_sdvo *intel_sdvo)
> #endif
>
> static bool intel_sdvo_write_infoframe(struct intel_sdvo
> *intel_sdvo,
> - unsigned if_index, uint8_t
> tx_rate,
> - const uint8_t *data, unsigned
> length)
> + unsigned int if_index, u8
> tx_rate,
> + const u8 *data, unsigned int
> length)
> {
> - uint8_t set_buf_index[2] = { if_index, 0 };
> - uint8_t hbuf_size, tmp[8];
> + u8 set_buf_index[2] = { if_index, 0 };
> + u8 hbuf_size, tmp[8];
> int i;
>
> if (!intel_sdvo_set_value(intel_sdvo,
> @@ -984,7 +984,7 @@ static bool intel_sdvo_set_avi_infoframe(struct
> intel_sdvo *intel_sdvo,
> {
> const struct drm_display_mode *adjusted_mode =
> &pipe_config->base.adjusted_mode;
> - uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
> + u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
> union hdmi_infoframe frame;
> int ret;
> ssize_t len;
> @@ -1017,7 +1017,7 @@ static bool intel_sdvo_set_tv_format(struct
> intel_sdvo *intel_sdvo,
> const struct drm_connector_state
> *conn_state)
> {
> struct intel_sdvo_tv_format format;
> - uint32_t format_map;
> + u32 format_map;
>
> format_map = 1 << conn_state->tv.mode;
> memset(&format, 0, sizeof(format));
> @@ -1208,7 +1208,7 @@ static void intel_sdvo_update_props(struct
> intel_sdvo *intel_sdvo,
> const struct drm_connector_state *conn_state = &sdvo_state-
> >base.base;
> struct intel_sdvo_connector *intel_sdvo_conn =
> to_intel_sdvo_connector(conn_state->connector);
> - uint16_t val;
> + u16 val;
>
> if (intel_sdvo_conn->left)
> UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
> @@ -1692,10 +1692,10 @@ static bool
> intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in
> return true;
> }
>
> -static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo
> *intel_sdvo)
> +static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo
> *intel_sdvo)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_sdvo-
> >base.base.dev);
> - uint16_t hotplug;
> + u16 hotplug;
>
> if (!I915_HAS_HOTPLUG(dev_priv))
> return 0;
> @@ -1826,7 +1826,7 @@ intel_sdvo_connector_matches_edid(struct
> intel_sdvo_connector *sdvo,
> static enum drm_connector_status
> intel_sdvo_detect(struct drm_connector *connector, bool force)
> {
> - uint16_t response;
> + u16 response;
> struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
> struct intel_sdvo_connector *intel_sdvo_connector =
> to_intel_sdvo_connector(connector);
> enum drm_connector_status ret;
> @@ -1977,7 +1977,7 @@ static void intel_sdvo_get_tv_modes(struct
> drm_connector *connector)
> struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
> const struct drm_connector_state *conn_state = connector-
> >state;
> struct intel_sdvo_sdtv_resolution_request tv_res;
> - uint32_t reply = 0, format_map = 0;
> + u32 reply = 0, format_map = 0;
> int i;
>
> DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> @@ -2062,7 +2062,7 @@ static int
> intel_sdvo_connector_atomic_get_property(struct drm_connector
> *connector,
> const struct
> drm_connector_state *state,
> struct drm_property *property,
> - uint64_t *val)
> + u64 *val)
> {
> struct intel_sdvo_connector *intel_sdvo_connector =
> to_intel_sdvo_connector(connector);
> const struct intel_sdvo_connector_state *sdvo_state =
> to_intel_sdvo_connector_state((void *)state);
> @@ -2121,7 +2121,7 @@ static int
> intel_sdvo_connector_atomic_set_property(struct drm_connector
> *connector,
> struct drm_connector_state
> *state,
> struct drm_property *property,
> - uint64_t val)
> + u64 val)
> {
> struct intel_sdvo_connector *intel_sdvo_connector =
> to_intel_sdvo_connector(connector);
> struct intel_sdvo_connector_state *sdvo_state =
> to_intel_sdvo_connector_state(state);
> @@ -2270,7 +2270,7 @@ static const struct drm_encoder_funcs
> intel_sdvo_enc_funcs = {
> static void
> intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
> {
> - uint16_t mask = 0;
> + u16 mask = 0;
> unsigned int num_bits;
>
> /*
> @@ -2671,7 +2671,7 @@ intel_sdvo_lvds_init(struct intel_sdvo
> *intel_sdvo, int device)
> }
>
> static bool
> -intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t
> flags)
> +intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags)
> {
> /* SDVO requires XXX1 function may not exist unless it has XXX0
> function.*/
>
> @@ -2747,7 +2747,7 @@ static bool
> intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
> {
> struct drm_device *dev = intel_sdvo->base.base.dev;
> struct intel_sdvo_tv_format format;
> - uint32_t format_map, i;
> + u32 format_map, i;
>
> if (!intel_sdvo_set_target_output(intel_sdvo, type))
> return false;
> @@ -2814,7 +2814,7 @@ intel_sdvo_create_enhance_property_tv(struct
> intel_sdvo *intel_sdvo,
> struct drm_connector_state *conn_state = connector->state;
> struct intel_sdvo_connector_state *sdvo_state =
> to_intel_sdvo_connector_state(conn_state);
> - uint16_t response, data_value[2];
> + u16 response, data_value[2];
>
> /* when horizontal overscan is supported, Add the left/right
> property */
> if (enhancements.overscan_h) {
> @@ -2925,7 +2925,7 @@ intel_sdvo_create_enhance_property_lvds(struct
> intel_sdvo *intel_sdvo,
> {
> struct drm_device *dev = intel_sdvo->base.base.dev;
> struct drm_connector *connector = &intel_sdvo_connector-
> >base.base;
> - uint16_t response, data_value[2];
> + u16 response, data_value[2];
>
> ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
>
> @@ -2939,7 +2939,7 @@ static bool
> intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
> {
> union {
> struct intel_sdvo_enhancements_reply reply;
> - uint16_t response;
> + u16 response;
> } enhancements;
>
> BUILD_BUG_ON(sizeof(enhancements) != 2);
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 04/17] drm/i915/lspcon: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (2 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 03/17] drm/i915/sdvo: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:28 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 05/17] drm/i915/debugfs: " Jani Nikula
` (18 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_lspcon.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c b/drivers/gpu/drm/i915/intel_lspcon.c
index 7d15be5932e0..322bdddda164 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -288,12 +288,12 @@ static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
}
static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
- uint8_t *avi_buf)
+ u8 *avi_buf)
{
u8 avi_if_ctrl;
u8 block_count = 0;
u8 *data;
- uint16_t reg;
+ u16 reg;
ssize_t ret;
while (block_count < 4) {
@@ -335,10 +335,10 @@ static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
}
static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
- const uint8_t *frame,
+ const u8 *frame,
ssize_t len)
{
- uint8_t avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
+ u8 avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
/*
* Parade's frames contains 32 bytes of data, divided
@@ -367,13 +367,13 @@ static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
}
static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux,
- const uint8_t *buffer, ssize_t len)
+ const u8 *buffer, ssize_t len)
{
int ret;
- uint32_t val = 0;
- uint32_t retry;
- uint16_t reg;
- const uint8_t *data = buffer;
+ u32 val = 0;
+ u32 retry;
+ u16 reg;
+ const u8 *data = buffer;
reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET;
while (val < len) {
@@ -459,7 +459,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
{
ssize_t ret;
union hdmi_infoframe frame;
- uint8_t buf[VIDEO_DIP_DATA_SIZE];
+ u8 buf[VIDEO_DIP_DATA_SIZE];
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
struct intel_lspcon *lspcon = &dig_port->lspcon;
const struct drm_display_mode *adjusted_mode =
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 04/17] drm/i915/lspcon: switch to kernel types
2019-01-16 9:15 ` [PATCH 04/17] drm/i915/lspcon: " Jani Nikula
@ 2019-01-17 0:28 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:28 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 2485 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel
> types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lspcon.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lspcon.c
> b/drivers/gpu/drm/i915/intel_lspcon.c
> index 7d15be5932e0..322bdddda164 100644
> --- a/drivers/gpu/drm/i915/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/intel_lspcon.c
> @@ -288,12 +288,12 @@ static bool lspcon_parade_fw_ready(struct
> drm_dp_aux *aux)
> }
>
> static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux
> *aux,
> - uint8_t *avi_buf)
> + u8 *avi_buf)
> {
> u8 avi_if_ctrl;
> u8 block_count = 0;
> u8 *data;
> - uint16_t reg;
> + u16 reg;
> ssize_t ret;
>
> while (block_count < 4) {
> @@ -335,10 +335,10 @@ static bool
> _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
> }
>
> static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux
> *aux,
> - const uint8_t *frame,
> + const u8 *frame,
> ssize_t len)
> {
> - uint8_t avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
> + u8 avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
>
> /*
> * Parade's frames contains 32 bytes of data, divided
> @@ -367,13 +367,13 @@ static bool
> _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
> }
>
> static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux,
> - const uint8_t *buffer,
> ssize_t len)
> + const u8 *buffer, ssize_t
> len)
> {
> int ret;
> - uint32_t val = 0;
> - uint32_t retry;
> - uint16_t reg;
> - const uint8_t *data = buffer;
> + u32 val = 0;
> + u32 retry;
> + u16 reg;
> + const u8 *data = buffer;
>
> reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET;
> while (val < len) {
> @@ -459,7 +459,7 @@ void lspcon_set_infoframes(struct intel_encoder
> *encoder,
> {
> ssize_t ret;
> union hdmi_infoframe frame;
> - uint8_t buf[VIDEO_DIP_DATA_SIZE];
> + u8 buf[VIDEO_DIP_DATA_SIZE];
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> struct intel_lspcon *lspcon = &dig_port->lspcon;
> const struct drm_display_mode *adjusted_mode =
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 05/17] drm/i915/debugfs: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (3 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 04/17] drm/i915/lspcon: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:29 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 06/17] drm/i915/irq: " Jani Nikula
` (17 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8d738e6ca7b5..fc78e45778b5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2249,7 +2249,7 @@ static void i915_guc_client_info(struct seq_file *m,
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
- uint64_t tot = 0;
+ u64 tot = 0;
seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
client->priority, client->stage_id, client->proc_desc_offset);
@@ -3637,7 +3637,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
-static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
+static void wm_latency_show(struct seq_file *m, const u16 wm[8])
{
struct drm_i915_private *dev_priv = m->private;
struct drm_device *dev = &dev_priv->drm;
@@ -3680,7 +3680,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
static int pri_wm_latency_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
- const uint16_t *latencies;
+ const u16 *latencies;
if (INTEL_GEN(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
@@ -3695,7 +3695,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data)
static int spr_wm_latency_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
- const uint16_t *latencies;
+ const u16 *latencies;
if (INTEL_GEN(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
@@ -3710,7 +3710,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data)
static int cur_wm_latency_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
- const uint16_t *latencies;
+ const u16 *latencies;
if (INTEL_GEN(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
@@ -3753,12 +3753,12 @@ static int cur_wm_latency_open(struct inode *inode, struct file *file)
}
static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
- size_t len, loff_t *offp, uint16_t wm[8])
+ size_t len, loff_t *offp, u16 wm[8])
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
struct drm_device *dev = &dev_priv->drm;
- uint16_t new[8] = { 0 };
+ u16 new[8] = { 0 };
int num_levels;
int level;
int ret;
@@ -3803,7 +3803,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- uint16_t *latencies;
+ u16 *latencies;
if (INTEL_GEN(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
@@ -3818,7 +3818,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- uint16_t *latencies;
+ u16 *latencies;
if (INTEL_GEN(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
@@ -3833,7 +3833,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- uint16_t *latencies;
+ u16 *latencies;
if (INTEL_GEN(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
@@ -4851,7 +4851,7 @@ static int i915_dpcd_show(struct seq_file *m, void *data)
struct drm_connector *connector = m->private;
struct intel_dp *intel_dp =
enc_to_intel_dp(&intel_attached_encoder(connector)->base);
- uint8_t buf[16];
+ u8 buf[16];
ssize_t err;
int i;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 05/17] drm/i915/debugfs: switch to kernel types
2019-01-16 9:15 ` [PATCH 05/17] drm/i915/debugfs: " Jani Nikula
@ 2019-01-17 0:29 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:29 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 4416 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel
> types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8d738e6ca7b5..fc78e45778b5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2249,7 +2249,7 @@ static void i915_guc_client_info(struct
> seq_file *m,
> {
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> - uint64_t tot = 0;
> + u64 tot = 0;
>
> seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset
> 0x%x\n",
> client->priority, client->stage_id, client-
> >proc_desc_offset);
> @@ -3637,7 +3637,7 @@ static int
> i915_displayport_test_type_show(struct seq_file *m, void *data)
> }
> DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
>
> -static void wm_latency_show(struct seq_file *m, const uint16_t
> wm[8])
> +static void wm_latency_show(struct seq_file *m, const u16 wm[8])
> {
> struct drm_i915_private *dev_priv = m->private;
> struct drm_device *dev = &dev_priv->drm;
> @@ -3680,7 +3680,7 @@ static void wm_latency_show(struct seq_file *m,
> const uint16_t wm[8])
> static int pri_wm_latency_show(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = m->private;
> - const uint16_t *latencies;
> + const u16 *latencies;
>
> if (INTEL_GEN(dev_priv) >= 9)
> latencies = dev_priv->wm.skl_latency;
> @@ -3695,7 +3695,7 @@ static int pri_wm_latency_show(struct seq_file
> *m, void *data)
> static int spr_wm_latency_show(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = m->private;
> - const uint16_t *latencies;
> + const u16 *latencies;
>
> if (INTEL_GEN(dev_priv) >= 9)
> latencies = dev_priv->wm.skl_latency;
> @@ -3710,7 +3710,7 @@ static int spr_wm_latency_show(struct seq_file
> *m, void *data)
> static int cur_wm_latency_show(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = m->private;
> - const uint16_t *latencies;
> + const u16 *latencies;
>
> if (INTEL_GEN(dev_priv) >= 9)
> latencies = dev_priv->wm.skl_latency;
> @@ -3753,12 +3753,12 @@ static int cur_wm_latency_open(struct inode
> *inode, struct file *file)
> }
>
> static ssize_t wm_latency_write(struct file *file, const char __user
> *ubuf,
> - size_t len, loff_t *offp, uint16_t
> wm[8])
> + size_t len, loff_t *offp, u16 wm[8])
> {
> struct seq_file *m = file->private_data;
> struct drm_i915_private *dev_priv = m->private;
> struct drm_device *dev = &dev_priv->drm;
> - uint16_t new[8] = { 0 };
> + u16 new[8] = { 0 };
> int num_levels;
> int level;
> int ret;
> @@ -3803,7 +3803,7 @@ static ssize_t pri_wm_latency_write(struct file
> *file, const char __user *ubuf,
> {
> struct seq_file *m = file->private_data;
> struct drm_i915_private *dev_priv = m->private;
> - uint16_t *latencies;
> + u16 *latencies;
>
> if (INTEL_GEN(dev_priv) >= 9)
> latencies = dev_priv->wm.skl_latency;
> @@ -3818,7 +3818,7 @@ static ssize_t spr_wm_latency_write(struct file
> *file, const char __user *ubuf,
> {
> struct seq_file *m = file->private_data;
> struct drm_i915_private *dev_priv = m->private;
> - uint16_t *latencies;
> + u16 *latencies;
>
> if (INTEL_GEN(dev_priv) >= 9)
> latencies = dev_priv->wm.skl_latency;
> @@ -3833,7 +3833,7 @@ static ssize_t cur_wm_latency_write(struct file
> *file, const char __user *ubuf,
> {
> struct seq_file *m = file->private_data;
> struct drm_i915_private *dev_priv = m->private;
> - uint16_t *latencies;
> + u16 *latencies;
>
> if (INTEL_GEN(dev_priv) >= 9)
> latencies = dev_priv->wm.skl_latency;
> @@ -4851,7 +4851,7 @@ static int i915_dpcd_show(struct seq_file *m,
> void *data)
> struct drm_connector *connector = m->private;
> struct intel_dp *intel_dp =
> enc_to_intel_dp(&intel_attached_encoder(connector)-
> >base);
> - uint8_t buf[16];
> + u8 buf[16];
> ssize_t err;
> int i;
>
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 06/17] drm/i915/irq: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (4 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 05/17] drm/i915/debugfs: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-16 9:19 ` Chris Wilson
2019-01-17 0:32 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 07/17] drm/i915/cdclk: " Jani Nikula
` (16 subsequent siblings)
22 siblings, 2 replies; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 82 ++++++++++++++++-----------------
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 94187e68d39a..29bbafb5b040 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -223,10 +223,10 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
/* For display hotplug interrupt */
static inline void
i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
- uint32_t mask,
- uint32_t bits)
+ u32 mask,
+ u32 bits)
{
- uint32_t val;
+ u32 val;
lockdep_assert_held(&dev_priv->irq_lock);
WARN_ON(bits & ~mask);
@@ -250,8 +250,8 @@ i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
* version is also available.
*/
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
- uint32_t mask,
- uint32_t bits)
+ u32 mask,
+ u32 bits)
{
spin_lock_irq(&dev_priv->irq_lock);
i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
@@ -300,10 +300,10 @@ static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
* @enabled_irq_mask: mask of interrupt bits to enable
*/
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask)
+ u32 interrupt_mask,
+ u32 enabled_irq_mask)
{
- uint32_t new_val;
+ u32 new_val;
lockdep_assert_held(&dev_priv->irq_lock);
@@ -330,8 +330,8 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv,
* @enabled_irq_mask: mask of interrupt bits to enable
*/
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask)
+ u32 interrupt_mask,
+ u32 enabled_irq_mask)
{
lockdep_assert_held(&dev_priv->irq_lock);
@@ -345,13 +345,13 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
}
-void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
{
ilk_update_gt_irq(dev_priv, mask, mask);
POSTING_READ_FW(GTIMR);
}
-void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
{
ilk_update_gt_irq(dev_priv, mask, 0);
}
@@ -390,10 +390,10 @@ static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
* @enabled_irq_mask: mask of interrupt bits to enable
*/
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask)
+ u32 interrupt_mask,
+ u32 enabled_irq_mask)
{
- uint32_t new_val;
+ u32 new_val;
WARN_ON(enabled_irq_mask & ~interrupt_mask);
@@ -577,11 +577,11 @@ void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
* @enabled_irq_mask: mask of interrupt bits to enable
*/
static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask)
+ u32 interrupt_mask,
+ u32 enabled_irq_mask)
{
- uint32_t new_val;
- uint32_t old_val;
+ u32 new_val;
+ u32 old_val;
lockdep_assert_held(&dev_priv->irq_lock);
@@ -611,10 +611,10 @@ static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
*/
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
enum pipe pipe,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask)
+ u32 interrupt_mask,
+ u32 enabled_irq_mask)
{
- uint32_t new_val;
+ u32 new_val;
lockdep_assert_held(&dev_priv->irq_lock);
@@ -641,10 +641,10 @@ void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
* @enabled_irq_mask: mask of interrupt bits to enable
*/
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask)
+ u32 interrupt_mask,
+ u32 enabled_irq_mask)
{
- uint32_t sdeimr = I915_READ(SDEIMR);
+ u32 sdeimr = I915_READ(SDEIMR);
sdeimr &= ~interrupt_mask;
sdeimr |= (~enabled_irq_mask & interrupt_mask);
@@ -1368,8 +1368,8 @@ static void ivybridge_parity_work(struct work_struct *work)
container_of(work, typeof(*dev_priv), l3_parity.error_work);
u32 error_status, row, bank, subbank;
char *parity_event[6];
- uint32_t misccpctl;
- uint8_t slice = 0;
+ u32 misccpctl;
+ u8 slice = 0;
/* We must turn off DOP level clock gating to access the L3 registers.
* In order to prevent a get/put style interface, acquire struct mutex
@@ -1730,13 +1730,13 @@ static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
#if defined(CONFIG_DEBUG_FS)
static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe,
- uint32_t crc0, uint32_t crc1,
- uint32_t crc2, uint32_t crc3,
- uint32_t crc4)
+ u32 crc0, u32 crc1,
+ u32 crc2, u32 crc3,
+ u32 crc4)
{
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- uint32_t crcs[5];
+ u32 crcs[5];
spin_lock(&pipe_crc->lock);
/*
@@ -1768,9 +1768,9 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
static inline void
display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe,
- uint32_t crc0, uint32_t crc1,
- uint32_t crc2, uint32_t crc3,
- uint32_t crc4) {}
+ u32 crc0, u32 crc1,
+ u32 crc2, u32 crc3,
+ u32 crc4) {}
#endif
@@ -1796,7 +1796,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- uint32_t res1, res2;
+ u32 res1, res2;
if (INTEL_GEN(dev_priv) >= 3)
res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
@@ -3410,7 +3410,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
- uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
+ u32 bit = INTEL_GEN(dev_priv) >= 7 ?
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -3472,7 +3472,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
- uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
+ u32 bit = INTEL_GEN(dev_priv) >= 7 ?
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -3690,7 +3690,7 @@ static void gen11_irq_reset(struct drm_device *dev)
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
- uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
+ u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
spin_lock_irq(&dev_priv->irq_lock);
@@ -4159,7 +4159,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
/* These are interrupts we'll toggle with the ring mask register */
- uint32_t gt_interrupts[] = {
+ u32 gt_interrupts[] = {
GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
@@ -4187,8 +4187,8 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
- uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
- uint32_t de_pipe_enables;
+ u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
+ u32 de_pipe_enables;
u32 de_port_masked = GEN8_AUX_CHANNEL_A;
u32 de_port_enables;
u32 de_misc_masked = GEN8_DE_EDP_PSR;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 06/17] drm/i915/irq: switch to kernel types
2019-01-16 9:15 ` [PATCH 06/17] drm/i915/irq: " Jani Nikula
@ 2019-01-16 9:19 ` Chris Wilson
2019-01-17 0:32 ` Souza, Jose
1 sibling, 0 replies; 46+ messages in thread
From: Chris Wilson @ 2019-01-16 9:19 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Quoting Jani Nikula (2019-01-16 09:15:24)
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 06/17] drm/i915/irq: switch to kernel types
2019-01-16 9:15 ` [PATCH 06/17] drm/i915/irq: " Jani Nikula
2019-01-16 9:19 ` Chris Wilson
@ 2019-01-17 0:32 ` Souza, Jose
1 sibling, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:32 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 9108 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel
> types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 82 ++++++++++++++++---------------
> --
> 1 file changed, 41 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 94187e68d39a..29bbafb5b040 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -223,10 +223,10 @@ static void gen9_guc_irq_handler(struct
> drm_i915_private *dev_priv, u32 pm_iir);
> /* For display hotplug interrupt */
> static inline void
> i915_hotplug_interrupt_update_locked(struct drm_i915_private
> *dev_priv,
> - uint32_t mask,
> - uint32_t bits)
> + u32 mask,
> + u32 bits)
> {
> - uint32_t val;
> + u32 val;
>
> lockdep_assert_held(&dev_priv->irq_lock);
> WARN_ON(bits & ~mask);
> @@ -250,8 +250,8 @@ i915_hotplug_interrupt_update_locked(struct
> drm_i915_private *dev_priv,
> * version is also available.
> */
> void i915_hotplug_interrupt_update(struct drm_i915_private
> *dev_priv,
> - uint32_t mask,
> - uint32_t bits)
> + u32 mask,
> + u32 bits)
> {
> spin_lock_irq(&dev_priv->irq_lock);
> i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
> @@ -300,10 +300,10 @@ static bool gen11_reset_one_iir(struct
> drm_i915_private * const i915,
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> void ilk_update_display_irq(struct drm_i915_private *dev_priv,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask)
> + u32 interrupt_mask,
> + u32 enabled_irq_mask)
> {
> - uint32_t new_val;
> + u32 new_val;
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -330,8 +330,8 @@ void ilk_update_display_irq(struct
> drm_i915_private *dev_priv,
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask)
> + u32 interrupt_mask,
> + u32 enabled_irq_mask)
> {
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -345,13 +345,13 @@ static void ilk_update_gt_irq(struct
> drm_i915_private *dev_priv,
> I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> }
>
> -void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t
> mask)
> +void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
> {
> ilk_update_gt_irq(dev_priv, mask, mask);
> POSTING_READ_FW(GTIMR);
> }
>
> -void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t
> mask)
> +void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32
> mask)
> {
> ilk_update_gt_irq(dev_priv, mask, 0);
> }
> @@ -390,10 +390,10 @@ static i915_reg_t gen6_pm_ier(struct
> drm_i915_private *dev_priv)
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask)
> + u32 interrupt_mask,
> + u32 enabled_irq_mask)
> {
> - uint32_t new_val;
> + u32 new_val;
>
> WARN_ON(enabled_irq_mask & ~interrupt_mask);
>
> @@ -577,11 +577,11 @@ void gen9_disable_guc_interrupts(struct
> drm_i915_private *dev_priv)
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask)
> + u32 interrupt_mask,
> + u32 enabled_irq_mask)
> {
> - uint32_t new_val;
> - uint32_t old_val;
> + u32 new_val;
> + u32 old_val;
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -611,10 +611,10 @@ static void bdw_update_port_irq(struct
> drm_i915_private *dev_priv,
> */
> void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask)
> + u32 interrupt_mask,
> + u32 enabled_irq_mask)
> {
> - uint32_t new_val;
> + u32 new_val;
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -641,10 +641,10 @@ void bdw_update_pipe_irq(struct
> drm_i915_private *dev_priv,
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask)
> + u32 interrupt_mask,
> + u32 enabled_irq_mask)
> {
> - uint32_t sdeimr = I915_READ(SDEIMR);
> + u32 sdeimr = I915_READ(SDEIMR);
> sdeimr &= ~interrupt_mask;
> sdeimr |= (~enabled_irq_mask & interrupt_mask);
>
> @@ -1368,8 +1368,8 @@ static void ivybridge_parity_work(struct
> work_struct *work)
> container_of(work, typeof(*dev_priv),
> l3_parity.error_work);
> u32 error_status, row, bank, subbank;
> char *parity_event[6];
> - uint32_t misccpctl;
> - uint8_t slice = 0;
> + u32 misccpctl;
> + u8 slice = 0;
>
> /* We must turn off DOP level clock gating to access the L3
> registers.
> * In order to prevent a get/put style interface, acquire
> struct mutex
> @@ -1730,13 +1730,13 @@ static void dp_aux_irq_handler(struct
> drm_i915_private *dev_priv)
> #if defined(CONFIG_DEBUG_FS)
> static void display_pipe_crc_irq_handler(struct drm_i915_private
> *dev_priv,
> enum pipe pipe,
> - uint32_t crc0, uint32_t crc1,
> - uint32_t crc2, uint32_t crc3,
> - uint32_t crc4)
> + u32 crc0, u32 crc1,
> + u32 crc2, u32 crc3,
> + u32 crc4)
> {
> struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
> struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> pipe);
> - uint32_t crcs[5];
> + u32 crcs[5];
>
> spin_lock(&pipe_crc->lock);
> /*
> @@ -1768,9 +1768,9 @@ static void display_pipe_crc_irq_handler(struct
> drm_i915_private *dev_priv,
> static inline void
> display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> - uint32_t crc0, uint32_t crc1,
> - uint32_t crc2, uint32_t crc3,
> - uint32_t crc4) {}
> + u32 crc0, u32 crc1,
> + u32 crc2, u32 crc3,
> + u32 crc4) {}
> #endif
>
>
> @@ -1796,7 +1796,7 @@ static void ivb_pipe_crc_irq_handler(struct
> drm_i915_private *dev_priv,
> static void i9xx_pipe_crc_irq_handler(struct drm_i915_private
> *dev_priv,
> enum pipe pipe)
> {
> - uint32_t res1, res2;
> + u32 res1, res2;
>
> if (INTEL_GEN(dev_priv) >= 3)
> res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
> @@ -3410,7 +3410,7 @@ static int ironlake_enable_vblank(struct
> drm_device *dev, unsigned int pipe)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> unsigned long irqflags;
> - uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
> + u32 bit = INTEL_GEN(dev_priv) >= 7 ?
> DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> @@ -3472,7 +3472,7 @@ static void ironlake_disable_vblank(struct
> drm_device *dev, unsigned int pipe)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> unsigned long irqflags;
> - uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
> + u32 bit = INTEL_GEN(dev_priv) >= 7 ?
> DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> @@ -3690,7 +3690,7 @@ static void gen11_irq_reset(struct drm_device
> *dev)
> void gen8_irq_power_well_post_enable(struct drm_i915_private
> *dev_priv,
> u8 pipe_mask)
> {
> - uint32_t extra_ier = GEN8_PIPE_VBLANK |
> GEN8_PIPE_FIFO_UNDERRUN;
> + u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
> enum pipe pipe;
>
> spin_lock_irq(&dev_priv->irq_lock);
> @@ -4159,7 +4159,7 @@ static int valleyview_irq_postinstall(struct
> drm_device *dev)
> static void gen8_gt_irq_postinstall(struct drm_i915_private
> *dev_priv)
> {
> /* These are interrupts we'll toggle with the ring mask
> register */
> - uint32_t gt_interrupts[] = {
> + u32 gt_interrupts[] = {
> GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> GT_CONTEXT_SWITCH_INTERRUPT <<
> GEN8_RCS_IRQ_SHIFT |
> GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT
> |
> @@ -4187,8 +4187,8 @@ static void gen8_gt_irq_postinstall(struct
> drm_i915_private *dev_priv)
>
> static void gen8_de_irq_postinstall(struct drm_i915_private
> *dev_priv)
> {
> - uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
> - uint32_t de_pipe_enables;
> + u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
> + u32 de_pipe_enables;
> u32 de_port_masked = GEN8_AUX_CHANNEL_A;
> u32 de_port_enables;
> u32 de_misc_masked = GEN8_DE_EDP_PSR;
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 07/17] drm/i915/cdclk: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (5 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 06/17] drm/i915/irq: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:34 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 08/17] drm/i915/dpll_mgr: " Jani Nikula
` (15 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 40 +++++++++++++++---------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 73cb7250118e..15ba950dee00 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -218,7 +218,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
};
const unsigned int *vco_table;
unsigned int vco;
- uint8_t tmp = 0;
+ u8 tmp = 0;
/* FIXME other chipsets? */
if (IS_GM45(dev_priv))
@@ -249,13 +249,13 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
- static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
- static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
- static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
- static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
- const uint8_t *div_table;
+ static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
+ static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
+ static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
+ static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
+ const u8 *div_table;
unsigned int cdclk_sel;
- uint16_t tmp = 0;
+ u16 tmp = 0;
cdclk_state->vco = intel_hpll_vco(dev_priv);
@@ -330,12 +330,12 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
- static const uint8_t div_3200[] = { 16, 10, 8 };
- static const uint8_t div_4000[] = { 20, 12, 10 };
- static const uint8_t div_5333[] = { 24, 16, 14 };
- const uint8_t *div_table;
+ static const u8 div_3200[] = { 16, 10, 8 };
+ static const u8 div_4000[] = { 20, 12, 10 };
+ static const u8 div_5333[] = { 24, 16, 14 };
+ const u8 *div_table;
unsigned int cdclk_sel;
- uint16_t tmp = 0;
+ u16 tmp = 0;
cdclk_state->vco = intel_hpll_vco(dev_priv);
@@ -375,7 +375,7 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
{
struct pci_dev *pdev = dev_priv->drm.pdev;
unsigned int cdclk_sel;
- uint16_t tmp = 0;
+ u16 tmp = 0;
cdclk_state->vco = intel_hpll_vco(dev_priv);
@@ -403,8 +403,8 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
- uint32_t lcpll = I915_READ(LCPLL_CTL);
- uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
+ u32 lcpll = I915_READ(LCPLL_CTL);
+ u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
if (lcpll & LCPLL_CD_SOURCE_FCLK)
cdclk_state->cdclk = 800000;
@@ -672,8 +672,8 @@ static u8 bdw_calc_voltage_level(int cdclk)
static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
- uint32_t lcpll = I915_READ(LCPLL_CTL);
- uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
+ u32 lcpll = I915_READ(LCPLL_CTL);
+ u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
if (lcpll & LCPLL_CD_SOURCE_FCLK)
cdclk_state->cdclk = 800000;
@@ -700,7 +700,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state)
{
int cdclk = cdclk_state->cdclk;
- uint32_t val;
+ u32 val;
int ret;
if (WARN((I915_READ(LCPLL_CTL) &
@@ -1083,7 +1083,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
- uint32_t cdctl, expected;
+ u32 cdctl, expected;
/*
* check if the pre-os initialized the display
@@ -2690,7 +2690,7 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv)
static int g4x_hrawclk(struct drm_i915_private *dev_priv)
{
- uint32_t clkcfg;
+ u32 clkcfg;
/* hrawclock is 1/4 the FSB frequency */
clkcfg = I915_READ(CLKCFG);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 07/17] drm/i915/cdclk: switch to kernel types
2019-01-16 9:15 ` [PATCH 07/17] drm/i915/cdclk: " Jani Nikula
@ 2019-01-17 0:34 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:34 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 4550 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel
> types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 40 +++++++++++++++-------------
> --
> 1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 73cb7250118e..15ba950dee00 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -218,7 +218,7 @@ static unsigned int intel_hpll_vco(struct
> drm_i915_private *dev_priv)
> };
> const unsigned int *vco_table;
> unsigned int vco;
> - uint8_t tmp = 0;
> + u8 tmp = 0;
>
> /* FIXME other chipsets? */
> if (IS_GM45(dev_priv))
> @@ -249,13 +249,13 @@ static void g33_get_cdclk(struct
> drm_i915_private *dev_priv,
> struct intel_cdclk_state *cdclk_state)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> - static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
> - static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
> - static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
> - static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
> - const uint8_t *div_table;
> + static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
> + static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
> + static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
> + static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
> + const u8 *div_table;
> unsigned int cdclk_sel;
> - uint16_t tmp = 0;
> + u16 tmp = 0;
>
> cdclk_state->vco = intel_hpll_vco(dev_priv);
>
> @@ -330,12 +330,12 @@ static void i965gm_get_cdclk(struct
> drm_i915_private *dev_priv,
> struct intel_cdclk_state *cdclk_state)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> - static const uint8_t div_3200[] = { 16, 10, 8 };
> - static const uint8_t div_4000[] = { 20, 12, 10 };
> - static const uint8_t div_5333[] = { 24, 16, 14 };
> - const uint8_t *div_table;
> + static const u8 div_3200[] = { 16, 10, 8 };
> + static const u8 div_4000[] = { 20, 12, 10 };
> + static const u8 div_5333[] = { 24, 16, 14 };
> + const u8 *div_table;
> unsigned int cdclk_sel;
> - uint16_t tmp = 0;
> + u16 tmp = 0;
>
> cdclk_state->vco = intel_hpll_vco(dev_priv);
>
> @@ -375,7 +375,7 @@ static void gm45_get_cdclk(struct
> drm_i915_private *dev_priv,
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> unsigned int cdclk_sel;
> - uint16_t tmp = 0;
> + u16 tmp = 0;
>
> cdclk_state->vco = intel_hpll_vco(dev_priv);
>
> @@ -403,8 +403,8 @@ static void gm45_get_cdclk(struct
> drm_i915_private *dev_priv,
> static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_state *cdclk_state)
> {
> - uint32_t lcpll = I915_READ(LCPLL_CTL);
> - uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> + u32 lcpll = I915_READ(LCPLL_CTL);
> + u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
>
> if (lcpll & LCPLL_CD_SOURCE_FCLK)
> cdclk_state->cdclk = 800000;
> @@ -672,8 +672,8 @@ static u8 bdw_calc_voltage_level(int cdclk)
> static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_state *cdclk_state)
> {
> - uint32_t lcpll = I915_READ(LCPLL_CTL);
> - uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> + u32 lcpll = I915_READ(LCPLL_CTL);
> + u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
>
> if (lcpll & LCPLL_CD_SOURCE_FCLK)
> cdclk_state->cdclk = 800000;
> @@ -700,7 +700,7 @@ static void bdw_set_cdclk(struct drm_i915_private
> *dev_priv,
> const struct intel_cdclk_state *cdclk_state)
> {
> int cdclk = cdclk_state->cdclk;
> - uint32_t val;
> + u32 val;
> int ret;
>
> if (WARN((I915_READ(LCPLL_CTL) &
> @@ -1083,7 +1083,7 @@ static void skl_set_cdclk(struct
> drm_i915_private *dev_priv,
>
> static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> - uint32_t cdctl, expected;
> + u32 cdctl, expected;
>
> /*
> * check if the pre-os initialized the display
> @@ -2690,7 +2690,7 @@ static int vlv_hrawclk(struct drm_i915_private
> *dev_priv)
>
> static int g4x_hrawclk(struct drm_i915_private *dev_priv)
> {
> - uint32_t clkcfg;
> + u32 clkcfg;
>
> /* hrawclock is 1/4 the FSB frequency */
> clkcfg = I915_READ(CLKCFG);
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 08/17] drm/i915/dpll_mgr: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (6 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 07/17] drm/i915/cdclk: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:41 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 09/17] drm/i915/dp: " Jani Nikula
` (14 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Minor checkpatch/whitespace fixes sprinkled on top of the changed lines.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 145 +++++++++++++-------------
drivers/gpu/drm/i915/intel_dpll_mgr.h | 53 +++++-----
2 files changed, 99 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 04870e960537..606f54dde086 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -346,7 +346,7 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
- uint32_t val;
+ u32 val;
wakeref = intel_display_power_get_if_enabled(dev_priv,
POWER_DOMAIN_PLLS);
@@ -490,7 +490,7 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
- uint32_t val;
+ u32 val;
val = I915_READ(WRPLL_CTL(id));
I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
@@ -500,7 +500,7 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- uint32_t val;
+ u32 val;
val = I915_READ(SPLL_CTL);
I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
@@ -513,7 +513,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
- uint32_t val;
+ u32 val;
wakeref = intel_display_power_get_if_enabled(dev_priv,
POWER_DOMAIN_PLLS);
@@ -533,7 +533,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state)
{
intel_wakeref_t wakeref;
- uint32_t val;
+ u32 val;
wakeref = intel_display_power_get_if_enabled(dev_priv,
POWER_DOMAIN_PLLS);
@@ -639,11 +639,12 @@ static unsigned hsw_wrpll_get_budget_for_freq(int clock)
return budget;
}
-static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
- unsigned r2, unsigned n2, unsigned p,
+static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
+ unsigned int r2, unsigned int n2,
+ unsigned int p,
struct hsw_wrpll_rnp *best)
{
- uint64_t a, b, c, d, diff, diff_best;
+ u64 a, b, c, d, diff, diff_best;
/* No best (r,n,p) yet */
if (best->p == 0) {
@@ -702,7 +703,7 @@ static void
hsw_ddi_calculate_wrpll(int clock /* in Hz */,
unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
{
- uint64_t freq2k;
+ u64 freq2k;
unsigned p, n2, r2;
struct hsw_wrpll_rnp best = { 0, 0, 0 };
unsigned budget;
@@ -768,7 +769,7 @@ static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,
struct intel_crtc_state *crtc_state)
{
struct intel_shared_dpll *pll;
- uint32_t val;
+ u32 val;
unsigned int p, n2, r2;
hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
@@ -930,7 +931,7 @@ static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
- uint32_t val;
+ u32 val;
val = I915_READ(DPLL_CTRL1);
@@ -995,7 +996,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- uint32_t val;
+ u32 val;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -1035,7 +1036,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
- uint32_t val;
+ u32 val;
bool ret;
wakeref = intel_display_power_get_if_enabled(dev_priv,
@@ -1062,9 +1063,9 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
}
struct skl_wrpll_context {
- uint64_t min_deviation; /* current minimal deviation */
- uint64_t central_freq; /* chosen central freq */
- uint64_t dco_freq; /* chosen dco freq */
+ u64 min_deviation; /* current minimal deviation */
+ u64 central_freq; /* chosen central freq */
+ u64 dco_freq; /* chosen dco freq */
unsigned int p; /* chosen divider */
};
@@ -1080,11 +1081,11 @@ static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
#define SKL_DCO_MAX_NDEVIATION 600
static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
- uint64_t central_freq,
- uint64_t dco_freq,
+ u64 central_freq,
+ u64 dco_freq,
unsigned int divider)
{
- uint64_t deviation;
+ u64 deviation;
deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
central_freq);
@@ -1158,21 +1159,21 @@ static void skl_wrpll_get_multipliers(unsigned int p,
}
struct skl_wrpll_params {
- uint32_t dco_fraction;
- uint32_t dco_integer;
- uint32_t qdiv_ratio;
- uint32_t qdiv_mode;
- uint32_t kdiv;
- uint32_t pdiv;
- uint32_t central_freq;
+ u32 dco_fraction;
+ u32 dco_integer;
+ u32 qdiv_ratio;
+ u32 qdiv_mode;
+ u32 kdiv;
+ u32 pdiv;
+ u32 central_freq;
};
static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
- uint64_t afe_clock,
- uint64_t central_freq,
- uint32_t p0, uint32_t p1, uint32_t p2)
+ u64 afe_clock,
+ u64 central_freq,
+ u32 p0, u32 p1, u32 p2)
{
- uint64_t dco_freq;
+ u64 dco_freq;
switch (central_freq) {
case 9600000000ULL:
@@ -1238,10 +1239,10 @@ static bool
skl_ddi_calculate_wrpll(int clock /* in Hz */,
struct skl_wrpll_params *wrpll_params)
{
- uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
- uint64_t dco_central_freq[3] = {8400000000ULL,
- 9000000000ULL,
- 9600000000ULL};
+ u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
+ u64 dco_central_freq[3] = { 8400000000ULL,
+ 9000000000ULL,
+ 9600000000ULL };
static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
24, 28, 30, 32, 36, 40, 42, 44,
48, 52, 54, 56, 60, 64, 66, 68,
@@ -1265,7 +1266,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
for (i = 0; i < dividers[d].n_dividers; i++) {
unsigned int p = dividers[d].list[i];
- uint64_t dco_freq = p * afe_clock;
+ u64 dco_freq = p * afe_clock;
skl_wrpll_try_divider(&ctx,
dco_central_freq[dco],
@@ -1311,7 +1312,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
int clock)
{
- uint32_t ctrl1, cfgcr1, cfgcr2;
+ u32 ctrl1, cfgcr1, cfgcr2;
struct skl_wrpll_params wrpll_params = { 0, };
/*
@@ -1348,7 +1349,7 @@ static bool
skl_ddi_dp_set_dpll_hw_state(int clock,
struct intel_dpll_hw_state *dpll_hw_state)
{
- uint32_t ctrl1;
+ u32 ctrl1;
/*
* See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1450,7 +1451,7 @@ static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- uint32_t temp;
+ u32 temp;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy;
enum dpio_channel ch;
@@ -1571,7 +1572,7 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
- uint32_t temp;
+ u32 temp;
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
temp &= ~PORT_PLL_ENABLE;
@@ -1597,7 +1598,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
intel_wakeref_t wakeref;
enum dpio_phy phy;
enum dpio_channel ch;
- uint32_t val;
+ u32 val;
bool ret;
bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
@@ -1669,12 +1670,12 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
/* bxt clock parameters */
struct bxt_clk_div {
int clock;
- uint32_t p1;
- uint32_t p2;
- uint32_t m2_int;
- uint32_t m2_frac;
+ u32 p1;
+ u32 p2;
+ u32 m2_int;
+ u32 m2_frac;
bool m2_frac_en;
- uint32_t n;
+ u32 n;
int vco;
};
@@ -1741,8 +1742,8 @@ static bool bxt_ddi_set_dpll_hw_state(int clock,
struct intel_dpll_hw_state *dpll_hw_state)
{
int vco = clk_div->vco;
- uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
- uint32_t lanestagger;
+ u32 prop_coef, int_coef, gain_ctl, targ_cnt;
+ u32 lanestagger;
if (vco >= 6200000 && vco <= 6700000) {
prop_coef = 4;
@@ -1891,7 +1892,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
if (INTEL_GEN(dev_priv) < 9) {
- uint32_t val = I915_READ(LCPLL_CTL);
+ u32 val = I915_READ(LCPLL_CTL);
/*
* The LCPLL register should be turned on by the BIOS. For now
@@ -1977,7 +1978,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
- uint32_t val;
+ u32 val;
/* 1. Enable DPLL power in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(id));
@@ -2052,7 +2053,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
- uint32_t val;
+ u32 val;
/*
* 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
@@ -2110,7 +2111,7 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
- uint32_t val;
+ u32 val;
bool ret;
wakeref = intel_display_power_get_if_enabled(dev_priv,
@@ -2246,7 +2247,7 @@ cnl_ddi_calculate_wrpll(int clock,
struct skl_wrpll_params *wrpll_params)
{
u32 afe_clock = clock * 5;
- uint32_t ref_clock;
+ u32 ref_clock;
u32 dco_min = 7998000;
u32 dco_max = 10000000;
u32 dco_mid = (dco_min + dco_max) / 2;
@@ -2292,7 +2293,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
int clock)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- uint32_t cfgcr0, cfgcr1;
+ u32 cfgcr0, cfgcr1;
struct skl_wrpll_params wrpll_params = { 0, };
cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
@@ -2321,7 +2322,7 @@ static bool
cnl_ddi_dp_set_dpll_hw_state(int clock,
struct intel_dpll_hw_state *dpll_hw_state)
{
- uint32_t cfgcr0;
+ u32 cfgcr0;
cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
@@ -2538,7 +2539,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct intel_dpll_hw_state *pll_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- uint32_t cfgcr0, cfgcr1;
+ u32 cfgcr0, cfgcr1;
struct skl_wrpll_params pll_params = { 0 };
bool ret;
@@ -2568,10 +2569,10 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
}
int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
- uint32_t pll_id)
+ u32 pll_id)
{
- uint32_t cfgcr0, cfgcr1;
- uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
+ u32 cfgcr0, cfgcr1;
+ u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
const struct skl_wrpll_params *params;
int index, n_entries, link_clock;
@@ -2654,10 +2655,10 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id)
}
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
- uint32_t *target_dco_khz,
+ u32 *target_dco_khz,
struct intel_dpll_hw_state *state)
{
- uint32_t dco_min_freq, dco_max_freq;
+ u32 dco_min_freq, dco_max_freq;
int div1_vals[] = {7, 5, 3, 2};
unsigned int i;
int div2;
@@ -2733,12 +2734,12 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int refclk_khz = dev_priv->cdclk.hw.ref;
- uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
- uint32_t iref_ndiv, iref_trim, iref_pulse_w;
- uint32_t prop_coeff, int_coeff;
- uint32_t tdc_targetcnt, feedfwgain;
- uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;
- uint64_t tmp;
+ u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
+ u32 iref_ndiv, iref_trim, iref_pulse_w;
+ u32 prop_coeff, int_coeff;
+ u32 tdc_targetcnt, feedfwgain;
+ u64 ssc_stepsize, ssc_steplen, ssc_steplog;
+ u64 tmp;
bool use_ssc = false;
bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
@@ -2761,7 +2762,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
}
m2div_rem = dco_khz % (refclk_khz * m1div);
- tmp = (uint64_t)m2div_rem * (1 << 22);
+ tmp = (u64)m2div_rem * (1 << 22);
do_div(tmp, refclk_khz * m1div);
m2div_frac = tmp;
@@ -2820,11 +2821,11 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
}
if (use_ssc) {
- tmp = (uint64_t)dco_khz * 47 * 32;
+ tmp = (u64)dco_khz * 47 * 32;
do_div(tmp, refclk_khz * m1div * 10000);
ssc_stepsize = tmp;
- tmp = (uint64_t)dco_khz * 1000;
+ tmp = (u64)dco_khz * 1000;
ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
} else {
ssc_stepsize = 0;
@@ -2974,7 +2975,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
intel_wakeref_t wakeref;
bool ret = false;
enum port port;
- uint32_t val;
+ u32 val;
wakeref = intel_display_power_get_if_enabled(dev_priv,
POWER_DOMAIN_PLLS);
@@ -3101,7 +3102,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
{
const enum intel_dpll_id id = pll->info->id;
i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
- uint32_t val;
+ u32 val;
val = I915_READ(enable_reg);
val |= PLL_POWER_ENABLE;
@@ -3142,7 +3143,7 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
{
const enum intel_dpll_id id = pll->info->id;
i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
- uint32_t val;
+ u32 val;
/* The first steps are done by intel_ddi_post_disable(). */
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index a033d8f06d4a..e96e79413b54 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -138,14 +138,14 @@ enum intel_dpll_id {
struct intel_dpll_hw_state {
/* i9xx, pch plls */
- uint32_t dpll;
- uint32_t dpll_md;
- uint32_t fp0;
- uint32_t fp1;
+ u32 dpll;
+ u32 dpll_md;
+ u32 fp0;
+ u32 fp1;
/* hsw, bdw */
- uint32_t wrpll;
- uint32_t spll;
+ u32 wrpll;
+ u32 spll;
/* skl */
/*
@@ -154,34 +154,33 @@ struct intel_dpll_hw_state {
* the register. This allows us to easily compare the state to share
* the DPLL.
*/
- uint32_t ctrl1;
+ u32 ctrl1;
/* HDMI only, 0 when used for DP */
- uint32_t cfgcr1, cfgcr2;
+ u32 cfgcr1, cfgcr2;
/* cnl */
- uint32_t cfgcr0;
+ u32 cfgcr0;
/* CNL also uses cfgcr1 */
/* bxt */
- uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
- pcsdw12;
+ u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
/*
* ICL uses the following, already defined:
- * uint32_t cfgcr0, cfgcr1;
- */
- uint32_t mg_refclkin_ctl;
- uint32_t mg_clktop2_coreclkctl1;
- uint32_t mg_clktop2_hsclkctl;
- uint32_t mg_pll_div0;
- uint32_t mg_pll_div1;
- uint32_t mg_pll_lf;
- uint32_t mg_pll_frac_lock;
- uint32_t mg_pll_ssc;
- uint32_t mg_pll_bias;
- uint32_t mg_pll_tdc_coldst_bias;
- uint32_t mg_pll_bias_mask;
- uint32_t mg_pll_tdc_coldst_bias_mask;
+ * u32 cfgcr0, cfgcr1;
+ */
+ u32 mg_refclkin_ctl;
+ u32 mg_clktop2_coreclkctl1;
+ u32 mg_clktop2_hsclkctl;
+ u32 mg_pll_div0;
+ u32 mg_pll_div1;
+ u32 mg_pll_lf;
+ u32 mg_pll_frac_lock;
+ u32 mg_pll_ssc;
+ u32 mg_pll_bias;
+ u32 mg_pll_tdc_coldst_bias;
+ u32 mg_pll_bias_mask;
+ u32 mg_pll_tdc_coldst_bias_mask;
};
/**
@@ -280,7 +279,7 @@ struct dpll_info {
* Inform the state checker that the DPLL is kept enabled even if
* not in use by any CRTC.
*/
- uint32_t flags;
+ u32 flags;
};
/**
@@ -343,7 +342,7 @@ void intel_shared_dpll_init(struct drm_device *dev);
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state);
int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
- uint32_t pll_id);
+ u32 pll_id);
int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 08/17] drm/i915/dpll_mgr: switch to kernel types
2019-01-16 9:15 ` [PATCH 08/17] drm/i915/dpll_mgr: " Jani Nikula
@ 2019-01-17 0:41 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:41 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 18766 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch/whitespace fixes sprinkled on top of the changed
> lines.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 145 +++++++++++++-----------
> --
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 53 +++++-----
> 2 files changed, 99 insertions(+), 99 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 04870e960537..606f54dde086 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -346,7 +346,7 @@ static bool ibx_pch_dpll_get_hw_state(struct
> drm_i915_private *dev_priv,
> {
> const enum intel_dpll_id id = pll->info->id;
> intel_wakeref_t wakeref;
> - uint32_t val;
> + u32 val;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> POWER_DOMAIN_PLLS)
> ;
> @@ -490,7 +490,7 @@ static void hsw_ddi_wrpll_disable(struct
> drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
> - uint32_t val;
> + u32 val;
>
> val = I915_READ(WRPLL_CTL(id));
> I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
> @@ -500,7 +500,7 @@ static void hsw_ddi_wrpll_disable(struct
> drm_i915_private *dev_priv,
> static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> - uint32_t val;
> + u32 val;
>
> val = I915_READ(SPLL_CTL);
> I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
> @@ -513,7 +513,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct
> drm_i915_private *dev_priv,
> {
> const enum intel_dpll_id id = pll->info->id;
> intel_wakeref_t wakeref;
> - uint32_t val;
> + u32 val;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> POWER_DOMAIN_PLLS)
> ;
> @@ -533,7 +533,7 @@ static bool hsw_ddi_spll_get_hw_state(struct
> drm_i915_private *dev_priv,
> struct intel_dpll_hw_state
> *hw_state)
> {
> intel_wakeref_t wakeref;
> - uint32_t val;
> + u32 val;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> POWER_DOMAIN_PLLS)
> ;
> @@ -639,11 +639,12 @@ static unsigned
> hsw_wrpll_get_budget_for_freq(int clock)
> return budget;
> }
>
> -static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
> - unsigned r2, unsigned n2, unsigned p,
> +static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
> + unsigned int r2, unsigned int n2,
> + unsigned int p,
> struct hsw_wrpll_rnp *best)
> {
> - uint64_t a, b, c, d, diff, diff_best;
> + u64 a, b, c, d, diff, diff_best;
>
> /* No best (r,n,p) yet */
> if (best->p == 0) {
> @@ -702,7 +703,7 @@ static void
> hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> unsigned *r2_out, unsigned *n2_out, unsigned
> *p_out)
> {
> - uint64_t freq2k;
> + u64 freq2k;
> unsigned p, n2, r2;
> struct hsw_wrpll_rnp best = { 0, 0, 0 };
> unsigned budget;
> @@ -768,7 +769,7 @@ static struct intel_shared_dpll
> *hsw_ddi_hdmi_get_dpll(int clock,
> struct
> intel_crtc_state *crtc_state)
> {
> struct intel_shared_dpll *pll;
> - uint32_t val;
> + u32 val;
> unsigned int p, n2, r2;
>
> hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
> @@ -930,7 +931,7 @@ static void skl_ddi_pll_write_ctrl1(struct
> drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
> - uint32_t val;
> + u32 val;
>
> val = I915_READ(DPLL_CTRL1);
>
> @@ -995,7 +996,7 @@ static bool skl_ddi_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll,
> struct intel_dpll_hw_state
> *hw_state)
> {
> - uint32_t val;
> + u32 val;
> const struct skl_dpll_regs *regs = skl_dpll_regs;
> const enum intel_dpll_id id = pll->info->id;
> intel_wakeref_t wakeref;
> @@ -1035,7 +1036,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct
> drm_i915_private *dev_priv,
> const struct skl_dpll_regs *regs = skl_dpll_regs;
> const enum intel_dpll_id id = pll->info->id;
> intel_wakeref_t wakeref;
> - uint32_t val;
> + u32 val;
> bool ret;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> @@ -1062,9 +1063,9 @@ static bool skl_ddi_dpll0_get_hw_state(struct
> drm_i915_private *dev_priv,
> }
>
> struct skl_wrpll_context {
> - uint64_t min_deviation; /* current minimal deviation
> */
> - uint64_t central_freq; /* chosen central freq */
> - uint64_t dco_freq; /* chosen dco freq */
> + u64 min_deviation; /* current minimal deviation
> */
> + u64 central_freq; /* chosen central freq */
> + u64 dco_freq; /* chosen dco freq */
> unsigned int p; /* chosen divider */
> };
>
> @@ -1080,11 +1081,11 @@ static void skl_wrpll_context_init(struct
> skl_wrpll_context *ctx)
> #define SKL_DCO_MAX_NDEVIATION 600
>
> static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
> - uint64_t central_freq,
> - uint64_t dco_freq,
> + u64 central_freq,
> + u64 dco_freq,
> unsigned int divider)
> {
> - uint64_t deviation;
> + u64 deviation;
>
> deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
> central_freq);
> @@ -1158,21 +1159,21 @@ static void
> skl_wrpll_get_multipliers(unsigned int p,
> }
>
> struct skl_wrpll_params {
> - uint32_t dco_fraction;
> - uint32_t dco_integer;
> - uint32_t qdiv_ratio;
> - uint32_t qdiv_mode;
> - uint32_t kdiv;
> - uint32_t pdiv;
> - uint32_t central_freq;
> + u32 dco_fraction;
> + u32 dco_integer;
> + u32 qdiv_ratio;
> + u32 qdiv_mode;
> + u32 kdiv;
> + u32 pdiv;
> + u32 central_freq;
> };
>
> static void skl_wrpll_params_populate(struct skl_wrpll_params
> *params,
> - uint64_t afe_clock,
> - uint64_t central_freq,
> - uint32_t p0, uint32_t p1,
> uint32_t p2)
> + u64 afe_clock,
> + u64 central_freq,
> + u32 p0, u32 p1, u32 p2)
> {
> - uint64_t dco_freq;
> + u64 dco_freq;
>
> switch (central_freq) {
> case 9600000000ULL:
> @@ -1238,10 +1239,10 @@ static bool
> skl_ddi_calculate_wrpll(int clock /* in Hz */,
> struct skl_wrpll_params *wrpll_params)
> {
> - uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock
> */
> - uint64_t dco_central_freq[3] = {8400000000ULL,
> - 9000000000ULL,
> - 9600000000ULL};
> + u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
> + u64 dco_central_freq[3] = { 8400000000ULL,
> + 9000000000ULL,
> + 9600000000ULL };
> static const int even_dividers[] = { 4, 6, 8, 10, 12, 14,
> 16, 18, 20,
> 24, 28, 30, 32, 36, 40,
> 42, 44,
> 48, 52, 54, 56, 60, 64,
> 66, 68,
> @@ -1265,7 +1266,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> for (dco = 0; dco < ARRAY_SIZE(dco_central_freq);
> dco++) {
> for (i = 0; i < dividers[d].n_dividers; i++) {
> unsigned int p = dividers[d].list[i];
> - uint64_t dco_freq = p * afe_clock;
> + u64 dco_freq = p * afe_clock;
>
> skl_wrpll_try_divider(&ctx,
> dco_central_freq[
> dco],
> @@ -1311,7 +1312,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct
> intel_crtc *crtc,
> struct intel_crtc_state
> *crtc_state,
> int clock)
> {
> - uint32_t ctrl1, cfgcr1, cfgcr2;
> + u32 ctrl1, cfgcr1, cfgcr2;
> struct skl_wrpll_params wrpll_params = { 0, };
>
> /*
> @@ -1348,7 +1349,7 @@ static bool
> skl_ddi_dp_set_dpll_hw_state(int clock,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> - uint32_t ctrl1;
> + u32 ctrl1;
>
> /*
> * See comment in intel_dpll_hw_state to understand why we
> always use 0
> @@ -1450,7 +1451,7 @@ static const struct intel_shared_dpll_funcs
> skl_ddi_dpll0_funcs = {
> static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> - uint32_t temp;
> + u32 temp;
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL
> mapping */
> enum dpio_phy phy;
> enum dpio_channel ch;
> @@ -1571,7 +1572,7 @@ static void bxt_ddi_pll_disable(struct
> drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL
> mapping */
> - uint32_t temp;
> + u32 temp;
>
> temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> temp &= ~PORT_PLL_ENABLE;
> @@ -1597,7 +1598,7 @@ static bool bxt_ddi_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> intel_wakeref_t wakeref;
> enum dpio_phy phy;
> enum dpio_channel ch;
> - uint32_t val;
> + u32 val;
> bool ret;
>
> bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
> @@ -1669,12 +1670,12 @@ static bool bxt_ddi_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> /* bxt clock parameters */
> struct bxt_clk_div {
> int clock;
> - uint32_t p1;
> - uint32_t p2;
> - uint32_t m2_int;
> - uint32_t m2_frac;
> + u32 p1;
> + u32 p2;
> + u32 m2_int;
> + u32 m2_frac;
> bool m2_frac_en;
> - uint32_t n;
> + u32 n;
>
> int vco;
> };
> @@ -1741,8 +1742,8 @@ static bool bxt_ddi_set_dpll_hw_state(int
> clock,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> int vco = clk_div->vco;
> - uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
> - uint32_t lanestagger;
> + u32 prop_coef, int_coef, gain_ctl, targ_cnt;
> + u32 lanestagger;
>
> if (vco >= 6200000 && vco <= 6700000) {
> prop_coef = 4;
> @@ -1891,7 +1892,7 @@ static void intel_ddi_pll_init(struct
> drm_device *dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> if (INTEL_GEN(dev_priv) < 9) {
> - uint32_t val = I915_READ(LCPLL_CTL);
> + u32 val = I915_READ(LCPLL_CTL);
>
> /*
> * The LCPLL register should be turned on by the BIOS.
> For now
> @@ -1977,7 +1978,7 @@ static void cnl_ddi_pll_enable(struct
> drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
> - uint32_t val;
> + u32 val;
>
> /* 1. Enable DPLL power in DPLL_ENABLE. */
> val = I915_READ(CNL_DPLL_ENABLE(id));
> @@ -2052,7 +2053,7 @@ static void cnl_ddi_pll_disable(struct
> drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
> - uint32_t val;
> + u32 val;
>
> /*
> * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the
> DDI.
> @@ -2110,7 +2111,7 @@ static bool cnl_ddi_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> {
> const enum intel_dpll_id id = pll->info->id;
> intel_wakeref_t wakeref;
> - uint32_t val;
> + u32 val;
> bool ret;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> @@ -2246,7 +2247,7 @@ cnl_ddi_calculate_wrpll(int clock,
> struct skl_wrpll_params *wrpll_params)
> {
> u32 afe_clock = clock * 5;
> - uint32_t ref_clock;
> + u32 ref_clock;
> u32 dco_min = 7998000;
> u32 dco_max = 10000000;
> u32 dco_mid = (dco_min + dco_max) / 2;
> @@ -2292,7 +2293,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
> intel_crtc *crtc,
> int clock)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - uint32_t cfgcr0, cfgcr1;
> + u32 cfgcr0, cfgcr1;
> struct skl_wrpll_params wrpll_params = { 0, };
>
> cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
> @@ -2321,7 +2322,7 @@ static bool
> cnl_ddi_dp_set_dpll_hw_state(int clock,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> - uint32_t cfgcr0;
> + u32 cfgcr0;
>
> cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
>
> @@ -2538,7 +2539,7 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
> struct intel_dpll_hw_state *pll_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - uint32_t cfgcr0, cfgcr1;
> + u32 cfgcr0, cfgcr1;
> struct skl_wrpll_params pll_params = { 0 };
> bool ret;
>
> @@ -2568,10 +2569,10 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
> }
>
> int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> - uint32_t pll_id)
> + u32 pll_id)
> {
> - uint32_t cfgcr0, cfgcr1;
> - uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> dco_fraction;
> + u32 cfgcr0, cfgcr1;
> + u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> dco_fraction;
> const struct skl_wrpll_params *params;
> int index, n_entries, link_clock;
>
> @@ -2654,10 +2655,10 @@ bool intel_dpll_is_combophy(enum
> intel_dpll_id id)
> }
>
> static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool
> use_ssc,
> - uint32_t *target_dco_khz,
> + u32 *target_dco_khz,
> struct intel_dpll_hw_state *state)
> {
> - uint32_t dco_min_freq, dco_max_freq;
> + u32 dco_min_freq, dco_max_freq;
> int div1_vals[] = {7, 5, 3, 2};
> unsigned int i;
> int div2;
> @@ -2733,12 +2734,12 @@ static bool icl_calc_mg_pll_state(struct
> intel_crtc_state *crtc_state,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> int refclk_khz = dev_priv->cdclk.hw.ref;
> - uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> - uint32_t iref_ndiv, iref_trim, iref_pulse_w;
> - uint32_t prop_coeff, int_coeff;
> - uint32_t tdc_targetcnt, feedfwgain;
> - uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;
> - uint64_t tmp;
> + u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> + u32 iref_ndiv, iref_trim, iref_pulse_w;
> + u32 prop_coeff, int_coeff;
> + u32 tdc_targetcnt, feedfwgain;
> + u64 ssc_stepsize, ssc_steplen, ssc_steplog;
> + u64 tmp;
> bool use_ssc = false;
> bool is_dp = !intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_HDMI);
>
> @@ -2761,7 +2762,7 @@ static bool icl_calc_mg_pll_state(struct
> intel_crtc_state *crtc_state,
> }
> m2div_rem = dco_khz % (refclk_khz * m1div);
>
> - tmp = (uint64_t)m2div_rem * (1 << 22);
> + tmp = (u64)m2div_rem * (1 << 22);
> do_div(tmp, refclk_khz * m1div);
> m2div_frac = tmp;
>
> @@ -2820,11 +2821,11 @@ static bool icl_calc_mg_pll_state(struct
> intel_crtc_state *crtc_state,
> }
>
> if (use_ssc) {
> - tmp = (uint64_t)dco_khz * 47 * 32;
> + tmp = (u64)dco_khz * 47 * 32;
> do_div(tmp, refclk_khz * m1div * 10000);
> ssc_stepsize = tmp;
>
> - tmp = (uint64_t)dco_khz * 1000;
> + tmp = (u64)dco_khz * 1000;
> ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
> } else {
> ssc_stepsize = 0;
> @@ -2974,7 +2975,7 @@ static bool icl_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> intel_wakeref_t wakeref;
> bool ret = false;
> enum port port;
> - uint32_t val;
> + u32 val;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> POWER_DOMAIN_PLLS)
> ;
> @@ -3101,7 +3102,7 @@ static void icl_pll_enable(struct
> drm_i915_private *dev_priv,
> {
> const enum intel_dpll_id id = pll->info->id;
> i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
> - uint32_t val;
> + u32 val;
>
> val = I915_READ(enable_reg);
> val |= PLL_POWER_ENABLE;
> @@ -3142,7 +3143,7 @@ static void icl_pll_disable(struct
> drm_i915_private *dev_priv,
> {
> const enum intel_dpll_id id = pll->info->id;
> i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
> - uint32_t val;
> + u32 val;
>
> /* The first steps are done by intel_ddi_post_disable(). */
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index a033d8f06d4a..e96e79413b54 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -138,14 +138,14 @@ enum intel_dpll_id {
>
> struct intel_dpll_hw_state {
> /* i9xx, pch plls */
> - uint32_t dpll;
> - uint32_t dpll_md;
> - uint32_t fp0;
> - uint32_t fp1;
> + u32 dpll;
> + u32 dpll_md;
> + u32 fp0;
> + u32 fp1;
>
> /* hsw, bdw */
> - uint32_t wrpll;
> - uint32_t spll;
> + u32 wrpll;
> + u32 spll;
>
> /* skl */
> /*
> @@ -154,34 +154,33 @@ struct intel_dpll_hw_state {
> * the register. This allows us to easily compare the state to
> share
> * the DPLL.
> */
> - uint32_t ctrl1;
> + u32 ctrl1;
> /* HDMI only, 0 when used for DP */
> - uint32_t cfgcr1, cfgcr2;
> + u32 cfgcr1, cfgcr2;
>
> /* cnl */
> - uint32_t cfgcr0;
> + u32 cfgcr0;
> /* CNL also uses cfgcr1 */
>
> /* bxt */
> - uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9,
> pll10,
> - pcsdw12;
> + u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9,
> pll10, pcsdw12;
>
> /*
> * ICL uses the following, already defined:
> - * uint32_t cfgcr0, cfgcr1;
> - */
> - uint32_t mg_refclkin_ctl;
> - uint32_t mg_clktop2_coreclkctl1;
> - uint32_t mg_clktop2_hsclkctl;
> - uint32_t mg_pll_div0;
> - uint32_t mg_pll_div1;
> - uint32_t mg_pll_lf;
> - uint32_t mg_pll_frac_lock;
> - uint32_t mg_pll_ssc;
> - uint32_t mg_pll_bias;
> - uint32_t mg_pll_tdc_coldst_bias;
> - uint32_t mg_pll_bias_mask;
> - uint32_t mg_pll_tdc_coldst_bias_mask;
> + * u32 cfgcr0, cfgcr1;
> + */
> + u32 mg_refclkin_ctl;
> + u32 mg_clktop2_coreclkctl1;
> + u32 mg_clktop2_hsclkctl;
> + u32 mg_pll_div0;
> + u32 mg_pll_div1;
> + u32 mg_pll_lf;
> + u32 mg_pll_frac_lock;
> + u32 mg_pll_ssc;
> + u32 mg_pll_bias;
> + u32 mg_pll_tdc_coldst_bias;
> + u32 mg_pll_bias_mask;
> + u32 mg_pll_tdc_coldst_bias_mask;
> };
>
> /**
> @@ -280,7 +279,7 @@ struct dpll_info {
> * Inform the state checker that the DPLL is kept enabled
> even if
> * not in use by any CRTC.
> */
> - uint32_t flags;
> + u32 flags;
> };
>
> /**
> @@ -343,7 +342,7 @@ void intel_shared_dpll_init(struct drm_device
> *dev);
> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> struct intel_dpll_hw_state *hw_state);
> int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> - uint32_t pll_id);
> + u32 pll_id);
> int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
> bool intel_dpll_is_combophy(enum intel_dpll_id id);
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 09/17] drm/i915/dp: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (7 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 08/17] drm/i915/dpll_mgr: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:53 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 10/17] drm/i915/sprite: " Jani Nikula
` (13 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Minor checkpatch/whitespace fixes sprinkled on top of the changed lines.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 142 +++++++++---------
drivers/gpu/drm/i915/intel_dp_link_training.c | 32 ++--
2 files changed, 87 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index df4292bb1a4f..808ccdae15b8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -429,7 +429,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
}
static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
- uint8_t lane_count)
+ u8 lane_count)
{
/*
* FIXME: we need to synchronize the current link parameters with
@@ -449,7 +449,7 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
int link_rate,
- uint8_t lane_count)
+ u8 lane_count)
{
const struct drm_display_mode *fixed_mode =
intel_dp->attached_connector->panel.fixed_mode;
@@ -464,7 +464,7 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
}
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
- int link_rate, uint8_t lane_count)
+ int link_rate, u8 lane_count)
{
int index;
@@ -572,19 +572,19 @@ intel_dp_mode_valid(struct drm_connector *connector,
return MODE_OK;
}
-uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
+u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
{
- int i;
- uint32_t v = 0;
+ int i;
+ u32 v = 0;
if (src_bytes > 4)
src_bytes = 4;
for (i = 0; i < src_bytes; i++)
- v |= ((uint32_t) src[i]) << ((3-i) * 8);
+ v |= ((u32)src[i]) << ((3 - i) * 8);
return v;
}
-static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
+static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
{
int i;
if (dst_bytes > 4)
@@ -643,7 +643,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
bool pll_enabled, release_cl_override = false;
enum dpio_phy phy = DPIO_PHY(pipe);
enum dpio_channel ch = vlv_pipe_to_channel(pipe);
- uint32_t DP;
+ u32 DP;
if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
"skipping pipe %c power sequencer kick due to port %c being active\n",
@@ -1051,12 +1051,12 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
}
}
-static uint32_t
+static u32
intel_dp_aux_wait_done(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
- uint32_t status;
+ u32 status;
bool done;
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
@@ -1069,7 +1069,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
return status;
}
-static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1083,7 +1083,7 @@ static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
}
-static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -1102,7 +1102,7 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
}
-static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -1119,7 +1119,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
return ilk_get_aux_clock_divider(intel_dp, index);
}
-static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
/*
* SKL doesn't need us to program the AUX clock divider (Hardware will
@@ -1129,14 +1129,14 @@ static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
return index ? 0 : 1;
}
-static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
- int send_bytes,
- uint32_t aux_clock_divider)
+static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
+ int send_bytes,
+ u32 aux_clock_divider)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
- uint32_t precharge, timeout;
+ u32 precharge, timeout;
if (IS_GEN(dev_priv, 6))
precharge = 3;
@@ -1159,12 +1159,12 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
}
-static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
- int send_bytes,
- uint32_t unused)
+static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
+ int send_bytes,
+ u32 unused)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- uint32_t ret;
+ u32 ret;
ret = DP_AUX_CH_CTL_SEND_BUSY |
DP_AUX_CH_CTL_DONE |
@@ -1184,19 +1184,19 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
static int
intel_dp_aux_xfer(struct intel_dp *intel_dp,
- const uint8_t *send, int send_bytes,
- uint8_t *recv, int recv_size,
+ const u8 *send, int send_bytes,
+ u8 *recv, int recv_size,
u32 aux_send_ctl_flags)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
i915_reg_t ch_ctl, ch_data[5];
- uint32_t aux_clock_divider;
+ u32 aux_clock_divider;
intel_wakeref_t wakeref;
int i, ret, recv_bytes;
int try, clock = 0;
- uint32_t status;
+ u32 status;
bool vdd;
ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
@@ -1369,7 +1369,7 @@ static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
{
struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
- uint8_t txbuf[20], rxbuf[20];
+ u8 txbuf[20], rxbuf[20];
size_t txsize, rxsize;
int ret;
@@ -1702,7 +1702,7 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
}
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
- uint8_t *link_bw, uint8_t *rate_select)
+ u8 *link_bw, u8 *rate_select)
{
/* eDP 1.4 rate select method. */
if (intel_dp->use_rate_select) {
@@ -2217,7 +2217,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
}
void intel_dp_set_link_params(struct intel_dp *intel_dp,
- int link_rate, uint8_t lane_count,
+ int link_rate, u8 lane_count,
bool link_mst)
{
intel_dp->link_trained = false;
@@ -3177,20 +3177,20 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
- uint32_t *DP,
- uint8_t dp_train_pat)
+ u32 *DP,
+ u8 dp_train_pat)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->base.port;
- uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
+ u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
if (dp_train_pat & train_pat_mask)
DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
dp_train_pat & train_pat_mask);
if (HAS_DDI(dev_priv)) {
- uint32_t temp = I915_READ(DP_TP_CTL(port));
+ u32 temp = I915_READ(DP_TP_CTL(port));
if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
@@ -3289,7 +3289,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
- uint32_t dp_reg = I915_READ(intel_dp->output_reg);
+ u32 dp_reg = I915_READ(intel_dp->output_reg);
enum pipe pipe = crtc->pipe;
intel_wakeref_t wakeref;
@@ -3508,14 +3508,14 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
* link status information
*/
bool
-intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
+intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
{
return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
}
/* These are source-specific values. */
-uint8_t
+u8
intel_dp_voltage_max(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -3534,8 +3534,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
}
-uint8_t
-intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
+u8
+intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
@@ -3580,12 +3580,12 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
}
}
-static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
+static u32 vlv_signal_levels(struct intel_dp *intel_dp)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
unsigned long demph_reg_value, preemph_reg_value,
uniqtranscale_reg_value;
- uint8_t train_set = intel_dp->train_set[0];
+ u8 train_set = intel_dp->train_set[0];
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3666,12 +3666,12 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
return 0;
}
-static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
+static u32 chv_signal_levels(struct intel_dp *intel_dp)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
u32 deemph_reg_value, margin_reg_value;
bool uniq_trans_scale = false;
- uint8_t train_set = intel_dp->train_set[0];
+ u8 train_set = intel_dp->train_set[0];
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3749,10 +3749,10 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
return 0;
}
-static uint32_t
-g4x_signal_levels(uint8_t train_set)
+static u32
+g4x_signal_levels(u8 train_set)
{
- uint32_t signal_levels = 0;
+ u32 signal_levels = 0;
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
@@ -3788,8 +3788,8 @@ g4x_signal_levels(uint8_t train_set)
}
/* SNB CPU eDP voltage swing and pre-emphasis control */
-static uint32_t
-snb_cpu_edp_signal_levels(uint8_t train_set)
+static u32
+snb_cpu_edp_signal_levels(u8 train_set)
{
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -3816,8 +3816,8 @@ snb_cpu_edp_signal_levels(uint8_t train_set)
}
/* IVB CPU eDP voltage swing and pre-emphasis control */
-static uint32_t
-ivb_cpu_edp_signal_levels(uint8_t train_set)
+static u32
+ivb_cpu_edp_signal_levels(u8 train_set)
{
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -3852,8 +3852,8 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->base.port;
- uint32_t signal_levels, mask = 0;
- uint8_t train_set = intel_dp->train_set[0];
+ u32 signal_levels, mask = 0;
+ u8 train_set = intel_dp->train_set[0];
if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
signal_levels = bxt_signal_levels(intel_dp);
@@ -3892,7 +3892,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
- uint8_t dp_train_pat)
+ u8 dp_train_pat)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv =
@@ -3909,7 +3909,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->base.port;
- uint32_t val;
+ u32 val;
if (!HAS_DDI(dev_priv))
return;
@@ -3944,7 +3944,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
enum port port = encoder->port;
- uint32_t DP = intel_dp->DP;
+ u32 DP = intel_dp->DP;
if (WARN_ON(HAS_DDI(dev_priv)))
return;
@@ -4285,7 +4285,7 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
DP_DPRX_ESI_LEN;
}
-u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
+u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
int mode_clock, int mode_hdisplay)
{
u16 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -4352,7 +4352,7 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
return 0;
}
/* Also take into account max slice width */
- min_slice_count = min_t(uint8_t, min_slice_count,
+ min_slice_count = min_t(u8, min_slice_count,
DIV_ROUND_UP(mode_hdisplay,
max_slice_width));
@@ -4370,11 +4370,11 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
return 0;
}
-static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
+static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
int status = 0;
int test_link_rate;
- uint8_t test_lane_count, test_link_bw;
+ u8 test_lane_count, test_link_bw;
/* (DP CTS 1.2)
* 4.3.1.11
*/
@@ -4407,10 +4407,10 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
return DP_TEST_ACK;
}
-static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
+static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
- uint8_t test_pattern;
- uint8_t test_misc;
+ u8 test_pattern;
+ u8 test_misc;
__be16 h_width, v_height;
int status = 0;
@@ -4468,9 +4468,9 @@ static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
return DP_TEST_ACK;
}
-static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
+static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
{
- uint8_t test_result = DP_TEST_ACK;
+ u8 test_result = DP_TEST_ACK;
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct drm_connector *connector = &intel_connector->base;
@@ -4512,16 +4512,16 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
return test_result;
}
-static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
+static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
- uint8_t test_result = DP_TEST_NAK;
+ u8 test_result = DP_TEST_NAK;
return test_result;
}
static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
- uint8_t response = DP_TEST_NAK;
- uint8_t request = 0;
+ u8 response = DP_TEST_NAK;
+ u8 request = 0;
int status;
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
@@ -4847,8 +4847,8 @@ static enum drm_connector_status
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
{
struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
- uint8_t *dpcd = intel_dp->dpcd;
- uint8_t type;
+ u8 *dpcd = intel_dp->dpcd;
+ u8 type;
if (lspcon->active)
lspcon_resume(lspcon);
@@ -5630,7 +5630,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
.address = DP_AUX_HDCP_AKSV,
.size = DRM_HDCP_KSV_LEN,
};
- uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
+ u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
ssize_t dpcd_ret;
int ret;
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 30be0e39bd5f..b59c87daa4f7 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -24,7 +24,7 @@
#include "intel_drv.h"
static void
-intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
+intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
{
DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
@@ -34,17 +34,17 @@ intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
static void
intel_get_adjust_train(struct intel_dp *intel_dp,
- const uint8_t link_status[DP_LINK_STATUS_SIZE])
+ const u8 link_status[DP_LINK_STATUS_SIZE])
{
- uint8_t v = 0;
- uint8_t p = 0;
+ u8 v = 0;
+ u8 p = 0;
int lane;
- uint8_t voltage_max;
- uint8_t preemph_max;
+ u8 voltage_max;
+ u8 preemph_max;
for (lane = 0; lane < intel_dp->lane_count; lane++) {
- uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
- uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
+ u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
+ u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
if (this_v > v)
v = this_v;
@@ -66,9 +66,9 @@ intel_get_adjust_train(struct intel_dp *intel_dp,
static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
- uint8_t dp_train_pat)
+ u8 dp_train_pat)
{
- uint8_t buf[sizeof(intel_dp->train_set) + 1];
+ u8 buf[sizeof(intel_dp->train_set) + 1];
int ret, len;
intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
@@ -92,7 +92,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp,
- uint8_t dp_train_pat)
+ u8 dp_train_pat)
{
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
@@ -128,11 +128,11 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
static bool
intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
{
- uint8_t voltage;
+ u8 voltage;
int voltage_tries, cr_tries, max_cr_tries;
bool max_vswing_reached = false;
- uint8_t link_config[2];
- uint8_t link_bw, rate_select;
+ u8 link_config[2];
+ u8 link_bw, rate_select;
if (intel_dp->prepare_link_retrain)
intel_dp->prepare_link_retrain(intel_dp);
@@ -186,7 +186,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
voltage_tries = 1;
for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
- uint8_t link_status[DP_LINK_STATUS_SIZE];
+ u8 link_status[DP_LINK_STATUS_SIZE];
drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
@@ -282,7 +282,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
{
int tries;
u32 training_pattern;
- uint8_t link_status[DP_LINK_STATUS_SIZE];
+ u8 link_status[DP_LINK_STATUS_SIZE];
bool channel_eq = false;
training_pattern = intel_dp_training_pattern(intel_dp);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 09/17] drm/i915/dp: switch to kernel types
2019-01-16 9:15 ` [PATCH 09/17] drm/i915/dp: " Jani Nikula
@ 2019-01-17 0:53 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:53 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 21835 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch/whitespace fixes sprinkled on top of the changed
> lines.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 142 +++++++++-------
> --
> drivers/gpu/drm/i915/intel_dp_link_training.c | 32 ++--
> 2 files changed, 87 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index df4292bb1a4f..808ccdae15b8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -429,7 +429,7 @@ static void intel_dp_set_common_rates(struct
> intel_dp *intel_dp)
> }
>
> static bool intel_dp_link_params_valid(struct intel_dp *intel_dp,
> int link_rate,
> - uint8_t lane_count)
> + u8 lane_count)
> {
> /*
> * FIXME: we need to synchronize the current link parameters
> with
> @@ -449,7 +449,7 @@ static bool intel_dp_link_params_valid(struct
> intel_dp *intel_dp, int link_rate,
>
> static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp
> *intel_dp,
> int link_rate,
> - uint8_t
> lane_count)
> + u8 lane_count)
> {
> const struct drm_display_mode *fixed_mode =
> intel_dp->attached_connector->panel.fixed_mode;
> @@ -464,7 +464,7 @@ static bool
> intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
> }
>
> int intel_dp_get_link_train_fallback_values(struct intel_dp
> *intel_dp,
> - int link_rate, uint8_t
> lane_count)
> + int link_rate, u8
> lane_count)
> {
> int index;
>
> @@ -572,19 +572,19 @@ intel_dp_mode_valid(struct drm_connector
> *connector,
> return MODE_OK;
> }
>
> -uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
> +u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
> {
> - int i;
> - uint32_t v = 0;
> + int i;
> + u32 v = 0;
>
> if (src_bytes > 4)
> src_bytes = 4;
> for (i = 0; i < src_bytes; i++)
> - v |= ((uint32_t) src[i]) << ((3-i) * 8);
> + v |= ((u32)src[i]) << ((3 - i) * 8);
> return v;
> }
>
> -static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int
> dst_bytes)
> +static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
> {
> int i;
> if (dst_bytes > 4)
> @@ -643,7 +643,7 @@ vlv_power_sequencer_kick(struct intel_dp
> *intel_dp)
> bool pll_enabled, release_cl_override = false;
> enum dpio_phy phy = DPIO_PHY(pipe);
> enum dpio_channel ch = vlv_pipe_to_channel(pipe);
> - uint32_t DP;
> + u32 DP;
>
> if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
> "skipping pipe %c power sequencer kick due to port %c
> being active\n",
> @@ -1051,12 +1051,12 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
> }
> }
>
> -static uint32_t
> +static u32
> intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> - uint32_t status;
> + u32 status;
> bool done;
>
> #define C (((status = I915_READ_NOTRACE(ch_ctl)) &
> DP_AUX_CH_CTL_SEND_BUSY) == 0)
> @@ -1069,7 +1069,7 @@ intel_dp_aux_wait_done(struct intel_dp
> *intel_dp)
> return status;
> }
>
> -static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp,
> int index)
> +static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int
> index)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> @@ -1083,7 +1083,7 @@ static uint32_t
> g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
> }
>
> -static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp,
> int index)
> +static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int
> index)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -1102,7 +1102,7 @@ static uint32_t
> ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
> }
>
> -static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp,
> int index)
> +static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int
> index)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -1119,7 +1119,7 @@ static uint32_t
> hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> return ilk_get_aux_clock_divider(intel_dp, index);
> }
>
> -static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp,
> int index)
> +static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int
> index)
> {
> /*
> * SKL doesn't need us to program the AUX clock divider
> (Hardware will
> @@ -1129,14 +1129,14 @@ static uint32_t
> skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> return index ? 0 : 1;
> }
>
> -static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> - int send_bytes,
> - uint32_t aux_clock_divider)
> +static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> + int send_bytes,
> + u32 aux_clock_divider)
> {
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv =
> to_i915(intel_dig_port->base.base.dev);
> - uint32_t precharge, timeout;
> + u32 precharge, timeout;
>
> if (IS_GEN(dev_priv, 6))
> precharge = 3;
> @@ -1159,12 +1159,12 @@ static uint32_t g4x_get_aux_send_ctl(struct
> intel_dp *intel_dp,
> (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
> }
>
> -static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> - int send_bytes,
> - uint32_t unused)
> +static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> + int send_bytes,
> + u32 unused)
> {
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> - uint32_t ret;
> + u32 ret;
>
> ret = DP_AUX_CH_CTL_SEND_BUSY |
> DP_AUX_CH_CTL_DONE |
> @@ -1184,19 +1184,19 @@ static uint32_t skl_get_aux_send_ctl(struct
> intel_dp *intel_dp,
>
> static int
> intel_dp_aux_xfer(struct intel_dp *intel_dp,
> - const uint8_t *send, int send_bytes,
> - uint8_t *recv, int recv_size,
> + const u8 *send, int send_bytes,
> + u8 *recv, int recv_size,
> u32 aux_send_ctl_flags)
> {
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv =
> to_i915(intel_dig_port->base.base.dev);
> i915_reg_t ch_ctl, ch_data[5];
> - uint32_t aux_clock_divider;
> + u32 aux_clock_divider;
> intel_wakeref_t wakeref;
> int i, ret, recv_bytes;
> int try, clock = 0;
> - uint32_t status;
> + u32 status;
> bool vdd;
>
> ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> @@ -1369,7 +1369,7 @@ static ssize_t
> intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
> *msg)
> {
> struct intel_dp *intel_dp = container_of(aux, struct intel_dp,
> aux);
> - uint8_t txbuf[20], rxbuf[20];
> + u8 txbuf[20], rxbuf[20];
> size_t txsize, rxsize;
> int ret;
>
> @@ -1702,7 +1702,7 @@ int intel_dp_rate_select(struct intel_dp
> *intel_dp, int rate)
> }
>
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int
> port_clock,
> - uint8_t *link_bw, uint8_t *rate_select)
> + u8 *link_bw, u8 *rate_select)
> {
> /* eDP 1.4 rate select method. */
> if (intel_dp->use_rate_select) {
> @@ -2217,7 +2217,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> }
>
> void intel_dp_set_link_params(struct intel_dp *intel_dp,
> - int link_rate, uint8_t lane_count,
> + int link_rate, u8 lane_count,
> bool link_mst)
> {
> intel_dp->link_trained = false;
> @@ -3177,20 +3177,20 @@ static void chv_post_disable_dp(struct
> intel_encoder *encoder,
>
> static void
> _intel_dp_set_link_train(struct intel_dp *intel_dp,
> - uint32_t *DP,
> - uint8_t dp_train_pat)
> + u32 *DP,
> + u8 dp_train_pat)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> enum port port = intel_dig_port->base.port;
> - uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp-
> >dpcd);
> + u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp-
> >dpcd);
>
> if (dp_train_pat & train_pat_mask)
> DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
> dp_train_pat & train_pat_mask);
>
> if (HAS_DDI(dev_priv)) {
> - uint32_t temp = I915_READ(DP_TP_CTL(port));
> + u32 temp = I915_READ(DP_TP_CTL(port));
>
> if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
> @@ -3289,7 +3289,7 @@ static void intel_enable_dp(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config-
> >base.crtc);
> - uint32_t dp_reg = I915_READ(intel_dp->output_reg);
> + u32 dp_reg = I915_READ(intel_dp->output_reg);
> enum pipe pipe = crtc->pipe;
> intel_wakeref_t wakeref;
>
> @@ -3508,14 +3508,14 @@ static void chv_dp_post_pll_disable(struct
> intel_encoder *encoder,
> * link status information
> */
> bool
> -intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t
> link_status[DP_LINK_STATUS_SIZE])
> +intel_dp_get_link_status(struct intel_dp *intel_dp, u8
> link_status[DP_LINK_STATUS_SIZE])
> {
> return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS,
> link_status,
> DP_LINK_STATUS_SIZE) ==
> DP_LINK_STATUS_SIZE;
> }
>
> /* These are source-specific values. */
> -uint8_t
> +u8
> intel_dp_voltage_max(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -3534,8 +3534,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> }
>
> -uint8_t
> -intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t
> voltage_swing)
> +u8
> +intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8
> voltage_swing)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)-
> >base;
> @@ -3580,12 +3580,12 @@ intel_dp_pre_emphasis_max(struct intel_dp
> *intel_dp, uint8_t voltage_swing)
> }
> }
>
> -static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> +static u32 vlv_signal_levels(struct intel_dp *intel_dp)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)-
> >base;
> unsigned long demph_reg_value, preemph_reg_value,
> uniqtranscale_reg_value;
> - uint8_t train_set = intel_dp->train_set[0];
> + u8 train_set = intel_dp->train_set[0];
>
> switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3666,12 +3666,12 @@ static uint32_t vlv_signal_levels(struct
> intel_dp *intel_dp)
> return 0;
> }
>
> -static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
> +static u32 chv_signal_levels(struct intel_dp *intel_dp)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)-
> >base;
> u32 deemph_reg_value, margin_reg_value;
> bool uniq_trans_scale = false;
> - uint8_t train_set = intel_dp->train_set[0];
> + u8 train_set = intel_dp->train_set[0];
>
> switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3749,10 +3749,10 @@ static uint32_t chv_signal_levels(struct
> intel_dp *intel_dp)
> return 0;
> }
>
> -static uint32_t
> -g4x_signal_levels(uint8_t train_set)
> +static u32
> +g4x_signal_levels(u8 train_set)
> {
> - uint32_t signal_levels = 0;
> + u32 signal_levels = 0;
>
> switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> @@ -3788,8 +3788,8 @@ g4x_signal_levels(uint8_t train_set)
> }
>
> /* SNB CPU eDP voltage swing and pre-emphasis control */
> -static uint32_t
> -snb_cpu_edp_signal_levels(uint8_t train_set)
> +static u32
> +snb_cpu_edp_signal_levels(u8 train_set)
> {
> int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> DP_TRAIN_PRE_EMPHASIS_MASK);
> @@ -3816,8 +3816,8 @@ snb_cpu_edp_signal_levels(uint8_t train_set)
> }
>
> /* IVB CPU eDP voltage swing and pre-emphasis control */
> -static uint32_t
> -ivb_cpu_edp_signal_levels(uint8_t train_set)
> +static u32
> +ivb_cpu_edp_signal_levels(u8 train_set)
> {
> int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> DP_TRAIN_PRE_EMPHASIS_MASK);
> @@ -3852,8 +3852,8 @@ intel_dp_set_signal_levels(struct intel_dp
> *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> enum port port = intel_dig_port->base.port;
> - uint32_t signal_levels, mask = 0;
> - uint8_t train_set = intel_dp->train_set[0];
> + u32 signal_levels, mask = 0;
> + u8 train_set = intel_dp->train_set[0];
>
> if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> signal_levels = bxt_signal_levels(intel_dp);
> @@ -3892,7 +3892,7 @@ intel_dp_set_signal_levels(struct intel_dp
> *intel_dp)
>
> void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> - uint8_t dp_train_pat)
> + u8 dp_train_pat)
> {
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv =
> @@ -3909,7 +3909,7 @@ void intel_dp_set_idle_link_train(struct
> intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> enum port port = intel_dig_port->base.port;
> - uint32_t val;
> + u32 val;
>
> if (!HAS_DDI(dev_priv))
> return;
> @@ -3944,7 +3944,7 @@ intel_dp_link_down(struct intel_encoder
> *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> >base.crtc);
> enum port port = encoder->port;
> - uint32_t DP = intel_dp->DP;
> + u32 DP = intel_dp->DP;
>
> if (WARN_ON(HAS_DDI(dev_priv)))
> return;
> @@ -4285,7 +4285,7 @@ intel_dp_get_sink_irq_esi(struct intel_dp
> *intel_dp, u8 *sink_irq_vector)
> DP_DPRX_ESI_LEN;
> }
>
> -u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
> +u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
> int mode_clock, int mode_hdisplay)
> {
> u16 bits_per_pixel, max_bpp_small_joiner_ram;
> @@ -4352,7 +4352,7 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp
> *intel_dp,
> return 0;
> }
> /* Also take into account max slice width */
> - min_slice_count = min_t(uint8_t, min_slice_count,
> + min_slice_count = min_t(u8, min_slice_count,
> DIV_ROUND_UP(mode_hdisplay,
> max_slice_width));
>
> @@ -4370,11 +4370,11 @@ u8 intel_dp_dsc_get_slice_count(struct
> intel_dp *intel_dp,
> return 0;
> }
>
> -static uint8_t intel_dp_autotest_link_training(struct intel_dp
> *intel_dp)
> +static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
> {
> int status = 0;
> int test_link_rate;
> - uint8_t test_lane_count, test_link_bw;
> + u8 test_lane_count, test_link_bw;
> /* (DP CTS 1.2)
> * 4.3.1.11
> */
> @@ -4407,10 +4407,10 @@ static uint8_t
> intel_dp_autotest_link_training(struct intel_dp *intel_dp)
> return DP_TEST_ACK;
> }
>
> -static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
> *intel_dp)
> +static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
> {
> - uint8_t test_pattern;
> - uint8_t test_misc;
> + u8 test_pattern;
> + u8 test_misc;
> __be16 h_width, v_height;
> int status = 0;
>
> @@ -4468,9 +4468,9 @@ static uint8_t
> intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
> return DP_TEST_ACK;
> }
>
> -static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
> +static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
> {
> - uint8_t test_result = DP_TEST_ACK;
> + u8 test_result = DP_TEST_ACK;
> struct intel_connector *intel_connector = intel_dp-
> >attached_connector;
> struct drm_connector *connector = &intel_connector->base;
>
> @@ -4512,16 +4512,16 @@ static uint8_t intel_dp_autotest_edid(struct
> intel_dp *intel_dp)
> return test_result;
> }
>
> -static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
> *intel_dp)
> +static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> {
> - uint8_t test_result = DP_TEST_NAK;
> + u8 test_result = DP_TEST_NAK;
> return test_result;
> }
>
> static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> {
> - uint8_t response = DP_TEST_NAK;
> - uint8_t request = 0;
> + u8 response = DP_TEST_NAK;
> + u8 request = 0;
> int status;
>
> status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST,
> &request);
> @@ -4847,8 +4847,8 @@ static enum drm_connector_status
> intel_dp_detect_dpcd(struct intel_dp *intel_dp)
> {
> struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
> - uint8_t *dpcd = intel_dp->dpcd;
> - uint8_t type;
> + u8 *dpcd = intel_dp->dpcd;
> + u8 type;
>
> if (lspcon->active)
> lspcon_resume(lspcon);
> @@ -5630,7 +5630,7 @@ int intel_dp_hdcp_write_an_aksv(struct
> intel_digital_port *intel_dig_port,
> .address = DP_AUX_HDCP_AKSV,
> .size = DRM_HDCP_KSV_LEN,
> };
> - uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2],
> reply = 0;
> + u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply
> = 0;
> ssize_t dpcd_ret;
> int ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 30be0e39bd5f..b59c87daa4f7 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -24,7 +24,7 @@
> #include "intel_drv.h"
>
> static void
> -intel_dp_dump_link_status(const uint8_t
> link_status[DP_LINK_STATUS_SIZE])
> +intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
> {
>
> DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x
> adj_req0_1:0x%x adj_req2_3:0x%x",
> @@ -34,17 +34,17 @@ intel_dp_dump_link_status(const uint8_t
> link_status[DP_LINK_STATUS_SIZE])
>
> static void
> intel_get_adjust_train(struct intel_dp *intel_dp,
> - const uint8_t link_status[DP_LINK_STATUS_SIZE])
> + const u8 link_status[DP_LINK_STATUS_SIZE])
> {
> - uint8_t v = 0;
> - uint8_t p = 0;
> + u8 v = 0;
> + u8 p = 0;
> int lane;
> - uint8_t voltage_max;
> - uint8_t preemph_max;
> + u8 voltage_max;
> + u8 preemph_max;
>
> for (lane = 0; lane < intel_dp->lane_count; lane++) {
> - uint8_t this_v =
> drm_dp_get_adjust_request_voltage(link_status, lane);
> - uint8_t this_p =
> drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> + u8 this_v =
> drm_dp_get_adjust_request_voltage(link_status, lane);
> + u8 this_p =
> drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>
> if (this_v > v)
> v = this_v;
> @@ -66,9 +66,9 @@ intel_get_adjust_train(struct intel_dp *intel_dp,
>
> static bool
> intel_dp_set_link_train(struct intel_dp *intel_dp,
> - uint8_t dp_train_pat)
> + u8 dp_train_pat)
> {
> - uint8_t buf[sizeof(intel_dp->train_set) + 1];
> + u8 buf[sizeof(intel_dp->train_set) + 1];
> int ret, len;
>
> intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
> @@ -92,7 +92,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>
> static bool
> intel_dp_reset_link_train(struct intel_dp *intel_dp,
> - uint8_t dp_train_pat)
> + u8 dp_train_pat)
> {
> memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> intel_dp_set_signal_levels(intel_dp);
> @@ -128,11 +128,11 @@ static bool
> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
> static bool
> intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> {
> - uint8_t voltage;
> + u8 voltage;
> int voltage_tries, cr_tries, max_cr_tries;
> bool max_vswing_reached = false;
> - uint8_t link_config[2];
> - uint8_t link_bw, rate_select;
> + u8 link_config[2];
> + u8 link_bw, rate_select;
>
> if (intel_dp->prepare_link_retrain)
> intel_dp->prepare_link_retrain(intel_dp);
> @@ -186,7 +186,7 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
>
> voltage_tries = 1;
> for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> - uint8_t link_status[DP_LINK_STATUS_SIZE];
> + u8 link_status[DP_LINK_STATUS_SIZE];
>
> drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
>
> @@ -282,7 +282,7 @@
> intel_dp_link_training_channel_equalization(struct intel_dp
> *intel_dp)
> {
> int tries;
> u32 training_pattern;
> - uint8_t link_status[DP_LINK_STATUS_SIZE];
> + u8 link_status[DP_LINK_STATUS_SIZE];
> bool channel_eq = false;
>
> training_pattern = intel_dp_training_pattern(intel_dp);
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 10/17] drm/i915/sprite: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (8 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 09/17] drm/i915/dp: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:55 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 11/17] drm/i915/color: " Jani Nikula
` (12 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_sprite.c | 60 ++++++++++++++---------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 87a06fcca284..b02d3d9809e3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -321,8 +321,8 @@ skl_program_scaler(struct intel_plane *plane,
&crtc_state->scaler_state.scalers[scaler_id];
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
- uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
- uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
+ u32 crtc_w = drm_rect_width(&plane_state->base.dst);
+ u32 crtc_h = drm_rect_height(&plane_state->base.dst);
u16 y_hphase, uv_rgb_hphase;
u16 y_vphase, uv_rgb_vphase;
int hscale, vscale;
@@ -477,10 +477,10 @@ skl_program_plane(struct intel_plane *plane,
u32 aux_stride = skl_plane_stride(plane_state, 1);
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
- uint32_t x = plane_state->color_plane[color_plane].x;
- uint32_t y = plane_state->color_plane[color_plane].y;
- uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
- uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ u32 x = plane_state->color_plane[color_plane].x;
+ u32 y = plane_state->color_plane[color_plane].y;
+ u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
struct intel_plane *linked = plane_state->linked_plane;
const struct drm_framebuffer *fb = plane_state->base.fb;
u8 alpha = plane_state->base.alpha >> 8;
@@ -814,10 +814,10 @@ vlv_update_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
- uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
- uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
- uint32_t x = plane_state->color_plane[0].x;
- uint32_t y = plane_state->color_plane[0].y;
+ u32 crtc_w = drm_rect_width(&plane_state->base.dst);
+ u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+ u32 x = plane_state->color_plane[0].x;
+ u32 y = plane_state->color_plane[0].y;
unsigned long irqflags;
/* Sizes are 0 based */
@@ -976,12 +976,12 @@ ivb_update_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
- uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
- uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
- uint32_t x = plane_state->color_plane[0].x;
- uint32_t y = plane_state->color_plane[0].y;
- uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
- uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ u32 crtc_w = drm_rect_width(&plane_state->base.dst);
+ u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+ u32 x = plane_state->color_plane[0].x;
+ u32 y = plane_state->color_plane[0].y;
+ u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
unsigned long irqflags;
/* Sizes are 0 based */
@@ -1152,12 +1152,12 @@ g4x_update_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
- uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
- uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
- uint32_t x = plane_state->color_plane[0].x;
- uint32_t y = plane_state->color_plane[0].y;
- uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
- uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ u32 crtc_w = drm_rect_width(&plane_state->base.dst);
+ u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+ u32 x = plane_state->color_plane[0].x;
+ u32 y = plane_state->color_plane[0].y;
+ u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
unsigned long irqflags;
/* Sizes are 0 based */
@@ -1706,7 +1706,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
return ret;
}
-static const uint32_t g4x_plane_formats[] = {
+static const u32 g4x_plane_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
@@ -1714,13 +1714,13 @@ static const uint32_t g4x_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static const uint64_t i9xx_plane_format_modifiers[] = {
+static const u64 i9xx_plane_format_modifiers[] = {
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_INVALID
};
-static const uint32_t snb_plane_formats[] = {
+static const u32 snb_plane_formats[] = {
DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_YUYV,
@@ -1729,7 +1729,7 @@ static const uint32_t snb_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static const uint32_t vlv_plane_formats[] = {
+static const u32 vlv_plane_formats[] = {
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
@@ -1743,7 +1743,7 @@ static const uint32_t vlv_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static const uint32_t skl_plane_formats[] = {
+static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888,
@@ -1758,7 +1758,7 @@ static const uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static const uint32_t skl_planar_formats[] = {
+static const u32 skl_planar_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888,
@@ -1774,7 +1774,7 @@ static const uint32_t skl_planar_formats[] = {
DRM_FORMAT_NV12,
};
-static const uint64_t skl_plane_format_modifiers_noccs[] = {
+static const u64 skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
@@ -1782,7 +1782,7 @@ static const uint64_t skl_plane_format_modifiers_noccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const uint64_t skl_plane_format_modifiers_ccs[] = {
+static const u64 skl_plane_format_modifiers_ccs[] = {
I915_FORMAT_MOD_Yf_TILED_CCS,
I915_FORMAT_MOD_Y_TILED_CCS,
I915_FORMAT_MOD_Yf_TILED,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 10/17] drm/i915/sprite: switch to kernel types
2019-01-16 9:15 ` [PATCH 10/17] drm/i915/sprite: " Jani Nikula
@ 2019-01-17 0:55 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:55 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 7067 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 60 ++++++++++++++-------------
> --
> 1 file changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 87a06fcca284..b02d3d9809e3 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -321,8 +321,8 @@ skl_program_scaler(struct intel_plane *plane,
> &crtc_state->scaler_state.scalers[scaler_id];
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> - uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> - uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
> + u32 crtc_w = drm_rect_width(&plane_state->base.dst);
> + u32 crtc_h = drm_rect_height(&plane_state->base.dst);
> u16 y_hphase, uv_rgb_hphase;
> u16 y_vphase, uv_rgb_vphase;
> int hscale, vscale;
> @@ -477,10 +477,10 @@ skl_program_plane(struct intel_plane *plane,
> u32 aux_stride = skl_plane_stride(plane_state, 1);
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> - uint32_t x = plane_state->color_plane[color_plane].x;
> - uint32_t y = plane_state->color_plane[color_plane].y;
> - uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> - uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> + u32 x = plane_state->color_plane[color_plane].x;
> + u32 y = plane_state->color_plane[color_plane].y;
> + u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
> + u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
> struct intel_plane *linked = plane_state->linked_plane;
> const struct drm_framebuffer *fb = plane_state->base.fb;
> u8 alpha = plane_state->base.alpha >> 8;
> @@ -814,10 +814,10 @@ vlv_update_plane(struct intel_plane *plane,
> const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> - uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> - uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
> - uint32_t x = plane_state->color_plane[0].x;
> - uint32_t y = plane_state->color_plane[0].y;
> + u32 crtc_w = drm_rect_width(&plane_state->base.dst);
> + u32 crtc_h = drm_rect_height(&plane_state->base.dst);
> + u32 x = plane_state->color_plane[0].x;
> + u32 y = plane_state->color_plane[0].y;
> unsigned long irqflags;
>
> /* Sizes are 0 based */
> @@ -976,12 +976,12 @@ ivb_update_plane(struct intel_plane *plane,
> const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> - uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> - uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
> - uint32_t x = plane_state->color_plane[0].x;
> - uint32_t y = plane_state->color_plane[0].y;
> - uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> - uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> + u32 crtc_w = drm_rect_width(&plane_state->base.dst);
> + u32 crtc_h = drm_rect_height(&plane_state->base.dst);
> + u32 x = plane_state->color_plane[0].x;
> + u32 y = plane_state->color_plane[0].y;
> + u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
> + u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
> unsigned long irqflags;
>
> /* Sizes are 0 based */
> @@ -1152,12 +1152,12 @@ g4x_update_plane(struct intel_plane *plane,
> const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> - uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> - uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
> - uint32_t x = plane_state->color_plane[0].x;
> - uint32_t y = plane_state->color_plane[0].y;
> - uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> - uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> + u32 crtc_w = drm_rect_width(&plane_state->base.dst);
> + u32 crtc_h = drm_rect_height(&plane_state->base.dst);
> + u32 x = plane_state->color_plane[0].x;
> + u32 y = plane_state->color_plane[0].y;
> + u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
> + u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
> unsigned long irqflags;
>
> /* Sizes are 0 based */
> @@ -1706,7 +1706,7 @@ int intel_sprite_set_colorkey_ioctl(struct
> drm_device *dev, void *data,
> return ret;
> }
>
> -static const uint32_t g4x_plane_formats[] = {
> +static const u32 g4x_plane_formats[] = {
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> @@ -1714,13 +1714,13 @@ static const uint32_t g4x_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
> -static const uint64_t i9xx_plane_format_modifiers[] = {
> +static const u64 i9xx_plane_format_modifiers[] = {
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> DRM_FORMAT_MOD_INVALID
> };
>
> -static const uint32_t snb_plane_formats[] = {
> +static const u32 snb_plane_formats[] = {
> DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_YUYV,
> @@ -1729,7 +1729,7 @@ static const uint32_t snb_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
> -static const uint32_t vlv_plane_formats[] = {
> +static const u32 vlv_plane_formats[] = {
> DRM_FORMAT_RGB565,
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_ARGB8888,
> @@ -1743,7 +1743,7 @@ static const uint32_t vlv_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
> -static const uint32_t skl_plane_formats[] = {
> +static const u32 skl_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> @@ -1758,7 +1758,7 @@ static const uint32_t skl_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
> -static const uint32_t skl_planar_formats[] = {
> +static const u32 skl_planar_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> @@ -1774,7 +1774,7 @@ static const uint32_t skl_planar_formats[] = {
> DRM_FORMAT_NV12,
> };
>
> -static const uint64_t skl_plane_format_modifiers_noccs[] = {
> +static const u64 skl_plane_format_modifiers_noccs[] = {
> I915_FORMAT_MOD_Yf_TILED,
> I915_FORMAT_MOD_Y_TILED,
> I915_FORMAT_MOD_X_TILED,
> @@ -1782,7 +1782,7 @@ static const uint64_t
> skl_plane_format_modifiers_noccs[] = {
> DRM_FORMAT_MOD_INVALID
> };
>
> -static const uint64_t skl_plane_format_modifiers_ccs[] = {
> +static const u64 skl_plane_format_modifiers_ccs[] = {
> I915_FORMAT_MOD_Yf_TILED_CCS,
> I915_FORMAT_MOD_Y_TILED_CCS,
> I915_FORMAT_MOD_Yf_TILED,
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 11/17] drm/i915/color: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (9 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 10/17] drm/i915/sprite: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 0:58 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 12/17] drm/i915/pm: " Jani Nikula
` (11 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 40 +++++++++++++++---------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 37fd9ddf762e..299eb7858adc 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -142,7 +142,7 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int i, pipe = crtc->pipe;
- uint16_t coeffs[9] = { 0, };
+ u16 coeffs[9] = { 0, };
bool limited_color_range = false;
/*
@@ -171,7 +171,7 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
* hardware.
*/
for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
- uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];
+ u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
/*
* Clamp input value to min/max supported by
@@ -233,7 +233,7 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
if (INTEL_GEN(dev_priv) > 6) {
- uint16_t postoff = 0;
+ u16 postoff = 0;
if (limited_color_range)
postoff = (16 * (1 << 12) / 255) & 0x1fff;
@@ -244,7 +244,7 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
I915_WRITE(PIPE_CSC_MODE(pipe), 0);
} else {
- uint32_t mode = CSC_MODE_YUV_TO_RGB;
+ u32 mode = CSC_MODE_YUV_TO_RGB;
if (limited_color_range)
mode |= CSC_BLACK_SCREEN_OFFSET;
@@ -261,15 +261,15 @@ static void cherryview_load_csc_matrix(struct intel_crtc_state *crtc_state)
struct drm_device *dev = crtc_state->base.crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
- uint32_t mode;
+ u32 mode;
if (crtc_state->base.ctm) {
struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
- uint16_t coeffs[9] = { 0, };
+ u16 coeffs[9] = { 0, };
int i;
for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
- uint64_t abs_coeff =
+ u64 abs_coeff =
((1ULL << 63) - 1) & ctm->matrix[i];
/* Round coefficient. */
@@ -331,7 +331,7 @@ static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
if (blob) {
struct drm_color_lut *lut = blob->data;
for (i = 0; i < 256; i++) {
- uint32_t word =
+ u32 word =
(drm_color_lut_extract(lut[i].red, 8) << 16) |
(drm_color_lut_extract(lut[i].green, 8) << 8) |
drm_color_lut_extract(lut[i].blue, 8);
@@ -343,7 +343,7 @@ static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
}
} else {
for (i = 0; i < 256; i++) {
- uint32_t word = (i << 16) | (i << 8) | i;
+ u32 word = (i << 16) | (i << 8) | i;
if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word);
@@ -388,7 +388,7 @@ static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
- uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
I915_WRITE(PREC_PAL_INDEX(pipe),
PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
@@ -397,7 +397,7 @@ static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
for (i = 0; i < lut_size; i++) {
- uint32_t word =
+ u32 word =
drm_color_lut_extract(lut[i].red, 10) << 20 |
drm_color_lut_extract(lut[i].green, 10) << 10 |
drm_color_lut_extract(lut[i].blue, 10);
@@ -406,7 +406,7 @@ static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
}
} else {
for (i = 0; i < lut_size; i++) {
- uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
+ u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
I915_WRITE(PREC_PAL_DATA(pipe),
(v << 20) | (v << 10) | v);
@@ -418,7 +418,7 @@ static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
- uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
@@ -431,7 +431,7 @@ static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
struct drm_color_lut *lut = crtc_state->base.gamma_lut->data;
for (i = 0; i < lut_size; i++) {
- uint32_t word =
+ u32 word =
(drm_color_lut_extract(lut[i].red, 10) << 20) |
(drm_color_lut_extract(lut[i].green, 10) << 10) |
drm_color_lut_extract(lut[i].blue, 10);
@@ -449,7 +449,7 @@ static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
drm_color_lut_extract(lut[i].blue, 16));
} else {
for (i = 0; i < lut_size; i++) {
- uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
+ u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
I915_WRITE(PREC_PAL_DATA(pipe),
(v << 20) | (v << 10) | v);
@@ -491,8 +491,8 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
- const uint32_t lut_size = 33;
- uint32_t i;
+ const u32 lut_size = 33;
+ u32 i;
/*
* When setting the auto-increment bit, the hardware seems to
@@ -507,7 +507,7 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
* different values per channel, so this just loads a linear table.
*/
for (i = 0; i < lut_size; i++) {
- uint32_t v = (i * (1 << 16)) / (lut_size - 1);
+ u32 v = (i * (1 << 16)) / (lut_size - 1);
I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
}
@@ -544,8 +544,8 @@ static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
struct drm_color_lut *lut;
- uint32_t i, lut_size;
- uint32_t word0, word1;
+ u32 i, lut_size;
+ u32 word0, word1;
if (crtc_state_is_legacy_gamma(crtc_state)) {
/* Turn off degamma/gamma on CGM block. */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 11/17] drm/i915/color: switch to kernel types
2019-01-16 9:15 ` [PATCH 11/17] drm/i915/color: " Jani Nikula
@ 2019-01-17 0:58 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 0:58 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 7259 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel
> types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_color.c | 40 +++++++++++++++-------------
> --
> 1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 37fd9ddf762e..299eb7858adc 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -142,7 +142,7 @@ static void ilk_load_csc_matrix(struct
> intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int i, pipe = crtc->pipe;
> - uint16_t coeffs[9] = { 0, };
> + u16 coeffs[9] = { 0, };
> bool limited_color_range = false;
>
> /*
> @@ -171,7 +171,7 @@ static void ilk_load_csc_matrix(struct
> intel_crtc_state *crtc_state)
> * hardware.
> */
> for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
> - uint64_t abs_coeff = ((1ULL << 63) - 1) &
> input[i];
> + u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
>
> /*
> * Clamp input value to min/max supported by
> @@ -233,7 +233,7 @@ static void ilk_load_csc_matrix(struct
> intel_crtc_state *crtc_state)
> I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>
> if (INTEL_GEN(dev_priv) > 6) {
> - uint16_t postoff = 0;
> + u16 postoff = 0;
>
> if (limited_color_range)
> postoff = (16 * (1 << 12) / 255) & 0x1fff;
> @@ -244,7 +244,7 @@ static void ilk_load_csc_matrix(struct
> intel_crtc_state *crtc_state)
>
> I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> } else {
> - uint32_t mode = CSC_MODE_YUV_TO_RGB;
> + u32 mode = CSC_MODE_YUV_TO_RGB;
>
> if (limited_color_range)
> mode |= CSC_BLACK_SCREEN_OFFSET;
> @@ -261,15 +261,15 @@ static void cherryview_load_csc_matrix(struct
> intel_crtc_state *crtc_state)
> struct drm_device *dev = crtc_state->base.crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> - uint32_t mode;
> + u32 mode;
>
> if (crtc_state->base.ctm) {
> struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> - uint16_t coeffs[9] = { 0, };
> + u16 coeffs[9] = { 0, };
> int i;
>
> for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
> - uint64_t abs_coeff =
> + u64 abs_coeff =
> ((1ULL << 63) - 1) & ctm->matrix[i];
>
> /* Round coefficient. */
> @@ -331,7 +331,7 @@ static void i9xx_load_luts_internal(struct
> intel_crtc_state *crtc_state,
> if (blob) {
> struct drm_color_lut *lut = blob->data;
> for (i = 0; i < 256; i++) {
> - uint32_t word =
> + u32 word =
> (drm_color_lut_extract(lut[i].red, 8)
> << 16) |
> (drm_color_lut_extract(lut[i].green, 8)
> << 8) |
> drm_color_lut_extract(lut[i].blue, 8);
> @@ -343,7 +343,7 @@ static void i9xx_load_luts_internal(struct
> intel_crtc_state *crtc_state,
> }
> } else {
> for (i = 0; i < 256; i++) {
> - uint32_t word = (i << 16) | (i << 8) | i;
> + u32 word = (i << 16) | (i << 8) | i;
>
> if (HAS_GMCH_DISPLAY(dev_priv))
> I915_WRITE(PALETTE(pipe, i), word);
> @@ -388,7 +388,7 @@ static void bdw_load_degamma_lut(struct
> intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >base.crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> - uint32_t i, lut_size = INTEL_INFO(dev_priv)-
> >color.degamma_lut_size;
> + u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>
> I915_WRITE(PREC_PAL_INDEX(pipe),
> PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
> @@ -397,7 +397,7 @@ static void bdw_load_degamma_lut(struct
> intel_crtc_state *crtc_state)
> struct drm_color_lut *lut = crtc_state-
> >base.degamma_lut->data;
>
> for (i = 0; i < lut_size; i++) {
> - uint32_t word =
> + u32 word =
> drm_color_lut_extract(lut[i].red, 10) << 20 |
> drm_color_lut_extract(lut[i].green, 10) << 10 |
> drm_color_lut_extract(lut[i].blue, 10);
> @@ -406,7 +406,7 @@ static void bdw_load_degamma_lut(struct
> intel_crtc_state *crtc_state)
> }
> } else {
> for (i = 0; i < lut_size; i++) {
> - uint32_t v = (i * ((1 << 10) - 1)) / (lut_size
> - 1);
> + u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
>
> I915_WRITE(PREC_PAL_DATA(pipe),
> (v << 20) | (v << 10) | v);
> @@ -418,7 +418,7 @@ static void bdw_load_gamma_lut(struct
> intel_crtc_state *crtc_state, u32 offset)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >base.crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> - uint32_t i, lut_size = INTEL_INFO(dev_priv)-
> >color.gamma_lut_size;
> + u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>
> WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
>
> @@ -431,7 +431,7 @@ static void bdw_load_gamma_lut(struct
> intel_crtc_state *crtc_state, u32 offset)
> struct drm_color_lut *lut = crtc_state->base.gamma_lut-
> >data;
>
> for (i = 0; i < lut_size; i++) {
> - uint32_t word =
> + u32 word =
> (drm_color_lut_extract(lut[i].red, 10) << 20) |
> (drm_color_lut_extract(lut[i].green, 10) << 10)
> |
> drm_color_lut_extract(lut[i].blue, 10);
> @@ -449,7 +449,7 @@ static void bdw_load_gamma_lut(struct
> intel_crtc_state *crtc_state, u32 offset)
> drm_color_lut_extract(lut[i].blue, 16));
> } else {
> for (i = 0; i < lut_size; i++) {
> - uint32_t v = (i * ((1 << 10) - 1)) / (lut_size
> - 1);
> + u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
>
> I915_WRITE(PREC_PAL_DATA(pipe),
> (v << 20) | (v << 10) | v);
> @@ -491,8 +491,8 @@ static void glk_load_degamma_lut(struct
> intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >base.crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> - const uint32_t lut_size = 33;
> - uint32_t i;
> + const u32 lut_size = 33;
> + u32 i;
>
> /*
> * When setting the auto-increment bit, the hardware seems to
> @@ -507,7 +507,7 @@ static void glk_load_degamma_lut(struct
> intel_crtc_state *crtc_state)
> * different values per channel, so this just loads a linear
> table.
> */
> for (i = 0; i < lut_size; i++) {
> - uint32_t v = (i * (1 << 16)) / (lut_size - 1);
> + u32 v = (i * (1 << 16)) / (lut_size - 1);
>
> I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
> }
> @@ -544,8 +544,8 @@ static void cherryview_load_luts(struct
> intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> struct drm_color_lut *lut;
> - uint32_t i, lut_size;
> - uint32_t word0, word1;
> + u32 i, lut_size;
> + u32 word0, word1;
>
> if (crtc_state_is_legacy_gamma(crtc_state)) {
> /* Turn off degamma/gamma on CGM block. */
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 12/17] drm/i915/pm: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (10 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 11/17] drm/i915/color: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 1:06 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 13/17] drm/i915/ddi: " Jani Nikula
` (10 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Minor checkpatch fixes sprinkled on top of the changed lines.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 213 ++++++++++++++++----------------
1 file changed, 105 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7613ae72df3d..8b63afa3a221 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -480,7 +480,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
int sprite0_start, sprite1_start;
switch (pipe) {
- uint32_t dsparb, dsparb2, dsparb3;
+ u32 dsparb, dsparb2, dsparb3;
case PIPE_A:
dsparb = I915_READ(DSPARB);
dsparb2 = I915_READ(DSPARB2);
@@ -513,7 +513,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- uint32_t dsparb = I915_READ(DSPARB);
+ u32 dsparb = I915_READ(DSPARB);
int size;
size = dsparb & 0x7f;
@@ -529,7 +529,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- uint32_t dsparb = I915_READ(DSPARB);
+ u32 dsparb = I915_READ(DSPARB);
int size;
size = dsparb & 0x1ff;
@@ -546,7 +546,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- uint32_t dsparb = I915_READ(DSPARB);
+ u32 dsparb = I915_READ(DSPARB);
int size;
size = dsparb & 0x7f;
@@ -667,9 +667,9 @@ static unsigned int intel_wm_method1(unsigned int pixel_rate,
unsigned int cpp,
unsigned int latency)
{
- uint64_t ret;
+ u64 ret;
- ret = (uint64_t) pixel_rate * cpp * latency;
+ ret = (u64)pixel_rate * cpp * latency;
ret = DIV_ROUND_UP_ULL(ret, 10000);
return ret;
@@ -1089,9 +1089,9 @@ static int g4x_fbc_fifo_size(int level)
}
}
-static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int level)
+static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int level)
{
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -1188,9 +1188,9 @@ static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
return dirty;
}
-static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
- uint32_t pri_val);
+static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
+ const struct intel_plane_state *pstate,
+ u32 pri_val);
static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
@@ -1598,9 +1598,9 @@ static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
}
}
-static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int level)
+static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int level)
{
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -1968,7 +1968,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
spin_lock(&dev_priv->uncore.lock);
switch (crtc->pipe) {
- uint32_t dsparb, dsparb2, dsparb3;
+ u32 dsparb, dsparb2, dsparb3;
case PIPE_A:
dsparb = I915_READ_FW(DSPARB);
dsparb2 = I915_READ_FW(DSPARB2);
@@ -2262,8 +2262,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
{
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
const struct intel_watermark_params *wm_info;
- uint32_t fwater_lo;
- uint32_t fwater_hi;
+ u32 fwater_lo;
+ u32 fwater_hi;
int cwm, srwm = 1;
int fifo_size;
int planea_wm, planeb_wm;
@@ -2406,7 +2406,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct drm_display_mode *adjusted_mode;
- uint32_t fwater_lo;
+ u32 fwater_lo;
int planea_wm;
crtc = single_enabled_crtc(dev_priv);
@@ -2455,8 +2455,7 @@ static unsigned int ilk_wm_method2(unsigned int pixel_rate,
return ret;
}
-static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
- uint8_t cpp)
+static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
{
/*
* Neither of these should be possible since this function shouldn't be
@@ -2473,22 +2472,21 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
}
struct ilk_wm_maximums {
- uint16_t pri;
- uint16_t spr;
- uint16_t cur;
- uint16_t fbc;
+ u16 pri;
+ u16 spr;
+ u16 cur;
+ u16 fbc;
};
/*
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
- uint32_t mem_value,
- bool is_lp)
+static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
+ const struct intel_plane_state *pstate,
+ u32 mem_value, bool is_lp)
{
- uint32_t method1, method2;
+ u32 method1, method2;
int cpp;
if (mem_value == 0)
@@ -2516,11 +2514,11 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
- uint32_t mem_value)
+static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
+ const struct intel_plane_state *pstate,
+ u32 mem_value)
{
- uint32_t method1, method2;
+ u32 method1, method2;
int cpp;
if (mem_value == 0)
@@ -2543,9 +2541,9 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
- uint32_t mem_value)
+static u32 ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
+ const struct intel_plane_state *pstate,
+ u32 mem_value)
{
int cpp;
@@ -2563,9 +2561,9 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
}
/* Only for WM_LP. */
-static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
- const struct intel_plane_state *pstate,
- uint32_t pri_val)
+static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
+ const struct intel_plane_state *pstate,
+ u32 pri_val)
{
int cpp;
@@ -2731,9 +2729,9 @@ static bool ilk_validate_wm_level(int level,
DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
level, result->cur_val, max->cur);
- result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
- result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
- result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
+ result->pri_val = min_t(u32, result->pri_val, max->pri);
+ result->spr_val = min_t(u32, result->spr_val, max->spr);
+ result->cur_val = min_t(u32, result->cur_val, max->cur);
result->enable = true;
}
@@ -2749,9 +2747,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
const struct intel_plane_state *curstate,
struct intel_wm_level *result)
{
- uint16_t pri_latency = dev_priv->wm.pri_latency[level];
- uint16_t spr_latency = dev_priv->wm.spr_latency[level];
- uint16_t cur_latency = dev_priv->wm.cur_latency[level];
+ u16 pri_latency = dev_priv->wm.pri_latency[level];
+ u16 spr_latency = dev_priv->wm.spr_latency[level];
+ u16 cur_latency = dev_priv->wm.cur_latency[level];
/* WM1+ latency values stored in 0.5us units */
if (level > 0) {
@@ -2775,7 +2773,7 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
result->enable = true;
}
-static uint32_t
+static u32
hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
{
const struct intel_atomic_state *intel_state =
@@ -2804,10 +2802,10 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
}
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
- uint16_t wm[8])
+ u16 wm[8])
{
if (INTEL_GEN(dev_priv) >= 9) {
- uint32_t val;
+ u32 val;
int ret, i;
int level, max_level = ilk_wm_max_level(dev_priv);
@@ -2891,7 +2889,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
wm[0] += 1;
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- uint64_t sskpd = I915_READ64(MCH_SSKPD);
+ u64 sskpd = I915_READ64(MCH_SSKPD);
wm[0] = (sskpd >> 56) & 0xFF;
if (wm[0] == 0)
@@ -2901,14 +2899,14 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
wm[3] = (sskpd >> 20) & 0x1FF;
wm[4] = (sskpd >> 32) & 0x1FF;
} else if (INTEL_GEN(dev_priv) >= 6) {
- uint32_t sskpd = I915_READ(MCH_SSKPD);
+ u32 sskpd = I915_READ(MCH_SSKPD);
wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
} else if (INTEL_GEN(dev_priv) >= 5) {
- uint32_t mltr = I915_READ(MLTR_ILK);
+ u32 mltr = I915_READ(MLTR_ILK);
/* ILK primary LP0 latency is 700 ns */
wm[0] = 7;
@@ -2920,7 +2918,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
}
static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
- uint16_t wm[5])
+ u16 wm[5])
{
/* ILK sprite LP0 latency is 1300 ns */
if (IS_GEN(dev_priv, 5))
@@ -2928,7 +2926,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
}
static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
- uint16_t wm[5])
+ u16 wm[5])
{
/* ILK cursor LP0 latency is 1300 ns */
if (IS_GEN(dev_priv, 5))
@@ -2950,7 +2948,7 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
const char *name,
- const uint16_t wm[8])
+ const u16 wm[8])
{
int level, max_level = ilk_wm_max_level(dev_priv);
@@ -2979,7 +2977,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
}
static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
- uint16_t wm[5], uint16_t min)
+ u16 wm[5], u16 min)
{
int level, max_level = ilk_wm_max_level(dev_priv);
@@ -2988,7 +2986,7 @@ static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
wm[0] = max(wm[0], min);
for (level = 1; level <= max_level; level++)
- wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
+ wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
return true;
}
@@ -3535,7 +3533,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
{
struct ilk_wm_values *previous = &dev_priv->wm.hw;
unsigned int dirty;
- uint32_t val;
+ u32 val;
dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
if (!dirty)
@@ -4033,7 +4031,7 @@ skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate)
{
struct intel_plane *plane = to_intel_plane(pstate->base.plane);
- uint32_t src_w, src_h, dst_w, dst_h;
+ u32 src_w, src_h, dst_w, dst_h;
uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
uint_fixed_16_16_t downscale_h, downscale_w;
@@ -4079,8 +4077,8 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
return pipe_downscale;
if (crtc_state->pch_pfit.enabled) {
- uint32_t src_w, src_h, dst_w, dst_h;
- uint32_t pfit_size = crtc_state->pch_pfit.size;
+ u32 src_w, src_h, dst_w, dst_h;
+ u32 pfit_size = crtc_state->pch_pfit.size;
uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
uint_fixed_16_16_t downscale_h, downscale_w;
@@ -4113,7 +4111,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
const struct drm_plane_state *pstate;
struct intel_plane_state *intel_pstate;
int crtc_clock, dotclk;
- uint32_t pipe_max_pixel_rate;
+ u32 pipe_max_pixel_rate;
uint_fixed_16_16_t pipe_downscale;
uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
@@ -4169,8 +4167,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
{
struct intel_plane *intel_plane =
to_intel_plane(intel_pstate->base.plane);
- uint32_t data_rate;
- uint32_t width = 0, height = 0;
+ u32 data_rate;
+ u32 width = 0, height = 0;
struct drm_framebuffer *fb;
u32 format;
uint_fixed_16_16_t down_scale_amount;
@@ -4313,15 +4311,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
struct skl_plane_wm *wm;
- uint16_t alloc_size, start = 0;
- uint16_t total[I915_MAX_PLANES] = {};
- uint16_t uv_total[I915_MAX_PLANES] = {};
+ u16 alloc_size, start = 0;
+ u16 total[I915_MAX_PLANES] = {};
+ u16 uv_total[I915_MAX_PLANES] = {};
u64 total_data_rate;
enum plane_id plane_id;
int num_active;
u64 plane_data_rate[I915_MAX_PLANES] = {};
u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
- uint16_t blocks = 0;
+ u16 blocks = 0;
int level;
/* Clear the partitioning for disabled planes. */
@@ -4493,10 +4491,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
* 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
*/
static uint_fixed_16_16_t
-skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
- uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
+skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
+ u8 cpp, u32 latency, u32 dbuf_block_size)
{
- uint32_t wm_intermediate_val;
+ u32 wm_intermediate_val;
uint_fixed_16_16_t ret;
if (latency == 0)
@@ -4511,12 +4509,11 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
return ret;
}
-static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
- uint32_t pipe_htotal,
- uint32_t latency,
- uint_fixed_16_16_t plane_blocks_per_line)
+static uint_fixed_16_16_t
+skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
+ uint_fixed_16_16_t plane_blocks_per_line)
{
- uint32_t wm_intermediate_val;
+ u32 wm_intermediate_val;
uint_fixed_16_16_t ret;
if (latency == 0)
@@ -4532,8 +4529,8 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
static uint_fixed_16_16_t
intel_get_linetime_us(const struct intel_crtc_state *cstate)
{
- uint32_t pixel_rate;
- uint32_t crtc_htotal;
+ u32 pixel_rate;
+ u32 crtc_htotal;
uint_fixed_16_16_t linetime_us;
if (!cstate->base.active)
@@ -4550,11 +4547,11 @@ intel_get_linetime_us(const struct intel_crtc_state *cstate)
return linetime_us;
}
-static uint32_t
+static u32
skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate)
{
- uint64_t adjusted_pixel_rate;
+ u64 adjusted_pixel_rate;
uint_fixed_16_16_t downscale_amount;
/* Shouldn't reach here on disabled planes... */
@@ -4581,7 +4578,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_plane_state *pstate = &intel_pstate->base;
const struct drm_framebuffer *fb = pstate->fb;
- uint32_t interm_pbpl;
+ u32 interm_pbpl;
struct intel_atomic_state *state =
to_intel_atomic_state(cstate->base.state);
bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
@@ -4686,10 +4683,10 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
{
struct drm_i915_private *dev_priv =
to_i915(intel_pstate->base.plane->dev);
- uint32_t latency = dev_priv->wm.skl_latency[level];
+ u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
- uint32_t res_blocks, res_lines;
+ u32 res_blocks, res_lines;
struct intel_atomic_state *state =
to_intel_atomic_state(cstate->base.state);
bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
@@ -4795,13 +4792,13 @@ skl_compute_wm_levels(const struct intel_crtc_state *cstate,
}
}
-static uint32_t
+static u32
skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
{
struct drm_atomic_state *state = cstate->base.state;
struct drm_i915_private *dev_priv = to_i915(state->dev);
uint_fixed_16_16_t linetime_us;
- uint32_t linetime_wm;
+ u32 linetime_wm;
linetime_us = intel_get_linetime_us(cstate);
@@ -4824,9 +4821,9 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
{
struct drm_device *dev = cstate->base.crtc->dev;
const struct drm_i915_private *dev_priv = to_i915(dev);
- uint16_t trans_min, trans_y_tile_min;
- const uint16_t trans_amount = 10; /* This is configurable amount */
- uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
+ u16 trans_min, trans_y_tile_min;
+ const u16 trans_amount = 10; /* This is configurable amount */
+ u16 wm0_sel_res_b, trans_offset_b, res_blocks;
/* Transition WM are not recommended by HW team for GEN9 */
if (INTEL_GEN(dev_priv) <= 9)
@@ -4855,8 +4852,8 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
if (wp->y_tiled) {
- trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
- wp->y_tile_minimum);
+ trans_y_tile_min =
+ (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
trans_offset_b;
} else {
@@ -5030,7 +5027,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
i915_reg_t reg,
const struct skl_wm_level *level)
{
- uint32_t val = 0;
+ u32 val = 0;
if (level->plane_en) {
val |= PLANE_WM_EN;
@@ -5161,12 +5158,12 @@ static int skl_update_pipe_wm(struct intel_crtc_state *cstate,
return 0;
}
-static uint32_t
+static u32
pipes_modified(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
struct intel_crtc_state *cstate;
- uint32_t i, ret = 0;
+ u32 i, ret = 0;
for_each_new_intel_crtc_in_state(state, crtc, cstate, i)
ret |= drm_crtc_mask(&crtc->base);
@@ -5267,7 +5264,7 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state, bool *changed)
const struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
- uint32_t realloc_pipes = pipes_modified(state);
+ u32 realloc_pipes = pipes_modified(state);
int ret, i;
/*
@@ -5566,7 +5563,7 @@ static void ilk_optimize_watermarks(struct intel_atomic_state *state,
mutex_unlock(&dev_priv->wm.wm_mutex);
}
-static inline void skl_wm_level_from_reg_val(uint32_t val,
+static inline void skl_wm_level_from_reg_val(u32 val,
struct skl_wm_level *level)
{
level->plane_en = val & PLANE_WM_EN;
@@ -5582,7 +5579,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
enum pipe pipe = crtc->pipe;
int level, max_level;
enum plane_id plane_id;
- uint32_t val;
+ u32 val;
max_level = ilk_wm_max_level(dev_priv);
@@ -5694,7 +5691,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
struct g4x_wm_values *wm)
{
- uint32_t tmp;
+ u32 tmp;
tmp = I915_READ(DSPFW1);
wm->sr.plane = _FW_WM(tmp, SR);
@@ -5721,7 +5718,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
struct vlv_wm_values *wm)
{
enum pipe pipe;
- uint32_t tmp;
+ u32 tmp;
for_each_pipe(dev_priv, pipe) {
tmp = I915_READ(VLV_DDL(pipe));
@@ -8505,7 +8502,7 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
{
- uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+ u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
/*
* Required for FBC
@@ -8577,7 +8574,7 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
{
int pipe;
- uint32_t val;
+ u32 val;
/*
* On Ibex Peak and Cougar Point, we need to disable clock
@@ -8612,7 +8609,7 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
{
- uint32_t tmp;
+ u32 tmp;
tmp = I915_READ(MCH_SSKPD);
if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
@@ -8622,7 +8619,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
{
- uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+ u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
@@ -8716,7 +8713,7 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
{
- uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
+ u32 reg = I915_READ(GEN7_FF_THREAD_MODE);
/*
* WaVSThreadDispatchOverride:ivb,vlv
@@ -8752,7 +8749,7 @@ static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
{
if (HAS_PCH_LPT_LP(dev_priv)) {
- uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
+ u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
@@ -8990,7 +8987,7 @@ static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
{
- uint32_t snpcr;
+ u32 snpcr;
I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
@@ -9199,7 +9196,7 @@ static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
{
- uint32_t dspclk_gate;
+ u32 dspclk_gate;
I915_WRITE(RENCLK_GATE_D1, 0);
I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@@ -9449,7 +9446,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
{
- uint32_t flags =
+ u32 flags =
I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
switch (flags) {
@@ -9472,7 +9469,7 @@ static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
{
- uint32_t flags =
+ u32 flags =
I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
switch (flags) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 12/17] drm/i915/pm: switch to kernel types
2019-01-16 9:15 ` [PATCH 12/17] drm/i915/pm: " Jani Nikula
@ 2019-01-17 1:06 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 1:06 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 25814 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch fixes sprinkled on top of the changed lines.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 213 ++++++++++++++++------------
> ----
> 1 file changed, 105 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 7613ae72df3d..8b63afa3a221 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -480,7 +480,7 @@ static void vlv_get_fifo_size(struct
> intel_crtc_state *crtc_state)
> int sprite0_start, sprite1_start;
>
> switch (pipe) {
> - uint32_t dsparb, dsparb2, dsparb3;
> + u32 dsparb, dsparb2, dsparb3;
> case PIPE_A:
> dsparb = I915_READ(DSPARB);
> dsparb2 = I915_READ(DSPARB2);
> @@ -513,7 +513,7 @@ static void vlv_get_fifo_size(struct
> intel_crtc_state *crtc_state)
> static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
> enum i9xx_plane_id i9xx_plane)
> {
> - uint32_t dsparb = I915_READ(DSPARB);
> + u32 dsparb = I915_READ(DSPARB);
> int size;
>
> size = dsparb & 0x7f;
> @@ -529,7 +529,7 @@ static int i9xx_get_fifo_size(struct
> drm_i915_private *dev_priv,
> static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
> enum i9xx_plane_id i9xx_plane)
> {
> - uint32_t dsparb = I915_READ(DSPARB);
> + u32 dsparb = I915_READ(DSPARB);
> int size;
>
> size = dsparb & 0x1ff;
> @@ -546,7 +546,7 @@ static int i830_get_fifo_size(struct
> drm_i915_private *dev_priv,
> static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
> enum i9xx_plane_id i9xx_plane)
> {
> - uint32_t dsparb = I915_READ(DSPARB);
> + u32 dsparb = I915_READ(DSPARB);
> int size;
>
> size = dsparb & 0x7f;
> @@ -667,9 +667,9 @@ static unsigned int intel_wm_method1(unsigned int
> pixel_rate,
> unsigned int cpp,
> unsigned int latency)
> {
> - uint64_t ret;
> + u64 ret;
>
> - ret = (uint64_t) pixel_rate * cpp * latency;
> + ret = (u64)pixel_rate * cpp * latency;
> ret = DIV_ROUND_UP_ULL(ret, 10000);
>
> return ret;
> @@ -1089,9 +1089,9 @@ static int g4x_fbc_fifo_size(int level)
> }
> }
>
> -static uint16_t g4x_compute_wm(const struct intel_crtc_state
> *crtc_state,
> - const struct intel_plane_state
> *plane_state,
> - int level)
> +static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + int level)
> {
> struct intel_plane *plane = to_intel_plane(plane_state-
> >base.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -1188,9 +1188,9 @@ static bool g4x_raw_fbc_wm_set(struct
> intel_crtc_state *crtc_state,
> return dirty;
> }
>
> -static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
> *cstate,
> - const struct intel_plane_state
> *pstate,
> - uint32_t pri_val);
> +static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
> + const struct intel_plane_state *pstate,
> + u32 pri_val);
>
> static bool g4x_raw_plane_wm_compute(struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state
> *plane_state)
> @@ -1598,9 +1598,9 @@ static void vlv_setup_wm_latency(struct
> drm_i915_private *dev_priv)
> }
> }
>
> -static uint16_t vlv_compute_wm_level(const struct intel_crtc_state
> *crtc_state,
> - const struct intel_plane_state
> *plane_state,
> - int level)
> +static u16 vlv_compute_wm_level(const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state
> *plane_state,
> + int level)
> {
> struct intel_plane *plane = to_intel_plane(plane_state-
> >base.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -1968,7 +1968,7 @@ static void vlv_atomic_update_fifo(struct
> intel_atomic_state *state,
> spin_lock(&dev_priv->uncore.lock);
>
> switch (crtc->pipe) {
> - uint32_t dsparb, dsparb2, dsparb3;
> + u32 dsparb, dsparb2, dsparb3;
> case PIPE_A:
> dsparb = I915_READ_FW(DSPARB);
> dsparb2 = I915_READ_FW(DSPARB2);
> @@ -2262,8 +2262,8 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(unused_crtc-
> >base.dev);
> const struct intel_watermark_params *wm_info;
> - uint32_t fwater_lo;
> - uint32_t fwater_hi;
> + u32 fwater_lo;
> + u32 fwater_hi;
> int cwm, srwm = 1;
> int fifo_size;
> int planea_wm, planeb_wm;
> @@ -2406,7 +2406,7 @@ static void i845_update_wm(struct intel_crtc
> *unused_crtc)
> struct drm_i915_private *dev_priv = to_i915(unused_crtc-
> >base.dev);
> struct intel_crtc *crtc;
> const struct drm_display_mode *adjusted_mode;
> - uint32_t fwater_lo;
> + u32 fwater_lo;
> int planea_wm;
>
> crtc = single_enabled_crtc(dev_priv);
> @@ -2455,8 +2455,7 @@ static unsigned int ilk_wm_method2(unsigned int
> pixel_rate,
> return ret;
> }
>
> -static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
> - uint8_t cpp)
> +static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
> {
> /*
> * Neither of these should be possible since this function
> shouldn't be
> @@ -2473,22 +2472,21 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val,
> uint32_t horiz_pixels,
> }
>
> struct ilk_wm_maximums {
> - uint16_t pri;
> - uint16_t spr;
> - uint16_t cur;
> - uint16_t fbc;
> + u16 pri;
> + u16 spr;
> + u16 cur;
> + u16 fbc;
> };
>
> /*
> * For both WM_PIPE and WM_LP.
> * mem_value must be in 0.1us units.
> */
> -static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
> *cstate,
> - const struct intel_plane_state
> *pstate,
> - uint32_t mem_value,
> - bool is_lp)
> +static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
> + const struct intel_plane_state *pstate,
> + u32 mem_value, bool is_lp)
> {
> - uint32_t method1, method2;
> + u32 method1, method2;
> int cpp;
>
> if (mem_value == 0)
> @@ -2516,11 +2514,11 @@ static uint32_t ilk_compute_pri_wm(const
> struct intel_crtc_state *cstate,
> * For both WM_PIPE and WM_LP.
> * mem_value must be in 0.1us units.
> */
> -static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
> *cstate,
> - const struct intel_plane_state
> *pstate,
> - uint32_t mem_value)
> +static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
> + const struct intel_plane_state *pstate,
> + u32 mem_value)
> {
> - uint32_t method1, method2;
> + u32 method1, method2;
> int cpp;
>
> if (mem_value == 0)
> @@ -2543,9 +2541,9 @@ static uint32_t ilk_compute_spr_wm(const struct
> intel_crtc_state *cstate,
> * For both WM_PIPE and WM_LP.
> * mem_value must be in 0.1us units.
> */
> -static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
> *cstate,
> - const struct intel_plane_state
> *pstate,
> - uint32_t mem_value)
> +static u32 ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
> + const struct intel_plane_state *pstate,
> + u32 mem_value)
> {
> int cpp;
>
> @@ -2563,9 +2561,9 @@ static uint32_t ilk_compute_cur_wm(const struct
> intel_crtc_state *cstate,
> }
>
> /* Only for WM_LP. */
> -static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
> *cstate,
> - const struct intel_plane_state
> *pstate,
> - uint32_t pri_val)
> +static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
> + const struct intel_plane_state *pstate,
> + u32 pri_val)
> {
> int cpp;
>
> @@ -2731,9 +2729,9 @@ static bool ilk_validate_wm_level(int level,
> DRM_DEBUG_KMS("Cursor WM%d too large %u (max
> %u)\n",
> level, result->cur_val, max-
> >cur);
>
> - result->pri_val = min_t(uint32_t, result->pri_val, max-
> >pri);
> - result->spr_val = min_t(uint32_t, result->spr_val, max-
> >spr);
> - result->cur_val = min_t(uint32_t, result->cur_val, max-
> >cur);
> + result->pri_val = min_t(u32, result->pri_val, max-
> >pri);
> + result->spr_val = min_t(u32, result->spr_val, max-
> >spr);
> + result->cur_val = min_t(u32, result->cur_val, max-
> >cur);
> result->enable = true;
> }
>
> @@ -2749,9 +2747,9 @@ static void ilk_compute_wm_level(const struct
> drm_i915_private *dev_priv,
> const struct intel_plane_state
> *curstate,
> struct intel_wm_level *result)
> {
> - uint16_t pri_latency = dev_priv->wm.pri_latency[level];
> - uint16_t spr_latency = dev_priv->wm.spr_latency[level];
> - uint16_t cur_latency = dev_priv->wm.cur_latency[level];
> + u16 pri_latency = dev_priv->wm.pri_latency[level];
> + u16 spr_latency = dev_priv->wm.spr_latency[level];
> + u16 cur_latency = dev_priv->wm.cur_latency[level];
>
> /* WM1+ latency values stored in 0.5us units */
> if (level > 0) {
> @@ -2775,7 +2773,7 @@ static void ilk_compute_wm_level(const struct
> drm_i915_private *dev_priv,
> result->enable = true;
> }
>
> -static uint32_t
> +static u32
> hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
> {
> const struct intel_atomic_state *intel_state =
> @@ -2804,10 +2802,10 @@ hsw_compute_linetime_wm(const struct
> intel_crtc_state *cstate)
> }
>
> static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> - uint16_t wm[8])
> + u16 wm[8])
> {
> if (INTEL_GEN(dev_priv) >= 9) {
> - uint32_t val;
> + u32 val;
> int ret, i;
> int level, max_level = ilk_wm_max_level(dev_priv);
>
> @@ -2891,7 +2889,7 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> wm[0] += 1;
>
> } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - uint64_t sskpd = I915_READ64(MCH_SSKPD);
> + u64 sskpd = I915_READ64(MCH_SSKPD);
>
> wm[0] = (sskpd >> 56) & 0xFF;
> if (wm[0] == 0)
> @@ -2901,14 +2899,14 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> wm[3] = (sskpd >> 20) & 0x1FF;
> wm[4] = (sskpd >> 32) & 0x1FF;
> } else if (INTEL_GEN(dev_priv) >= 6) {
> - uint32_t sskpd = I915_READ(MCH_SSKPD);
> + u32 sskpd = I915_READ(MCH_SSKPD);
>
> wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
> wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
> wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
> wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
> } else if (INTEL_GEN(dev_priv) >= 5) {
> - uint32_t mltr = I915_READ(MLTR_ILK);
> + u32 mltr = I915_READ(MLTR_ILK);
>
> /* ILK primary LP0 latency is 700 ns */
> wm[0] = 7;
> @@ -2920,7 +2918,7 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> }
>
> static void intel_fixup_spr_wm_latency(struct drm_i915_private
> *dev_priv,
> - uint16_t wm[5])
> + u16 wm[5])
> {
> /* ILK sprite LP0 latency is 1300 ns */
> if (IS_GEN(dev_priv, 5))
> @@ -2928,7 +2926,7 @@ static void intel_fixup_spr_wm_latency(struct
> drm_i915_private *dev_priv,
> }
>
> static void intel_fixup_cur_wm_latency(struct drm_i915_private
> *dev_priv,
> - uint16_t wm[5])
> + u16 wm[5])
> {
> /* ILK cursor LP0 latency is 1300 ns */
> if (IS_GEN(dev_priv, 5))
> @@ -2950,7 +2948,7 @@ int ilk_wm_max_level(const struct
> drm_i915_private *dev_priv)
>
> static void intel_print_wm_latency(struct drm_i915_private
> *dev_priv,
> const char *name,
> - const uint16_t wm[8])
> + const u16 wm[8])
> {
> int level, max_level = ilk_wm_max_level(dev_priv);
>
> @@ -2979,7 +2977,7 @@ static void intel_print_wm_latency(struct
> drm_i915_private *dev_priv,
> }
>
> static bool ilk_increase_wm_latency(struct drm_i915_private
> *dev_priv,
> - uint16_t wm[5], uint16_t min)
> + u16 wm[5], u16 min)
> {
> int level, max_level = ilk_wm_max_level(dev_priv);
>
> @@ -2988,7 +2986,7 @@ static bool ilk_increase_wm_latency(struct
> drm_i915_private *dev_priv,
>
> wm[0] = max(wm[0], min);
> for (level = 1; level <= max_level; level++)
> - wm[level] = max_t(uint16_t, wm[level],
> DIV_ROUND_UP(min, 5));
> + wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min,
> 5));
>
> return true;
> }
> @@ -3535,7 +3533,7 @@ static void ilk_write_wm_values(struct
> drm_i915_private *dev_priv,
> {
> struct ilk_wm_values *previous = &dev_priv->wm.hw;
> unsigned int dirty;
> - uint32_t val;
> + u32 val;
>
> dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
> if (!dirty)
> @@ -4033,7 +4031,7 @@ skl_plane_downscale_amount(const struct
> intel_crtc_state *cstate,
> const struct intel_plane_state *pstate)
> {
> struct intel_plane *plane = to_intel_plane(pstate->base.plane);
> - uint32_t src_w, src_h, dst_w, dst_h;
> + u32 src_w, src_h, dst_w, dst_h;
> uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
> uint_fixed_16_16_t downscale_h, downscale_w;
>
> @@ -4079,8 +4077,8 @@ skl_pipe_downscale_amount(const struct
> intel_crtc_state *crtc_state)
> return pipe_downscale;
>
> if (crtc_state->pch_pfit.enabled) {
> - uint32_t src_w, src_h, dst_w, dst_h;
> - uint32_t pfit_size = crtc_state->pch_pfit.size;
> + u32 src_w, src_h, dst_w, dst_h;
> + u32 pfit_size = crtc_state->pch_pfit.size;
> uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
> uint_fixed_16_16_t downscale_h, downscale_w;
>
> @@ -4113,7 +4111,7 @@ int skl_check_pipe_max_pixel_rate(struct
> intel_crtc *intel_crtc,
> const struct drm_plane_state *pstate;
> struct intel_plane_state *intel_pstate;
> int crtc_clock, dotclk;
> - uint32_t pipe_max_pixel_rate;
> + u32 pipe_max_pixel_rate;
> uint_fixed_16_16_t pipe_downscale;
> uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
>
> @@ -4169,8 +4167,8 @@ skl_plane_relative_data_rate(const struct
> intel_crtc_state *cstate,
> {
> struct intel_plane *intel_plane =
> to_intel_plane(intel_pstate->base.plane);
> - uint32_t data_rate;
> - uint32_t width = 0, height = 0;
> + u32 data_rate;
> + u32 width = 0, height = 0;
> struct drm_framebuffer *fb;
> u32 format;
> uint_fixed_16_16_t down_scale_amount;
> @@ -4313,15 +4311,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
> struct skl_plane_wm *wm;
> - uint16_t alloc_size, start = 0;
> - uint16_t total[I915_MAX_PLANES] = {};
> - uint16_t uv_total[I915_MAX_PLANES] = {};
> + u16 alloc_size, start = 0;
> + u16 total[I915_MAX_PLANES] = {};
> + u16 uv_total[I915_MAX_PLANES] = {};
> u64 total_data_rate;
> enum plane_id plane_id;
> int num_active;
> u64 plane_data_rate[I915_MAX_PLANES] = {};
> u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
> - uint16_t blocks = 0;
> + u16 blocks = 0;
> int level;
>
> /* Clear the partitioning for disabled planes. */
> @@ -4493,10 +4491,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
> * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
> */
> static uint_fixed_16_16_t
> -skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t
> pixel_rate,
> - uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
> +skl_wm_method1(const struct drm_i915_private *dev_priv, u32
> pixel_rate,
> + u8 cpp, u32 latency, u32 dbuf_block_size)
> {
> - uint32_t wm_intermediate_val;
> + u32 wm_intermediate_val;
> uint_fixed_16_16_t ret;
>
> if (latency == 0)
> @@ -4511,12 +4509,11 @@ skl_wm_method1(const struct drm_i915_private
> *dev_priv, uint32_t pixel_rate,
> return ret;
> }
>
> -static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
> - uint32_t pipe_htotal,
> - uint32_t latency,
> - uint_fixed_16_16_t plane_blocks_per_line)
> +static uint_fixed_16_16_t
> +skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
> + uint_fixed_16_16_t plane_blocks_per_line)
> {
> - uint32_t wm_intermediate_val;
> + u32 wm_intermediate_val;
> uint_fixed_16_16_t ret;
>
> if (latency == 0)
> @@ -4532,8 +4529,8 @@ static uint_fixed_16_16_t
> skl_wm_method2(uint32_t pixel_rate,
> static uint_fixed_16_16_t
> intel_get_linetime_us(const struct intel_crtc_state *cstate)
> {
> - uint32_t pixel_rate;
> - uint32_t crtc_htotal;
> + u32 pixel_rate;
> + u32 crtc_htotal;
> uint_fixed_16_16_t linetime_us;
>
> if (!cstate->base.active)
> @@ -4550,11 +4547,11 @@ intel_get_linetime_us(const struct
> intel_crtc_state *cstate)
> return linetime_us;
> }
>
> -static uint32_t
> +static u32
> skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
> const struct intel_plane_state *pstate)
> {
> - uint64_t adjusted_pixel_rate;
> + u64 adjusted_pixel_rate;
> uint_fixed_16_16_t downscale_amount;
>
> /* Shouldn't reach here on disabled planes... */
> @@ -4581,7 +4578,7 @@ skl_compute_plane_wm_params(const struct
> intel_crtc_state *cstate,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_plane_state *pstate = &intel_pstate->base;
> const struct drm_framebuffer *fb = pstate->fb;
> - uint32_t interm_pbpl;
> + u32 interm_pbpl;
> struct intel_atomic_state *state =
> to_intel_atomic_state(cstate->base.state);
> bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
> @@ -4686,10 +4683,10 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *cstate,
> {
> struct drm_i915_private *dev_priv =
> to_i915(intel_pstate->base.plane->dev);
> - uint32_t latency = dev_priv->wm.skl_latency[level];
> + u32 latency = dev_priv->wm.skl_latency[level];
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> - uint32_t res_blocks, res_lines;
> + u32 res_blocks, res_lines;
> struct intel_atomic_state *state =
> to_intel_atomic_state(cstate->base.state);
> bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
> @@ -4795,13 +4792,13 @@ skl_compute_wm_levels(const struct
> intel_crtc_state *cstate,
> }
> }
>
> -static uint32_t
> +static u32
> skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
> {
> struct drm_atomic_state *state = cstate->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->dev);
> uint_fixed_16_16_t linetime_us;
> - uint32_t linetime_wm;
> + u32 linetime_wm;
>
> linetime_us = intel_get_linetime_us(cstate);
>
> @@ -4824,9 +4821,9 @@ static void skl_compute_transition_wm(const
> struct intel_crtc_state *cstate,
> {
> struct drm_device *dev = cstate->base.crtc->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> - uint16_t trans_min, trans_y_tile_min;
> - const uint16_t trans_amount = 10; /* This is configurable
> amount */
> - uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
> + u16 trans_min, trans_y_tile_min;
> + const u16 trans_amount = 10; /* This is configurable amount */
> + u16 wm0_sel_res_b, trans_offset_b, res_blocks;
>
> /* Transition WM are not recommended by HW team for GEN9 */
> if (INTEL_GEN(dev_priv) <= 9)
> @@ -4855,8 +4852,8 @@ static void skl_compute_transition_wm(const
> struct intel_crtc_state *cstate,
> wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
>
> if (wp->y_tiled) {
> - trans_y_tile_min = (uint16_t)
> mul_round_up_u32_fixed16(2,
> - wp-
> >y_tile_minimum);
> + trans_y_tile_min =
> + (u16)mul_round_up_u32_fixed16(2, wp-
> >y_tile_minimum);
> res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
> trans_offset_b;
> } else {
> @@ -5030,7 +5027,7 @@ static void skl_write_wm_level(struct
> drm_i915_private *dev_priv,
> i915_reg_t reg,
> const struct skl_wm_level *level)
> {
> - uint32_t val = 0;
> + u32 val = 0;
>
> if (level->plane_en) {
> val |= PLANE_WM_EN;
> @@ -5161,12 +5158,12 @@ static int skl_update_pipe_wm(struct
> intel_crtc_state *cstate,
> return 0;
> }
>
> -static uint32_t
> +static u32
> pipes_modified(struct intel_atomic_state *state)
> {
> struct intel_crtc *crtc;
> struct intel_crtc_state *cstate;
> - uint32_t i, ret = 0;
> + u32 i, ret = 0;
>
> for_each_new_intel_crtc_in_state(state, crtc, cstate, i)
> ret |= drm_crtc_mask(&crtc->base);
> @@ -5267,7 +5264,7 @@ skl_ddb_add_affected_pipes(struct
> intel_atomic_state *state, bool *changed)
> const struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> - uint32_t realloc_pipes = pipes_modified(state);
> + u32 realloc_pipes = pipes_modified(state);
> int ret, i;
>
> /*
> @@ -5566,7 +5563,7 @@ static void ilk_optimize_watermarks(struct
> intel_atomic_state *state,
> mutex_unlock(&dev_priv->wm.wm_mutex);
> }
>
> -static inline void skl_wm_level_from_reg_val(uint32_t val,
> +static inline void skl_wm_level_from_reg_val(u32 val,
> struct skl_wm_level
> *level)
> {
> level->plane_en = val & PLANE_WM_EN;
> @@ -5582,7 +5579,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc
> *crtc,
> enum pipe pipe = crtc->pipe;
> int level, max_level;
> enum plane_id plane_id;
> - uint32_t val;
> + u32 val;
>
> max_level = ilk_wm_max_level(dev_priv);
>
> @@ -5694,7 +5691,7 @@ static void ilk_pipe_wm_get_hw_state(struct
> intel_crtc *crtc)
> static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
> struct g4x_wm_values *wm)
> {
> - uint32_t tmp;
> + u32 tmp;
>
> tmp = I915_READ(DSPFW1);
> wm->sr.plane = _FW_WM(tmp, SR);
> @@ -5721,7 +5718,7 @@ static void vlv_read_wm_values(struct
> drm_i915_private *dev_priv,
> struct vlv_wm_values *wm)
> {
> enum pipe pipe;
> - uint32_t tmp;
> + u32 tmp;
>
> for_each_pipe(dev_priv, pipe) {
> tmp = I915_READ(VLV_DDL(pipe));
> @@ -8505,7 +8502,7 @@ static void g4x_disable_trickle_feed(struct
> drm_i915_private *dev_priv)
>
> static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> - uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> + u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> /*
> * Required for FBC
> @@ -8577,7 +8574,7 @@ static void ilk_init_clock_gating(struct
> drm_i915_private *dev_priv)
> static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> int pipe;
> - uint32_t val;
> + u32 val;
>
> /*
> * On Ibex Peak and Cougar Point, we need to disable clock
> @@ -8612,7 +8609,7 @@ static void cpt_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
> {
> - uint32_t tmp;
> + u32 tmp;
>
> tmp = I915_READ(MCH_SSKPD);
> if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
> @@ -8622,7 +8619,7 @@ static void gen6_check_mch_setup(struct
> drm_i915_private *dev_priv)
>
> static void gen6_init_clock_gating(struct drm_i915_private
> *dev_priv)
> {
> - uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> + u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>
> @@ -8716,7 +8713,7 @@ static void gen6_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
> *dev_priv)
> {
> - uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
> + u32 reg = I915_READ(GEN7_FF_THREAD_MODE);
>
> /*
> * WaVSThreadDispatchOverride:ivb,vlv
> @@ -8752,7 +8749,7 @@ static void lpt_init_clock_gating(struct
> drm_i915_private *dev_priv)
> static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
> {
> if (HAS_PCH_LPT_LP(dev_priv)) {
> - uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
> + u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
>
> val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> @@ -8990,7 +8987,7 @@ static void hsw_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> - uint32_t snpcr;
> + u32 snpcr;
>
> I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>
> @@ -9199,7 +9196,7 @@ static void chv_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> - uint32_t dspclk_gate;
> + u32 dspclk_gate;
>
> I915_WRITE(RENCLK_GATE_D1, 0);
> I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> @@ -9449,7 +9446,7 @@ void intel_init_pm(struct drm_i915_private
> *dev_priv)
>
> static inline int gen6_check_mailbox_status(struct drm_i915_private
> *dev_priv)
> {
> - uint32_t flags =
> + u32 flags =
> I915_READ_FW(GEN6_PCODE_MAILBOX) &
> GEN6_PCODE_ERROR_MASK;
>
> switch (flags) {
> @@ -9472,7 +9469,7 @@ static inline int
> gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
>
> static inline int gen7_check_mailbox_status(struct drm_i915_private
> *dev_priv)
> {
> - uint32_t flags =
> + u32 flags =
> I915_READ_FW(GEN6_PCODE_MAILBOX) &
> GEN6_PCODE_ERROR_MASK;
>
> switch (flags) {
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 13/17] drm/i915/ddi: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (11 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 12/17] drm/i915/pm: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 1:07 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 14/17] drm/i915/csr: " Jani Nikula
` (9 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 52 ++++++++++++++++----------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ce44744a5f9d..b0bb8dfc2ed5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -974,7 +974,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
}
-static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
{
switch (pll->info->id) {
case DPLL_ID_WRPLL1:
@@ -995,8 +995,8 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
}
}
-static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static u32 icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
int clock = crtc_state->port_clock;
@@ -1243,8 +1243,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
enum intel_dpll_id pll_id)
{
i915_reg_t cfgcr1_reg, cfgcr2_reg;
- uint32_t cfgcr1_val, cfgcr2_val;
- uint32_t p0, p1, p2, dco_freq;
+ u32 cfgcr1_val, cfgcr2_val;
+ u32 p0, p1, p2, dco_freq;
cfgcr1_reg = DPLL_CFGCR1(pll_id);
cfgcr2_reg = DPLL_CFGCR2(pll_id);
@@ -1305,8 +1305,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
enum intel_dpll_id pll_id)
{
- uint32_t cfgcr0, cfgcr1;
- uint32_t p0, p1, p2, dco_freq, ref_clock;
+ u32 cfgcr0, cfgcr1;
+ u32 p0, p1, p2, dco_freq, ref_clock;
if (INTEL_GEN(dev_priv) >= 11) {
cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
@@ -1471,7 +1471,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
int link_clock = 0;
- uint32_t pll_id;
+ u32 pll_id;
pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
if (intel_port_is_combophy(dev_priv, port)) {
@@ -1496,7 +1496,7 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int link_clock = 0;
- uint32_t cfgcr0;
+ u32 cfgcr0;
enum intel_dpll_id pll_id;
pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
@@ -1550,7 +1550,7 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int link_clock = 0;
- uint32_t dpll_ctl1;
+ u32 dpll_ctl1;
enum intel_dpll_id pll_id;
pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
@@ -1739,7 +1739,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- uint32_t temp;
+ u32 temp;
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (state == true)
@@ -1757,7 +1757,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
- uint32_t temp;
+ u32 temp;
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
@@ -1841,7 +1841,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
- uint32_t val = I915_READ(reg);
+ u32 val = I915_READ(reg);
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
val |= TRANS_DDI_PORT_NONE;
@@ -1863,7 +1863,7 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
intel_wakeref_t wakeref;
enum pipe pipe = 0;
int ret = 0;
- uint32_t tmp;
+ u32 tmp;
wakeref = intel_display_power_get_if_enabled(dev_priv,
intel_encoder->power_domain);
@@ -1896,7 +1896,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
enum transcoder cpu_transcoder;
intel_wakeref_t wakeref;
enum pipe pipe = 0;
- uint32_t tmp;
+ u32 tmp;
bool ret;
wakeref = intel_display_power_get_if_enabled(dev_priv,
@@ -2132,7 +2132,7 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
}
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
- enum port port, uint8_t iboost)
+ enum port port, u8 iboost)
{
u32 tmp;
@@ -2151,7 +2151,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
- uint8_t iboost;
+ u8 iboost;
if (type == INTEL_OUTPUT_HDMI)
iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
@@ -2665,7 +2665,7 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
}
-static uint32_t translate_signal_level(int signal_levels)
+static u32 translate_signal_level(int signal_levels)
{
int i;
@@ -2680,9 +2680,9 @@ static uint32_t translate_signal_level(int signal_levels)
return 0;
}
-static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
+static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
{
- uint8_t train_set = intel_dp->train_set[0];
+ u8 train_set = intel_dp->train_set[0];
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -2707,7 +2707,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
return 0;
}
-uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+u32 ddi_signal_levels(struct intel_dp *intel_dp)
{
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
@@ -2721,8 +2721,8 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
}
static inline
-uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
- enum port port)
+u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
+ enum port port)
{
if (intel_port_is_combophy(dev_priv, port)) {
return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
@@ -2857,7 +2857,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
- uint32_t val;
+ u32 val;
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
if (WARN_ON(!pll))
@@ -3356,7 +3356,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
const struct drm_connector_state *old_conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- uint32_t val;
+ u32 val;
/*
* Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
@@ -3644,7 +3644,7 @@ void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
enum port port = intel_dig_port->base.port;
- uint32_t val;
+ u32 val;
bool wait = false;
if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 13/17] drm/i915/ddi: switch to kernel types
2019-01-16 9:15 ` [PATCH 13/17] drm/i915/ddi: " Jani Nikula
@ 2019-01-17 1:07 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 1:07 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 8749 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 52 ++++++++++++++++------------
> ----
> 1 file changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index ce44744a5f9d..b0bb8dfc2ed5 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -974,7 +974,7 @@ static void intel_wait_ddi_buf_idle(struct
> drm_i915_private *dev_priv,
> DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n",
> port_name(port));
> }
>
> -static uint32_t hsw_pll_to_ddi_pll_sel(const struct
> intel_shared_dpll *pll)
> +static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll
> *pll)
> {
> switch (pll->info->id) {
> case DPLL_ID_WRPLL1:
> @@ -995,8 +995,8 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const
> struct intel_shared_dpll *pll)
> }
> }
>
> -static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder
> *encoder,
> - const struct intel_crtc_state
> *crtc_state)
> +static u32 icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> + const struct intel_crtc_state
> *crtc_state)
> {
> const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> int clock = crtc_state->port_clock;
> @@ -1243,8 +1243,8 @@ static int skl_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
> enum intel_dpll_id pll_id)
> {
> i915_reg_t cfgcr1_reg, cfgcr2_reg;
> - uint32_t cfgcr1_val, cfgcr2_val;
> - uint32_t p0, p1, p2, dco_freq;
> + u32 cfgcr1_val, cfgcr2_val;
> + u32 p0, p1, p2, dco_freq;
>
> cfgcr1_reg = DPLL_CFGCR1(pll_id);
> cfgcr2_reg = DPLL_CFGCR2(pll_id);
> @@ -1305,8 +1305,8 @@ static int skl_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> enum intel_dpll_id pll_id)
> {
> - uint32_t cfgcr0, cfgcr1;
> - uint32_t p0, p1, p2, dco_freq, ref_clock;
> + u32 cfgcr0, cfgcr1;
> + u32 p0, p1, p2, dco_freq, ref_clock;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> @@ -1471,7 +1471,7 @@ static void icl_ddi_clock_get(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> int link_clock = 0;
> - uint32_t pll_id;
> + u32 pll_id;
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> if (intel_port_is_combophy(dev_priv, port)) {
> @@ -1496,7 +1496,7 @@ static void cnl_ddi_clock_get(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> int link_clock = 0;
> - uint32_t cfgcr0;
> + u32 cfgcr0;
> enum intel_dpll_id pll_id;
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> @@ -1550,7 +1550,7 @@ static void skl_ddi_clock_get(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> int link_clock = 0;
> - uint32_t dpll_ctl1;
> + u32 dpll_ctl1;
> enum intel_dpll_id pll_id;
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> @@ -1739,7 +1739,7 @@ void intel_ddi_set_vc_payload_alloc(const
> struct intel_crtc_state *crtc_state,
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - uint32_t temp;
> + u32 temp;
>
> temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (state == true)
> @@ -1757,7 +1757,7 @@ void intel_ddi_enable_transcoder_func(const
> struct intel_crtc_state *crtc_state)
> enum pipe pipe = crtc->pipe;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> enum port port = encoder->port;
> - uint32_t temp;
> + u32 temp;
>
> /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode
> */
> temp = TRANS_DDI_FUNC_ENABLE;
> @@ -1841,7 +1841,7 @@ void intel_ddi_disable_transcoder_func(const
> struct intel_crtc_state *crtc_state
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> - uint32_t val = I915_READ(reg);
> + u32 val = I915_READ(reg);
>
> val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> val |= TRANS_DDI_PORT_NONE;
> @@ -1863,7 +1863,7 @@ int intel_ddi_toggle_hdcp_signalling(struct
> intel_encoder *intel_encoder,
> intel_wakeref_t wakeref;
> enum pipe pipe = 0;
> int ret = 0;
> - uint32_t tmp;
> + u32 tmp;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> intel_encoder-
> >power_domain);
> @@ -1896,7 +1896,7 @@ bool intel_ddi_connector_get_hw_state(struct
> intel_connector *intel_connector)
> enum transcoder cpu_transcoder;
> intel_wakeref_t wakeref;
> enum pipe pipe = 0;
> - uint32_t tmp;
> + u32 tmp;
> bool ret;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> @@ -2132,7 +2132,7 @@ void intel_ddi_disable_pipe_clock(const struct
> intel_crtc_state *crtc_state)
> }
>
> static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
> - enum port port, uint8_t iboost)
> + enum port port, u8 iboost)
> {
> u32 tmp;
>
> @@ -2151,7 +2151,7 @@ static void skl_ddi_set_iboost(struct
> intel_encoder *encoder,
> struct intel_digital_port *intel_dig_port =
> enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> - uint8_t iboost;
> + u8 iboost;
>
> if (type == INTEL_OUTPUT_HDMI)
> iboost = dev_priv-
> >vbt.ddi_port_info[port].hdmi_boost_level;
> @@ -2665,7 +2665,7 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> icl_mg_phy_ddi_vswing_sequence(encoder, link_clock,
> level);
> }
>
> -static uint32_t translate_signal_level(int signal_levels)
> +static u32 translate_signal_level(int signal_levels)
> {
> int i;
>
> @@ -2680,9 +2680,9 @@ static uint32_t translate_signal_level(int
> signal_levels)
> return 0;
> }
>
> -static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
> +static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
> {
> - uint8_t train_set = intel_dp->train_set[0];
> + u8 train_set = intel_dp->train_set[0];
> int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> DP_TRAIN_PRE_EMPHASIS_MASK);
>
> @@ -2707,7 +2707,7 @@ u32 bxt_signal_levels(struct intel_dp
> *intel_dp)
> return 0;
> }
>
> -uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +u32 ddi_signal_levels(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dport-
> >base.base.dev);
> @@ -2721,8 +2721,8 @@ uint32_t ddi_signal_levels(struct intel_dp
> *intel_dp)
> }
>
> static inline
> -uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private
> *dev_priv,
> - enum port port)
> +u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> + enum port port)
> {
> if (intel_port_is_combophy(dev_priv, port)) {
> return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> @@ -2857,7 +2857,7 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> - uint32_t val;
> + u32 val;
> const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>
> if (WARN_ON(!pll))
> @@ -3356,7 +3356,7 @@ void intel_ddi_fdi_post_disable(struct
> intel_encoder *encoder,
> const struct drm_connector_state
> *old_conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - uint32_t val;
> + u32 val;
>
> /*
> * Bspec lists this as both step 13 (before DDI_BUF_CTL
> disable)
> @@ -3644,7 +3644,7 @@ void intel_ddi_prepare_link_retrain(struct
> intel_dp *intel_dp)
> struct drm_i915_private *dev_priv =
> to_i915(intel_dig_port->base.base.dev);
> enum port port = intel_dig_port->base.port;
> - uint32_t val;
> + u32 val;
> bool wait = false;
>
> if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 14/17] drm/i915/csr: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (12 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 13/17] drm/i915/ddi: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-16 17:03 ` Ville Syrjälä
2019-01-17 1:11 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 15/17] drm/i915/display: " Jani Nikula
` (8 subsequent siblings)
22 siblings, 2 replies; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Minor checkpatch fixes sprinkled on top of the changed lines.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_csr.c | 68 ++++++++++++++++----------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ea5fb64d33dd..2b25cccdae16 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -70,50 +70,50 @@ MODULE_FIRMWARE(BXT_CSR_PATH);
struct intel_css_header {
/* 0x09 for DMC */
- uint32_t module_type;
+ u32 module_type;
/* Includes the DMC specific header in dwords */
- uint32_t header_len;
+ u32 header_len;
/* always value would be 0x10000 */
- uint32_t header_ver;
+ u32 header_ver;
/* Not used */
- uint32_t module_id;
+ u32 module_id;
/* Not used */
- uint32_t module_vendor;
+ u32 module_vendor;
/* in YYYYMMDD format */
- uint32_t date;
+ u32 date;
/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
- uint32_t size;
+ u32 size;
/* Not used */
- uint32_t key_size;
+ u32 key_size;
/* Not used */
- uint32_t modulus_size;
+ u32 modulus_size;
/* Not used */
- uint32_t exponent_size;
+ u32 exponent_size;
/* Not used */
- uint32_t reserved1[12];
+ u32 reserved1[12];
/* Major Minor */
- uint32_t version;
+ u32 version;
/* Not used */
- uint32_t reserved2[8];
+ u32 reserved2[8];
/* Not used */
- uint32_t kernel_header_info;
+ u32 kernel_header_info;
} __packed;
struct intel_fw_info {
- uint16_t reserved1;
+ u16 reserved1;
/* Stepping (A, B, C, ..., *). * is a wildcard */
char stepping;
@@ -121,8 +121,8 @@ struct intel_fw_info {
/* Sub-stepping (0, 1, ..., *). * is a wildcard */
char substepping;
- uint32_t offset;
- uint32_t reserved2;
+ u32 offset;
+ u32 reserved2;
} __packed;
struct intel_package_header {
@@ -135,14 +135,14 @@ struct intel_package_header {
unsigned char reserved[10];
/* Number of valid entries in the FWInfo array below */
- uint32_t num_entries;
+ u32 num_entries;
struct intel_fw_info fw_info[20];
} __packed;
struct intel_dmc_header {
/* always value would be 0x40403E3E */
- uint32_t signature;
+ u32 signature;
/* DMC binary header length */
unsigned char header_len;
@@ -151,30 +151,30 @@ struct intel_dmc_header {
unsigned char header_ver;
/* Reserved */
- uint16_t dmcc_ver;
+ u16 dmcc_ver;
/* Major, Minor */
- uint32_t project;
+ u32 project;
/* Firmware program size (excluding header) in dwords */
- uint32_t fw_size;
+ u32 fw_size;
/* Major Minor version */
- uint32_t fw_version;
+ u32 fw_version;
/* Number of valid MMIO cycles present. */
- uint32_t mmio_count;
+ u32 mmio_count;
/* MMIO address */
- uint32_t mmioaddr[8];
+ u32 mmioaddr[8];
/* MMIO data */
- uint32_t mmiodata[8];
+ u32 mmiodata[8];
/* FW filename */
unsigned char dfile[32];
- uint32_t reserved1[2];
+ u32 reserved1[2];
} __packed;
struct stepping_info {
@@ -230,7 +230,7 @@ intel_get_stepping_info(struct drm_i915_private *dev_priv)
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
{
- uint32_t val, mask;
+ u32 val, mask;
mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
@@ -257,7 +257,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
void intel_csr_load_program(struct drm_i915_private *dev_priv)
{
u32 *payload = dev_priv->csr.dmc_payload;
- uint32_t i, fw_size;
+ u32 i, fw_size;
if (!HAS_CSR(dev_priv)) {
DRM_ERROR("No CSR support available for this platform\n");
@@ -289,17 +289,17 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
gen9_set_dc_state_debugmask(dev_priv);
}
-static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
- const struct firmware *fw)
+static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
+ const struct firmware *fw)
{
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header *dmc_header;
struct intel_csr *csr = &dev_priv->csr;
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
- uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
- uint32_t i;
- uint32_t *dmc_payload;
+ u32 dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
+ u32 i;
+ u32 *dmc_payload;
if (!fw)
return NULL;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 14/17] drm/i915/csr: switch to kernel types
2019-01-16 9:15 ` [PATCH 14/17] drm/i915/csr: " Jani Nikula
@ 2019-01-16 17:03 ` Ville Syrjälä
2019-01-17 1:11 ` Souza, Jose
1 sibling, 0 replies; 46+ messages in thread
From: Ville Syrjälä @ 2019-01-16 17:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Jan 16, 2019 at 11:15:32AM +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch fixes sprinkled on top of the changed lines.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 68 ++++++++++++++++----------------
> 1 file changed, 34 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index ea5fb64d33dd..2b25cccdae16 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -70,50 +70,50 @@ MODULE_FIRMWARE(BXT_CSR_PATH);
>
> struct intel_css_header {
> /* 0x09 for DMC */
> - uint32_t module_type;
> + u32 module_type;
>
> /* Includes the DMC specific header in dwords */
> - uint32_t header_len;
> + u32 header_len;
>
> /* always value would be 0x10000 */
> - uint32_t header_ver;
> + u32 header_ver;
>
> /* Not used */
> - uint32_t module_id;
> + u32 module_id;
>
> /* Not used */
> - uint32_t module_vendor;
> + u32 module_vendor;
>
> /* in YYYYMMDD format */
> - uint32_t date;
> + u32 date;
>
> /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
> - uint32_t size;
> + u32 size;
>
> /* Not used */
> - uint32_t key_size;
> + u32 key_size;
>
> /* Not used */
> - uint32_t modulus_size;
> + u32 modulus_size;
>
> /* Not used */
> - uint32_t exponent_size;
> + u32 exponent_size;
>
> /* Not used */
> - uint32_t reserved1[12];
> + u32 reserved1[12];
>
> /* Major Minor */
> - uint32_t version;
> + u32 version;
>
> /* Not used */
> - uint32_t reserved2[8];
> + u32 reserved2[8];
>
> /* Not used */
> - uint32_t kernel_header_info;
> + u32 kernel_header_info;
> } __packed;
>
> struct intel_fw_info {
> - uint16_t reserved1;
> + u16 reserved1;
>
> /* Stepping (A, B, C, ..., *). * is a wildcard */
> char stepping;
> @@ -121,8 +121,8 @@ struct intel_fw_info {
> /* Sub-stepping (0, 1, ..., *). * is a wildcard */
> char substepping;
>
> - uint32_t offset;
> - uint32_t reserved2;
> + u32 offset;
> + u32 reserved2;
> } __packed;
>
> struct intel_package_header {
> @@ -135,14 +135,14 @@ struct intel_package_header {
> unsigned char reserved[10];
>
> /* Number of valid entries in the FWInfo array below */
> - uint32_t num_entries;
> + u32 num_entries;
>
> struct intel_fw_info fw_info[20];
> } __packed;
>
> struct intel_dmc_header {
> /* always value would be 0x40403E3E */
> - uint32_t signature;
> + u32 signature;
>
> /* DMC binary header length */
> unsigned char header_len;
> @@ -151,30 +151,30 @@ struct intel_dmc_header {
> unsigned char header_ver;
>
> /* Reserved */
> - uint16_t dmcc_ver;
> + u16 dmcc_ver;
>
> /* Major, Minor */
> - uint32_t project;
> + u32 project;
>
> /* Firmware program size (excluding header) in dwords */
> - uint32_t fw_size;
> + u32 fw_size;
Some odd looking tabs here.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH 14/17] drm/i915/csr: switch to kernel types
2019-01-16 9:15 ` [PATCH 14/17] drm/i915/csr: " Jani Nikula
2019-01-16 17:03 ` Ville Syrjälä
@ 2019-01-17 1:11 ` Souza, Jose
1 sibling, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 1:11 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 5292 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch fixes sprinkled on top of the changed lines.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 68 ++++++++++++++++------------
> ----
> 1 file changed, 34 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index ea5fb64d33dd..2b25cccdae16 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -70,50 +70,50 @@ MODULE_FIRMWARE(BXT_CSR_PATH);
>
> struct intel_css_header {
> /* 0x09 for DMC */
> - uint32_t module_type;
> + u32 module_type;
>
> /* Includes the DMC specific header in dwords */
> - uint32_t header_len;
> + u32 header_len;
>
> /* always value would be 0x10000 */
> - uint32_t header_ver;
> + u32 header_ver;
>
> /* Not used */
> - uint32_t module_id;
> + u32 module_id;
>
> /* Not used */
> - uint32_t module_vendor;
> + u32 module_vendor;
>
> /* in YYYYMMDD format */
> - uint32_t date;
> + u32 date;
>
> /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc
> FWsLen)/4 */
> - uint32_t size;
> + u32 size;
>
> /* Not used */
> - uint32_t key_size;
> + u32 key_size;
>
> /* Not used */
> - uint32_t modulus_size;
> + u32 modulus_size;
>
> /* Not used */
> - uint32_t exponent_size;
> + u32 exponent_size;
>
> /* Not used */
> - uint32_t reserved1[12];
> + u32 reserved1[12];
>
> /* Major Minor */
> - uint32_t version;
> + u32 version;
>
> /* Not used */
> - uint32_t reserved2[8];
> + u32 reserved2[8];
>
> /* Not used */
> - uint32_t kernel_header_info;
> + u32 kernel_header_info;
> } __packed;
>
> struct intel_fw_info {
> - uint16_t reserved1;
> + u16 reserved1;
>
> /* Stepping (A, B, C, ..., *). * is a wildcard */
> char stepping;
> @@ -121,8 +121,8 @@ struct intel_fw_info {
> /* Sub-stepping (0, 1, ..., *). * is a wildcard */
> char substepping;
>
> - uint32_t offset;
> - uint32_t reserved2;
> + u32 offset;
> + u32 reserved2;
> } __packed;
>
> struct intel_package_header {
> @@ -135,14 +135,14 @@ struct intel_package_header {
> unsigned char reserved[10];
>
> /* Number of valid entries in the FWInfo array below */
> - uint32_t num_entries;
> + u32 num_entries;
>
> struct intel_fw_info fw_info[20];
> } __packed;
>
> struct intel_dmc_header {
> /* always value would be 0x40403E3E */
> - uint32_t signature;
> + u32 signature;
>
> /* DMC binary header length */
> unsigned char header_len;
> @@ -151,30 +151,30 @@ struct intel_dmc_header {
> unsigned char header_ver;
>
> /* Reserved */
> - uint16_t dmcc_ver;
> + u16 dmcc_ver;
>
> /* Major, Minor */
> - uint32_t project;
> + u32 project;
>
> /* Firmware program size (excluding header) in dwords */
> - uint32_t fw_size;
> + u32 fw_size;
While at it, why not drop this taps as you did in other files?
Anyways:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> /* Major Minor version */
> - uint32_t fw_version;
> + u32 fw_version;
>
> /* Number of valid MMIO cycles present. */
> - uint32_t mmio_count;
> + u32 mmio_count;
>
> /* MMIO address */
> - uint32_t mmioaddr[8];
> + u32 mmioaddr[8];
>
> /* MMIO data */
> - uint32_t mmiodata[8];
> + u32 mmiodata[8];
>
> /* FW filename */
> unsigned char dfile[32];
>
> - uint32_t reserved1[2];
> + u32 reserved1[2];
> } __packed;
>
> struct stepping_info {
> @@ -230,7 +230,7 @@ intel_get_stepping_info(struct drm_i915_private
> *dev_priv)
>
> static void gen9_set_dc_state_debugmask(struct drm_i915_private
> *dev_priv)
> {
> - uint32_t val, mask;
> + u32 val, mask;
>
> mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
>
> @@ -257,7 +257,7 @@ static void gen9_set_dc_state_debugmask(struct
> drm_i915_private *dev_priv)
> void intel_csr_load_program(struct drm_i915_private *dev_priv)
> {
> u32 *payload = dev_priv->csr.dmc_payload;
> - uint32_t i, fw_size;
> + u32 i, fw_size;
>
> if (!HAS_CSR(dev_priv)) {
> DRM_ERROR("No CSR support available for this
> platform\n");
> @@ -289,17 +289,17 @@ void intel_csr_load_program(struct
> drm_i915_private *dev_priv)
> gen9_set_dc_state_debugmask(dev_priv);
> }
>
> -static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
> - const struct firmware *fw)
> +static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
> + const struct firmware *fw)
> {
> struct intel_css_header *css_header;
> struct intel_package_header *package_header;
> struct intel_dmc_header *dmc_header;
> struct intel_csr *csr = &dev_priv->csr;
> const struct stepping_info *si =
> intel_get_stepping_info(dev_priv);
> - uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0,
> nbytes;
> - uint32_t i;
> - uint32_t *dmc_payload;
> + u32 dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
> + u32 i;
> + u32 *dmc_payload;
>
> if (!fw)
> return NULL;
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 15/17] drm/i915/display: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (13 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 14/17] drm/i915/csr: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 1:14 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 16/17] drm/i915/i915_drv.h: " Jani Nikula
` (7 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 104 +++++++++++++--------------
1 file changed, 52 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af164d712e9e..b3d6ee7eee0e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -49,7 +49,7 @@
#include <linux/reservation.h>
/* Primary plane formats for gen <= 3 */
-static const uint32_t i8xx_primary_formats[] = {
+static const u32 i8xx_primary_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB1555,
@@ -57,7 +57,7 @@ static const uint32_t i8xx_primary_formats[] = {
};
/* Primary plane formats for gen >= 4 */
-static const uint32_t i965_primary_formats[] = {
+static const u32 i965_primary_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888,
@@ -66,18 +66,18 @@ static const uint32_t i965_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
-static const uint64_t i9xx_format_modifiers[] = {
+static const u64 i9xx_format_modifiers[] = {
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_INVALID
};
/* Cursor formats */
-static const uint32_t intel_cursor_formats[] = {
+static const u32 intel_cursor_formats[] = {
DRM_FORMAT_ARGB8888,
};
-static const uint64_t cursor_format_modifiers[] = {
+static const u64 cursor_format_modifiers[] = {
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_INVALID
};
@@ -493,7 +493,7 @@ static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
return clock->dot;
}
-static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
+static u32 i9xx_dpll_compute_m(struct dpll *dpll)
{
return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
}
@@ -528,8 +528,8 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
clock->p = clock->p1 * clock->p2;
if (WARN_ON(clock->n == 0 || clock->p == 0))
return 0;
- clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
- clock->n << 22);
+ clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m,
+ clock->n << 22);
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
return clock->dot / 5;
@@ -891,7 +891,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
struct drm_device *dev = crtc->base.dev;
unsigned int best_error_ppm;
struct dpll clock;
- uint64_t m2;
+ u64 m2;
int found = false;
memset(best_clock, 0, sizeof(*best_clock));
@@ -913,7 +913,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
clock.p = clock.p1 * clock.p2;
- m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
+ m2 = DIV_ROUND_CLOSEST_ULL(((u64)target * clock.p *
clock.n) << 22, refclk * clock.m1);
if (m2 > INT_MAX/clock.m1)
@@ -1610,7 +1610,7 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
i915_reg_t reg;
- uint32_t val, pipeconf_val;
+ u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
@@ -1698,7 +1698,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
i915_reg_t reg;
- uint32_t val;
+ u32 val;
/* FDI relies on the transcoder */
assert_fdi_tx_disabled(dev_priv, pipe);
@@ -2375,7 +2375,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
return 0;
}
-static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
+static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
switch (fb_modifier) {
case I915_FORMAT_MOD_X_TILED:
@@ -3507,7 +3507,7 @@ u32 skl_plane_stride(const struct intel_plane_state *plane_state,
return stride / skl_plane_stride_mult(fb, color_plane, rotation);
}
-static u32 skl_plane_ctl_format(uint32_t pixel_format)
+static u32 skl_plane_ctl_format(u32 pixel_format)
{
switch (pixel_format) {
case DRM_FORMAT_C8:
@@ -3577,7 +3577,7 @@ static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state
}
}
-static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
+static u32 skl_plane_ctl_tiling(u64 fb_modifier)
{
switch (fb_modifier) {
case DRM_FORMAT_MOD_LINEAR:
@@ -4597,7 +4597,7 @@ static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *c
static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
{
- uint32_t temp;
+ u32 temp;
temp = I915_READ(SOUTH_CHICKEN1);
if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
@@ -5720,7 +5720,7 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- uint32_t val;
+ u32 val;
val = MBUS_DBOX_A_CREDIT(2);
val |= MBUS_DBOX_BW_CREDIT(1);
@@ -6624,9 +6624,9 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
}
-static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
+static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
{
- uint32_t pixel_rate;
+ u32 pixel_rate;
pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
@@ -6636,8 +6636,8 @@ static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
*/
if (pipe_config->pch_pfit.enabled) {
- uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
- uint32_t pfit_size = pipe_config->pch_pfit.size;
+ u64 pipe_w, pipe_h, pfit_w, pfit_h;
+ u32 pfit_size = pipe_config->pch_pfit.size;
pipe_w = pipe_config->pipe_src_w;
pipe_h = pipe_config->pipe_src_h;
@@ -6652,7 +6652,7 @@ static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
if (WARN_ON(!pfit_w || !pfit_h))
return pixel_rate;
- pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
+ pixel_rate = div_u64((u64)pixel_rate * pipe_w * pipe_h,
pfit_w * pfit_h);
}
@@ -6748,7 +6748,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
}
static void
-intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
+intel_reduce_m_n_ratio(u32 *num, u32 *den)
{
while (*num > DATA_LINK_M_N_MASK ||
*den > DATA_LINK_M_N_MASK) {
@@ -6758,7 +6758,7 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
}
static void compute_m_n(unsigned int m, unsigned int n,
- uint32_t *ret_m, uint32_t *ret_n,
+ u32 *ret_m, u32 *ret_n,
bool constant_n)
{
/*
@@ -6773,7 +6773,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
else
*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
- *ret_m = div_u64((uint64_t) m * *ret_n, n);
+ *ret_m = div_u64((u64)m * *ret_n, n);
intel_reduce_m_n_ratio(ret_m, ret_n);
}
@@ -6803,12 +6803,12 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
}
-static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
+static u32 pnv_dpll_compute_fp(struct dpll *dpll)
{
return (1 << dpll->n) << 16 | dpll->m2;
}
-static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
+static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
{
return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
}
@@ -7364,7 +7364,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
- uint32_t crtc_vtotal, crtc_vblank_end;
+ u32 crtc_vtotal, crtc_vblank_end;
int vsyncshift = 0;
/* We need to be careful not to changed the adjusted mode, for otherwise
@@ -7439,7 +7439,7 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
- uint32_t tmp;
+ u32 tmp;
tmp = I915_READ(HTOTAL(cpu_transcoder));
pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
@@ -7510,7 +7510,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- uint32_t pipeconf;
+ u32 pipeconf;
pipeconf = 0;
@@ -7755,7 +7755,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- uint32_t tmp;
+ u32 tmp;
if (INTEL_GEN(dev_priv) <= 3 &&
(IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
@@ -7971,7 +7971,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
- uint32_t tmp;
+ u32 tmp;
bool ret;
power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
@@ -8251,7 +8251,7 @@ static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
{
- uint32_t tmp;
+ u32 tmp;
tmp = I915_READ(SOUTH_CHICKEN2);
tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
@@ -8273,7 +8273,7 @@ static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
/* WaMPhyProgramming:hsw */
static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
{
- uint32_t tmp;
+ u32 tmp;
tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
tmp &= ~(0xFF << 24);
@@ -8354,7 +8354,7 @@ static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
bool with_spread, bool with_fdi)
{
- uint32_t reg, tmp;
+ u32 reg, tmp;
if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
with_spread = true;
@@ -8393,7 +8393,7 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
/* Sequence to disable CLKOUT_DP */
static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
{
- uint32_t reg, tmp;
+ u32 reg, tmp;
mutex_lock(&dev_priv->sb_lock);
@@ -8418,7 +8418,7 @@ static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
#define BEND_IDX(steps) ((50 + (steps)) / 5)
-static const uint16_t sscdivintphase[] = {
+static const u16 sscdivintphase[] = {
[BEND_IDX( 50)] = 0x3B23,
[BEND_IDX( 45)] = 0x3B23,
[BEND_IDX( 40)] = 0x3C23,
@@ -8450,7 +8450,7 @@ static const uint16_t sscdivintphase[] = {
*/
static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
{
- uint32_t tmp;
+ u32 tmp;
int idx = BEND_IDX(steps);
if (WARN_ON(steps % 5 != 0))
@@ -8516,7 +8516,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- uint32_t val;
+ u32 val;
val = 0;
@@ -8863,7 +8863,7 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
- uint32_t ps_ctrl = 0;
+ u32 ps_ctrl = 0;
int id = -1;
int i;
@@ -9019,7 +9019,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- uint32_t tmp;
+ u32 tmp;
tmp = I915_READ(PF_CTL(crtc->pipe));
@@ -9045,7 +9045,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(dev);
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
- uint32_t tmp;
+ u32 tmp;
bool ret;
power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
@@ -9173,7 +9173,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
}
-static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
+static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
{
if (IS_HASWELL(dev_priv))
return I915_READ(D_COMP_HSW);
@@ -9181,7 +9181,7 @@ static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
return I915_READ(D_COMP_BDW);
}
-static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
+static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
{
if (IS_HASWELL(dev_priv)) {
mutex_lock(&dev_priv->pcu_lock);
@@ -9206,7 +9206,7 @@ static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
bool switch_to_fclk, bool allow_power_down)
{
- uint32_t val;
+ u32 val;
assert_can_disable_lcpll(dev_priv);
@@ -9253,7 +9253,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
*/
static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
{
- uint32_t val;
+ u32 val;
val = I915_READ(LCPLL_CTL);
@@ -9328,7 +9328,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
*/
void hsw_enable_pc8(struct drm_i915_private *dev_priv)
{
- uint32_t val;
+ u32 val;
DRM_DEBUG_KMS("Enabling package C8+\n");
@@ -9344,7 +9344,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
void hsw_disable_pc8(struct drm_i915_private *dev_priv)
{
- uint32_t val;
+ u32 val;
DRM_DEBUG_KMS("Disabling package C8+\n");
@@ -9466,7 +9466,7 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
struct intel_crtc_state *pipe_config)
{
enum intel_dpll_id id;
- uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
+ u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
switch (ddi_pll_sel) {
case PORT_CLK_SEL_WRPLL1:
@@ -9634,7 +9634,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum port port;
- uint32_t tmp;
+ u32 tmp;
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
@@ -13751,8 +13751,8 @@ intel_legacy_cursor_update(struct drm_plane *plane,
struct drm_framebuffer *fb,
int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
- uint32_t src_x, uint32_t src_y,
- uint32_t src_w, uint32_t src_h,
+ u32 src_x, u32 src_y,
+ u32 src_w, u32 src_h,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 15/17] drm/i915/display: switch to kernel types
2019-01-16 9:15 ` [PATCH 15/17] drm/i915/display: " Jani Nikula
@ 2019-01-17 1:14 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 1:14 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 16379 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 104 +++++++++++++----------
> ----
> 1 file changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index af164d712e9e..b3d6ee7eee0e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -49,7 +49,7 @@
> #include <linux/reservation.h>
>
> /* Primary plane formats for gen <= 3 */
> -static const uint32_t i8xx_primary_formats[] = {
> +static const u32 i8xx_primary_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB1555,
> @@ -57,7 +57,7 @@ static const uint32_t i8xx_primary_formats[] = {
> };
>
> /* Primary plane formats for gen >= 4 */
> -static const uint32_t i965_primary_formats[] = {
> +static const u32 i965_primary_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> @@ -66,18 +66,18 @@ static const uint32_t i965_primary_formats[] = {
> DRM_FORMAT_XBGR2101010,
> };
>
> -static const uint64_t i9xx_format_modifiers[] = {
> +static const u64 i9xx_format_modifiers[] = {
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> DRM_FORMAT_MOD_INVALID
> };
>
> /* Cursor formats */
> -static const uint32_t intel_cursor_formats[] = {
> +static const u32 intel_cursor_formats[] = {
> DRM_FORMAT_ARGB8888,
> };
>
> -static const uint64_t cursor_format_modifiers[] = {
> +static const u64 cursor_format_modifiers[] = {
> DRM_FORMAT_MOD_LINEAR,
> DRM_FORMAT_MOD_INVALID
> };
> @@ -493,7 +493,7 @@ static int pnv_calc_dpll_params(int refclk,
> struct dpll *clock)
> return clock->dot;
> }
>
> -static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
> +static u32 i9xx_dpll_compute_m(struct dpll *dpll)
> {
> return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
> }
> @@ -528,8 +528,8 @@ int chv_calc_dpll_params(int refclk, struct dpll
> *clock)
> clock->p = clock->p1 * clock->p2;
> if (WARN_ON(clock->n == 0 || clock->p == 0))
> return 0;
> - clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
> - clock->n << 22);
> + clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m,
> + clock->n << 22);
> clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
>
> return clock->dot / 5;
> @@ -891,7 +891,7 @@ chv_find_best_dpll(const struct intel_limit
> *limit,
> struct drm_device *dev = crtc->base.dev;
> unsigned int best_error_ppm;
> struct dpll clock;
> - uint64_t m2;
> + u64 m2;
> int found = false;
>
> memset(best_clock, 0, sizeof(*best_clock));
> @@ -913,7 +913,7 @@ chv_find_best_dpll(const struct intel_limit
> *limit,
>
> clock.p = clock.p1 * clock.p2;
>
> - m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target *
> clock.p *
> + m2 = DIV_ROUND_CLOSEST_ULL(((u64)target *
> clock.p *
> clock.n) << 22, refclk *
> clock.m1);
>
> if (m2 > INT_MAX/clock.m1)
> @@ -1610,7 +1610,7 @@ static void
> ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t reg;
> - uint32_t val, pipeconf_val;
> + u32 val, pipeconf_val;
>
> /* Make sure PCH DPLL is enabled */
> assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
> @@ -1698,7 +1698,7 @@ static void
> ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> i915_reg_t reg;
> - uint32_t val;
> + u32 val;
>
> /* FDI relies on the transcoder */
> assert_fdi_tx_disabled(dev_priv, pipe);
> @@ -2375,7 +2375,7 @@ static int intel_fb_offset_to_xy(int *x, int
> *y,
> return 0;
> }
>
> -static unsigned int intel_fb_modifier_to_tiling(uint64_t
> fb_modifier)
> +static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> {
> switch (fb_modifier) {
> case I915_FORMAT_MOD_X_TILED:
> @@ -3507,7 +3507,7 @@ u32 skl_plane_stride(const struct
> intel_plane_state *plane_state,
> return stride / skl_plane_stride_mult(fb, color_plane,
> rotation);
> }
>
> -static u32 skl_plane_ctl_format(uint32_t pixel_format)
> +static u32 skl_plane_ctl_format(u32 pixel_format)
> {
> switch (pixel_format) {
> case DRM_FORMAT_C8:
> @@ -3577,7 +3577,7 @@ static u32 glk_plane_color_ctl_alpha(const
> struct intel_plane_state *plane_state
> }
> }
>
> -static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
> +static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> {
> switch (fb_modifier) {
> case DRM_FORMAT_MOD_LINEAR:
> @@ -4597,7 +4597,7 @@ static void
> ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *c
>
> static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private
> *dev_priv, bool enable)
> {
> - uint32_t temp;
> + u32 temp;
>
> temp = I915_READ(SOUTH_CHICKEN1);
> if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
> @@ -5720,7 +5720,7 @@ static void icl_pipe_mbus_enable(struct
> intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> - uint32_t val;
> + u32 val;
>
> val = MBUS_DBOX_A_CREDIT(2);
> val |= MBUS_DBOX_BW_CREDIT(1);
> @@ -6624,9 +6624,9 @@ static bool
> intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
> }
>
> -static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
> *pipe_config)
> +static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state
> *pipe_config)
> {
> - uint32_t pixel_rate;
> + u32 pixel_rate;
>
> pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
>
> @@ -6636,8 +6636,8 @@ static uint32_t ilk_pipe_pixel_rate(const
> struct intel_crtc_state *pipe_config)
> */
>
> if (pipe_config->pch_pfit.enabled) {
> - uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
> - uint32_t pfit_size = pipe_config->pch_pfit.size;
> + u64 pipe_w, pipe_h, pfit_w, pfit_h;
> + u32 pfit_size = pipe_config->pch_pfit.size;
>
> pipe_w = pipe_config->pipe_src_w;
> pipe_h = pipe_config->pipe_src_h;
> @@ -6652,7 +6652,7 @@ static uint32_t ilk_pipe_pixel_rate(const
> struct intel_crtc_state *pipe_config)
> if (WARN_ON(!pfit_w || !pfit_h))
> return pixel_rate;
>
> - pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w *
> pipe_h,
> + pixel_rate = div_u64((u64)pixel_rate * pipe_w * pipe_h,
> pfit_w * pfit_h);
> }
>
> @@ -6748,7 +6748,7 @@ static int intel_crtc_compute_config(struct
> intel_crtc *crtc,
> }
>
> static void
> -intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
> +intel_reduce_m_n_ratio(u32 *num, u32 *den)
> {
> while (*num > DATA_LINK_M_N_MASK ||
> *den > DATA_LINK_M_N_MASK) {
> @@ -6758,7 +6758,7 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t
> *den)
> }
>
> static void compute_m_n(unsigned int m, unsigned int n,
> - uint32_t *ret_m, uint32_t *ret_n,
> + u32 *ret_m, u32 *ret_n,
> bool constant_n)
> {
> /*
> @@ -6773,7 +6773,7 @@ static void compute_m_n(unsigned int m,
> unsigned int n,
> else
> *ret_n = min_t(unsigned int, roundup_pow_of_two(n),
> DATA_LINK_N_MAX);
>
> - *ret_m = div_u64((uint64_t) m * *ret_n, n);
> + *ret_m = div_u64((u64)m * *ret_n, n);
> intel_reduce_m_n_ratio(ret_m, ret_n);
> }
>
> @@ -6803,12 +6803,12 @@ static inline bool intel_panel_use_ssc(struct
> drm_i915_private *dev_priv)
> && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
> }
>
> -static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
> +static u32 pnv_dpll_compute_fp(struct dpll *dpll)
> {
> return (1 << dpll->n) << 16 | dpll->m2;
> }
>
> -static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
> +static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
> {
> return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
> }
> @@ -7364,7 +7364,7 @@ static void intel_set_pipe_timings(const struct
> intel_crtc_state *crtc_state)
> enum pipe pipe = crtc->pipe;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> const struct drm_display_mode *adjusted_mode = &crtc_state-
> >base.adjusted_mode;
> - uint32_t crtc_vtotal, crtc_vblank_end;
> + u32 crtc_vtotal, crtc_vblank_end;
> int vsyncshift = 0;
>
> /* We need to be careful not to changed the adjusted mode, for
> otherwise
> @@ -7439,7 +7439,7 @@ static void intel_get_pipe_timings(struct
> intel_crtc *crtc,
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> - uint32_t tmp;
> + u32 tmp;
>
> tmp = I915_READ(HTOTAL(cpu_transcoder));
> pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff)
> + 1;
> @@ -7510,7 +7510,7 @@ static void i9xx_set_pipeconf(const struct
> intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - uint32_t pipeconf;
> + u32 pipeconf;
>
> pipeconf = 0;
>
> @@ -7755,7 +7755,7 @@ static void i9xx_get_pfit_config(struct
> intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - uint32_t tmp;
> + u32 tmp;
>
> if (INTEL_GEN(dev_priv) <= 3 &&
> (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
> @@ -7971,7 +7971,7 @@ static bool i9xx_get_pipe_config(struct
> intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
> - uint32_t tmp;
> + u32 tmp;
> bool ret;
>
> power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
> @@ -8251,7 +8251,7 @@ static void ironlake_init_pch_refclk(struct
> drm_i915_private *dev_priv)
>
> static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
> {
> - uint32_t tmp;
> + u32 tmp;
>
> tmp = I915_READ(SOUTH_CHICKEN2);
> tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
> @@ -8273,7 +8273,7 @@ static void lpt_reset_fdi_mphy(struct
> drm_i915_private *dev_priv)
> /* WaMPhyProgramming:hsw */
> static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
> {
> - uint32_t tmp;
> + u32 tmp;
>
> tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
> tmp &= ~(0xFF << 24);
> @@ -8354,7 +8354,7 @@ static void lpt_program_fdi_mphy(struct
> drm_i915_private *dev_priv)
> static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
> bool with_spread, bool with_fdi)
> {
> - uint32_t reg, tmp;
> + u32 reg, tmp;
>
> if (WARN(with_fdi && !with_spread, "FDI requires
> downspread\n"))
> with_spread = true;
> @@ -8393,7 +8393,7 @@ static void lpt_enable_clkout_dp(struct
> drm_i915_private *dev_priv,
> /* Sequence to disable CLKOUT_DP */
> static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
> {
> - uint32_t reg, tmp;
> + u32 reg, tmp;
>
> mutex_lock(&dev_priv->sb_lock);
>
> @@ -8418,7 +8418,7 @@ static void lpt_disable_clkout_dp(struct
> drm_i915_private *dev_priv)
>
> #define BEND_IDX(steps) ((50 + (steps)) / 5)
>
> -static const uint16_t sscdivintphase[] = {
> +static const u16 sscdivintphase[] = {
> [BEND_IDX( 50)] = 0x3B23,
> [BEND_IDX( 45)] = 0x3B23,
> [BEND_IDX( 40)] = 0x3C23,
> @@ -8450,7 +8450,7 @@ static const uint16_t sscdivintphase[] = {
> */
> static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv,
> int steps)
> {
> - uint32_t tmp;
> + u32 tmp;
> int idx = BEND_IDX(steps);
>
> if (WARN_ON(steps % 5 != 0))
> @@ -8516,7 +8516,7 @@ static void ironlake_set_pipeconf(const struct
> intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> - uint32_t val;
> + u32 val;
>
> val = 0;
>
> @@ -8863,7 +8863,7 @@ static void skylake_get_pfit_config(struct
> intel_crtc *crtc,
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc_scaler_state *scaler_state = &pipe_config-
> >scaler_state;
> - uint32_t ps_ctrl = 0;
> + u32 ps_ctrl = 0;
> int id = -1;
> int i;
>
> @@ -9019,7 +9019,7 @@ static void ironlake_get_pfit_config(struct
> intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - uint32_t tmp;
> + u32 tmp;
>
> tmp = I915_READ(PF_CTL(crtc->pipe));
>
> @@ -9045,7 +9045,7 @@ static bool ironlake_get_pipe_config(struct
> intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
> - uint32_t tmp;
> + u32 tmp;
> bool ret;
>
> power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
> @@ -9173,7 +9173,7 @@ static void assert_can_disable_lcpll(struct
> drm_i915_private *dev_priv)
> I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs
> enabled\n");
> }
>
> -static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
> +static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
> {
> if (IS_HASWELL(dev_priv))
> return I915_READ(D_COMP_HSW);
> @@ -9181,7 +9181,7 @@ static uint32_t hsw_read_dcomp(struct
> drm_i915_private *dev_priv)
> return I915_READ(D_COMP_BDW);
> }
>
> -static void hsw_write_dcomp(struct drm_i915_private *dev_priv,
> uint32_t val)
> +static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32
> val)
> {
> if (IS_HASWELL(dev_priv)) {
> mutex_lock(&dev_priv->pcu_lock);
> @@ -9206,7 +9206,7 @@ static void hsw_write_dcomp(struct
> drm_i915_private *dev_priv, uint32_t val)
> static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
> bool switch_to_fclk, bool
> allow_power_down)
> {
> - uint32_t val;
> + u32 val;
>
> assert_can_disable_lcpll(dev_priv);
>
> @@ -9253,7 +9253,7 @@ static void hsw_disable_lcpll(struct
> drm_i915_private *dev_priv,
> */
> static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> {
> - uint32_t val;
> + u32 val;
>
> val = I915_READ(LCPLL_CTL);
>
> @@ -9328,7 +9328,7 @@ static void hsw_restore_lcpll(struct
> drm_i915_private *dev_priv)
> */
> void hsw_enable_pc8(struct drm_i915_private *dev_priv)
> {
> - uint32_t val;
> + u32 val;
>
> DRM_DEBUG_KMS("Enabling package C8+\n");
>
> @@ -9344,7 +9344,7 @@ void hsw_enable_pc8(struct drm_i915_private
> *dev_priv)
>
> void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> {
> - uint32_t val;
> + u32 val;
>
> DRM_DEBUG_KMS("Disabling package C8+\n");
>
> @@ -9466,7 +9466,7 @@ static void haswell_get_ddi_pll(struct
> drm_i915_private *dev_priv,
> struct intel_crtc_state *pipe_config)
> {
> enum intel_dpll_id id;
> - uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
> + u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
>
> switch (ddi_pll_sel) {
> case PORT_CLK_SEL_WRPLL1:
> @@ -9634,7 +9634,7 @@ static void haswell_get_ddi_port_state(struct
> intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll;
> enum port port;
> - uint32_t tmp;
> + u32 tmp;
>
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config-
> >cpu_transcoder));
>
> @@ -13751,8 +13751,8 @@ intel_legacy_cursor_update(struct drm_plane
> *plane,
> struct drm_framebuffer *fb,
> int crtc_x, int crtc_y,
> unsigned int crtc_w, unsigned int crtc_h,
> - uint32_t src_x, uint32_t src_y,
> - uint32_t src_w, uint32_t src_h,
> + u32 src_x, u32 src_y,
> + u32 src_w, u32 src_h,
> struct drm_modeset_acquire_ctx *ctx)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 16/17] drm/i915/i915_drv.h: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (14 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 15/17] drm/i915/display: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-16 9:21 ` Chris Wilson
2019-01-17 1:20 ` Souza, Jose
2019-01-16 9:15 ` [PATCH 17/17] drm/i915/intel_drv.h: " Jani Nikula
` (6 subsequent siblings)
22 siblings, 2 replies; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 158 ++++++++++++++++----------------
1 file changed, 79 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index da055a86db4d..ae4aedc53ca6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -334,16 +334,16 @@ struct drm_i915_display_funcs {
struct intel_csr {
struct work_struct work;
const char *fw_path;
- uint32_t required_version;
- uint32_t max_fw_size; /* bytes */
- uint32_t *dmc_payload;
- uint32_t dmc_fw_size; /* dwords */
- uint32_t version;
- uint32_t mmio_count;
+ u32 required_version;
+ u32 max_fw_size; /* bytes */
+ u32 *dmc_payload;
+ u32 dmc_fw_size; /* dwords */
+ u32 version;
+ u32 mmio_count;
i915_reg_t mmioaddr[8];
- uint32_t mmiodata[8];
- uint32_t dc_state;
- uint32_t allowed_dc_mask;
+ u32 mmiodata[8];
+ u32 dc_state;
+ u32 allowed_dc_mask;
intel_wakeref_t wakeref;
};
@@ -400,7 +400,7 @@ struct intel_fbc {
struct {
unsigned int mode_flags;
- uint32_t hsw_bdw_pixel_rate;
+ u32 hsw_bdw_pixel_rate;
} crtc;
struct {
@@ -419,7 +419,7 @@ struct intel_fbc {
int y;
- uint16_t pixel_blend_mode;
+ u16 pixel_blend_mode;
} plane;
struct {
@@ -559,7 +559,7 @@ struct i915_suspend_saved_registers {
u32 saveSWF0[16];
u32 saveSWF1[16];
u32 saveSWF3[3];
- uint64_t saveFENCE[I915_MAX_NUM_FENCES];
+ u64 saveFENCE[I915_MAX_NUM_FENCES];
u32 savePCH_PORT_HOTPLUG;
u16 saveGCDGMBUS;
};
@@ -906,9 +906,9 @@ struct i915_gem_mm {
atomic_t bsd_engine_dispatch_index;
/** Bit 6 swizzling required for X tiling */
- uint32_t bit_6_swizzle_x;
+ u32 bit_6_swizzle_x;
/** Bit 6 swizzling required for Y tiling */
- uint32_t bit_6_swizzle_y;
+ u32 bit_6_swizzle_y;
/* accounting, useful for userland debugging */
spinlock_t object_stat_lock;
@@ -935,20 +935,20 @@ struct ddi_vbt_port_info {
* populate this field.
*/
#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
- uint8_t hdmi_level_shift;
+ u8 hdmi_level_shift;
- uint8_t supports_dvi:1;
- uint8_t supports_hdmi:1;
- uint8_t supports_dp:1;
- uint8_t supports_edp:1;
- uint8_t supports_typec_usb:1;
- uint8_t supports_tbt:1;
+ u8 supports_dvi:1;
+ u8 supports_hdmi:1;
+ u8 supports_dp:1;
+ u8 supports_edp:1;
+ u8 supports_typec_usb:1;
+ u8 supports_tbt:1;
- uint8_t alternate_aux_channel;
- uint8_t alternate_ddc_pin;
+ u8 alternate_aux_channel;
+ u8 alternate_ddc_pin;
- uint8_t dp_boost_level;
- uint8_t hdmi_boost_level;
+ u8 dp_boost_level;
+ u8 hdmi_boost_level;
int dp_max_link_rate; /* 0 for not limited by VBT */
};
@@ -1039,41 +1039,41 @@ enum intel_ddb_partitioning {
struct intel_wm_level {
bool enable;
- uint32_t pri_val;
- uint32_t spr_val;
- uint32_t cur_val;
- uint32_t fbc_val;
+ u32 pri_val;
+ u32 spr_val;
+ u32 cur_val;
+ u32 fbc_val;
};
struct ilk_wm_values {
- uint32_t wm_pipe[3];
- uint32_t wm_lp[3];
- uint32_t wm_lp_spr[3];
- uint32_t wm_linetime[3];
+ u32 wm_pipe[3];
+ u32 wm_lp[3];
+ u32 wm_lp_spr[3];
+ u32 wm_linetime[3];
bool enable_fbc_wm;
enum intel_ddb_partitioning partitioning;
};
struct g4x_pipe_wm {
- uint16_t plane[I915_MAX_PLANES];
- uint16_t fbc;
+ u16 plane[I915_MAX_PLANES];
+ u16 fbc;
};
struct g4x_sr_wm {
- uint16_t plane;
- uint16_t cursor;
- uint16_t fbc;
+ u16 plane;
+ u16 cursor;
+ u16 fbc;
};
struct vlv_wm_ddl_values {
- uint8_t plane[I915_MAX_PLANES];
+ u8 plane[I915_MAX_PLANES];
};
struct vlv_wm_values {
struct g4x_pipe_wm pipe[3];
struct g4x_sr_wm sr;
struct vlv_wm_ddl_values ddl[3];
- uint8_t level;
+ u8 level;
bool cxsr;
};
@@ -1087,10 +1087,10 @@ struct g4x_wm_values {
};
struct skl_ddb_entry {
- uint16_t start, end; /* in number of blocks, 'end' is exclusive */
+ u16 start, end; /* in number of blocks, 'end' is exclusive */
};
-static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
+static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
return entry->end - entry->start;
}
@@ -1114,8 +1114,8 @@ struct skl_ddb_values {
};
struct skl_wm_level {
- uint16_t plane_res_b;
- uint8_t plane_res_l;
+ u16 plane_res_b;
+ u8 plane_res_l;
bool plane_en;
};
@@ -1124,15 +1124,15 @@ struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
bool is_planar;
- uint32_t width;
- uint8_t cpp;
- uint32_t plane_pixel_rate;
- uint32_t y_min_scanlines;
- uint32_t plane_bytes_per_line;
+ u32 width;
+ u8 cpp;
+ u32 plane_pixel_rate;
+ u32 y_min_scanlines;
+ u32 plane_bytes_per_line;
uint_fixed_16_16_t plane_blocks_per_line;
uint_fixed_16_16_t y_tile_minimum;
- uint32_t linetime_us;
- uint32_t dbuf_block_size;
+ u32 linetime_us;
+ u32 dbuf_block_size;
};
/*
@@ -1515,14 +1515,14 @@ struct drm_i915_private {
* Base address of where the gmbus and gpio blocks are located (either
* on PCH or on SoC for platforms without PCH).
*/
- uint32_t gpio_mmio_base;
+ u32 gpio_mmio_base;
/* MMIO base address for MIPI regs */
- uint32_t mipi_mmio_base;
+ u32 mipi_mmio_base;
- uint32_t psr_mmio_base;
+ u32 psr_mmio_base;
- uint32_t pps_mmio_base;
+ u32 pps_mmio_base;
wait_queue_head_t gmbus_wait_queue;
@@ -1777,17 +1777,17 @@ struct drm_i915_private {
* in 0.5us units for WM1+.
*/
/* primary */
- uint16_t pri_latency[5];
+ u16 pri_latency[5];
/* sprite */
- uint16_t spr_latency[5];
+ u16 spr_latency[5];
/* cursor */
- uint16_t cur_latency[5];
+ u16 cur_latency[5];
/*
* Raw watermark memory latency values
* for SKL for all 8 levels
* in 1us units.
*/
- uint16_t skl_latency[8];
+ u16 skl_latency[8];
/* current hardware state */
union {
@@ -1797,7 +1797,7 @@ struct drm_i915_private {
struct g4x_wm_values g4x;
};
- uint8_t max_level;
+ u8 max_level;
/*
* Should be held around atomic WM register writing; also
@@ -2707,45 +2707,45 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
- uint32_t mask,
- uint32_t bits);
+ u32 mask,
+ u32 bits);
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask);
+ u32 interrupt_mask,
+ u32 enabled_irq_mask);
static inline void
-ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
+ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
{
ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
-ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
+ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
{
ilk_update_display_irq(dev_priv, bits, 0);
}
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
enum pipe pipe,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask);
+ u32 interrupt_mask,
+ u32 enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
- enum pipe pipe, uint32_t bits)
+ enum pipe pipe, u32 bits)
{
bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
- enum pipe pipe, uint32_t bits)
+ enum pipe pipe, u32 bits)
{
bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask);
+ u32 interrupt_mask,
+ u32 enabled_irq_mask);
static inline void
-ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
+ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
{
ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
-ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
+ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
{
ibx_display_interrupt_update(dev_priv, bits, 0);
}
@@ -3005,7 +3005,7 @@ int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
- uint32_t handle, uint64_t *offset);
+ u32 handle, u64 *offset);
int i915_gem_mmap_gtt_version(void);
void i915_gem_track_fb(struct drm_i915_gem_object *old,
@@ -3156,7 +3156,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
struct i915_gem_context *ctx,
- uint32_t *reg_state);
+ u32 *reg_state);
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
@@ -3408,10 +3408,10 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
enum dpio_phy phy);
-uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
+u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
- uint8_t lane_lat_optim_mask);
-uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
+ u8 lane_lat_optim_mask);
+u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
void chv_set_phy_signal_level(struct intel_encoder *encoder,
u32 deemph_reg_value, u32 margin_reg_value,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 16/17] drm/i915/i915_drv.h: switch to kernel types
2019-01-16 9:15 ` [PATCH 16/17] drm/i915/i915_drv.h: " Jani Nikula
@ 2019-01-16 9:21 ` Chris Wilson
2019-01-17 1:20 ` Souza, Jose
1 sibling, 0 replies; 46+ messages in thread
From: Chris Wilson @ 2019-01-16 9:21 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Quoting Jani Nikula (2019-01-16 09:15:34)
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 16/17] drm/i915/i915_drv.h: switch to kernel types
2019-01-16 9:15 ` [PATCH 16/17] drm/i915/i915_drv.h: " Jani Nikula
2019-01-16 9:21 ` Chris Wilson
@ 2019-01-17 1:20 ` Souza, Jose
1 sibling, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 1:20 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 11121 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel
> types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 158 ++++++++++++++++------------
> ----
> 1 file changed, 79 insertions(+), 79 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index da055a86db4d..ae4aedc53ca6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -334,16 +334,16 @@ struct drm_i915_display_funcs {
> struct intel_csr {
> struct work_struct work;
> const char *fw_path;
> - uint32_t required_version;
> - uint32_t max_fw_size; /* bytes */
> - uint32_t *dmc_payload;
> - uint32_t dmc_fw_size; /* dwords */
> - uint32_t version;
> - uint32_t mmio_count;
> + u32 required_version;
> + u32 max_fw_size; /* bytes */
> + u32 *dmc_payload;
> + u32 dmc_fw_size; /* dwords */
> + u32 version;
> + u32 mmio_count;
> i915_reg_t mmioaddr[8];
> - uint32_t mmiodata[8];
> - uint32_t dc_state;
> - uint32_t allowed_dc_mask;
> + u32 mmiodata[8];
> + u32 dc_state;
> + u32 allowed_dc_mask;
> intel_wakeref_t wakeref;
> };
>
> @@ -400,7 +400,7 @@ struct intel_fbc {
>
> struct {
> unsigned int mode_flags;
> - uint32_t hsw_bdw_pixel_rate;
> + u32 hsw_bdw_pixel_rate;
> } crtc;
>
> struct {
> @@ -419,7 +419,7 @@ struct intel_fbc {
>
> int y;
>
> - uint16_t pixel_blend_mode;
> + u16 pixel_blend_mode;
> } plane;
>
> struct {
> @@ -559,7 +559,7 @@ struct i915_suspend_saved_registers {
> u32 saveSWF0[16];
> u32 saveSWF1[16];
> u32 saveSWF3[3];
> - uint64_t saveFENCE[I915_MAX_NUM_FENCES];
> + u64 saveFENCE[I915_MAX_NUM_FENCES];
> u32 savePCH_PORT_HOTPLUG;
> u16 saveGCDGMBUS;
> };
> @@ -906,9 +906,9 @@ struct i915_gem_mm {
> atomic_t bsd_engine_dispatch_index;
>
> /** Bit 6 swizzling required for X tiling */
> - uint32_t bit_6_swizzle_x;
> + u32 bit_6_swizzle_x;
> /** Bit 6 swizzling required for Y tiling */
> - uint32_t bit_6_swizzle_y;
> + u32 bit_6_swizzle_y;
>
> /* accounting, useful for userland debugging */
> spinlock_t object_stat_lock;
> @@ -935,20 +935,20 @@ struct ddi_vbt_port_info {
> * populate this field.
> */
> #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
> - uint8_t hdmi_level_shift;
> + u8 hdmi_level_shift;
>
> - uint8_t supports_dvi:1;
> - uint8_t supports_hdmi:1;
> - uint8_t supports_dp:1;
> - uint8_t supports_edp:1;
> - uint8_t supports_typec_usb:1;
> - uint8_t supports_tbt:1;
> + u8 supports_dvi:1;
> + u8 supports_hdmi:1;
> + u8 supports_dp:1;
> + u8 supports_edp:1;
> + u8 supports_typec_usb:1;
> + u8 supports_tbt:1;
>
> - uint8_t alternate_aux_channel;
> - uint8_t alternate_ddc_pin;
> + u8 alternate_aux_channel;
> + u8 alternate_ddc_pin;
>
> - uint8_t dp_boost_level;
> - uint8_t hdmi_boost_level;
> + u8 dp_boost_level;
> + u8 hdmi_boost_level;
> int dp_max_link_rate; /* 0 for not limited by VBT
> */
> };
>
> @@ -1039,41 +1039,41 @@ enum intel_ddb_partitioning {
>
> struct intel_wm_level {
> bool enable;
> - uint32_t pri_val;
> - uint32_t spr_val;
> - uint32_t cur_val;
> - uint32_t fbc_val;
> + u32 pri_val;
> + u32 spr_val;
> + u32 cur_val;
> + u32 fbc_val;
> };
>
> struct ilk_wm_values {
> - uint32_t wm_pipe[3];
> - uint32_t wm_lp[3];
> - uint32_t wm_lp_spr[3];
> - uint32_t wm_linetime[3];
> + u32 wm_pipe[3];
> + u32 wm_lp[3];
> + u32 wm_lp_spr[3];
> + u32 wm_linetime[3];
> bool enable_fbc_wm;
> enum intel_ddb_partitioning partitioning;
> };
>
> struct g4x_pipe_wm {
> - uint16_t plane[I915_MAX_PLANES];
> - uint16_t fbc;
> + u16 plane[I915_MAX_PLANES];
> + u16 fbc;
> };
>
> struct g4x_sr_wm {
> - uint16_t plane;
> - uint16_t cursor;
> - uint16_t fbc;
> + u16 plane;
> + u16 cursor;
> + u16 fbc;
> };
>
> struct vlv_wm_ddl_values {
> - uint8_t plane[I915_MAX_PLANES];
> + u8 plane[I915_MAX_PLANES];
> };
>
> struct vlv_wm_values {
> struct g4x_pipe_wm pipe[3];
> struct g4x_sr_wm sr;
> struct vlv_wm_ddl_values ddl[3];
> - uint8_t level;
> + u8 level;
> bool cxsr;
> };
>
> @@ -1087,10 +1087,10 @@ struct g4x_wm_values {
> };
>
> struct skl_ddb_entry {
> - uint16_t start, end; /* in number of blocks, 'end' is
> exclusive */
> + u16 start, end; /* in number of blocks, 'end' is exclusive */
> };
>
> -static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
> *entry)
> +static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry
> *entry)
> {
> return entry->end - entry->start;
> }
> @@ -1114,8 +1114,8 @@ struct skl_ddb_values {
> };
>
> struct skl_wm_level {
> - uint16_t plane_res_b;
> - uint8_t plane_res_l;
> + u16 plane_res_b;
> + u8 plane_res_l;
> bool plane_en;
> };
>
> @@ -1124,15 +1124,15 @@ struct skl_wm_params {
> bool x_tiled, y_tiled;
> bool rc_surface;
> bool is_planar;
> - uint32_t width;
> - uint8_t cpp;
> - uint32_t plane_pixel_rate;
> - uint32_t y_min_scanlines;
> - uint32_t plane_bytes_per_line;
> + u32 width;
> + u8 cpp;
> + u32 plane_pixel_rate;
> + u32 y_min_scanlines;
> + u32 plane_bytes_per_line;
> uint_fixed_16_16_t plane_blocks_per_line;
> uint_fixed_16_16_t y_tile_minimum;
> - uint32_t linetime_us;
> - uint32_t dbuf_block_size;
> + u32 linetime_us;
> + u32 dbuf_block_size;
> };
>
> /*
> @@ -1515,14 +1515,14 @@ struct drm_i915_private {
> * Base address of where the gmbus and gpio blocks are located
> (either
> * on PCH or on SoC for platforms without PCH).
> */
> - uint32_t gpio_mmio_base;
> + u32 gpio_mmio_base;
>
> /* MMIO base address for MIPI regs */
> - uint32_t mipi_mmio_base;
> + u32 mipi_mmio_base;
>
> - uint32_t psr_mmio_base;
> + u32 psr_mmio_base;
>
> - uint32_t pps_mmio_base;
> + u32 pps_mmio_base;
>
> wait_queue_head_t gmbus_wait_queue;
>
> @@ -1777,17 +1777,17 @@ struct drm_i915_private {
> * in 0.5us units for WM1+.
> */
> /* primary */
> - uint16_t pri_latency[5];
> + u16 pri_latency[5];
> /* sprite */
> - uint16_t spr_latency[5];
> + u16 spr_latency[5];
> /* cursor */
> - uint16_t cur_latency[5];
> + u16 cur_latency[5];
> /*
> * Raw watermark memory latency values
> * for SKL for all 8 levels
> * in 1us units.
> */
> - uint16_t skl_latency[8];
> + u16 skl_latency[8];
>
> /* current hardware state */
> union {
> @@ -1797,7 +1797,7 @@ struct drm_i915_private {
> struct g4x_wm_values g4x;
> };
>
> - uint8_t max_level;
> + u8 max_level;
>
> /*
> * Should be held around atomic WM register writing;
> also
> @@ -2707,45 +2707,45 @@ i915_disable_pipestat(struct drm_i915_private
> *dev_priv, enum pipe pipe,
> void valleyview_enable_display_irqs(struct drm_i915_private
> *dev_priv);
> void valleyview_disable_display_irqs(struct drm_i915_private
> *dev_priv);
> void i915_hotplug_interrupt_update(struct drm_i915_private
> *dev_priv,
> - uint32_t mask,
> - uint32_t bits);
> + u32 mask,
> + u32 bits);
> void ilk_update_display_irq(struct drm_i915_private *dev_priv,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask);
> + u32 interrupt_mask,
> + u32 enabled_irq_mask);
> static inline void
> -ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t
> bits)
> +ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
> {
> ilk_update_display_irq(dev_priv, bits, bits);
> }
> static inline void
> -ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t
> bits)
> +ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
> {
> ilk_update_display_irq(dev_priv, bits, 0);
> }
> void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask);
> + u32 interrupt_mask,
> + u32 enabled_irq_mask);
> static inline void bdw_enable_pipe_irq(struct drm_i915_private
> *dev_priv,
> - enum pipe pipe, uint32_t bits)
> + enum pipe pipe, u32 bits)
> {
> bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
> }
> static inline void bdw_disable_pipe_irq(struct drm_i915_private
> *dev_priv,
> - enum pipe pipe, uint32_t bits)
> + enum pipe pipe, u32 bits)
> {
> bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
> }
> void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
> - uint32_t interrupt_mask,
> - uint32_t enabled_irq_mask);
> + u32 interrupt_mask,
> + u32 enabled_irq_mask);
> static inline void
> -ibx_enable_display_interrupt(struct drm_i915_private *dev_priv,
> uint32_t bits)
> +ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32
> bits)
> {
> ibx_display_interrupt_update(dev_priv, bits, bits);
> }
> static inline void
> -ibx_disable_display_interrupt(struct drm_i915_private *dev_priv,
> uint32_t bits)
> +ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32
> bits)
> {
> ibx_display_interrupt_update(dev_priv, bits, 0);
> }
> @@ -3005,7 +3005,7 @@ int i915_gem_dumb_create(struct drm_file
> *file_priv,
> struct drm_device *dev,
> struct drm_mode_create_dumb *args);
> int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device
> *dev,
> - uint32_t handle, uint64_t *offset);
> + u32 handle, u64 *offset);
> int i915_gem_mmap_gtt_version(void);
>
> void i915_gem_track_fb(struct drm_i915_gem_object *old,
> @@ -3156,7 +3156,7 @@ int i915_perf_remove_config_ioctl(struct
> drm_device *dev, void *data,
> struct drm_file *file);
> void i915_oa_init_reg_state(struct intel_engine_cs *engine,
> struct i915_gem_context *ctx,
> - uint32_t *reg_state);
> + u32 *reg_state);
>
> /* i915_gem_evict.c */
> int __must_check i915_gem_evict_something(struct i915_address_space
> *vm,
> @@ -3408,10 +3408,10 @@ bool bxt_ddi_phy_is_enabled(struct
> drm_i915_private *dev_priv,
> enum dpio_phy phy);
> bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
> enum dpio_phy phy);
> -uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
> +u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
> void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
> - uint8_t lane_lat_optim_mask);
> -uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
> *encoder);
> + u8 lane_lat_optim_mask);
> +u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
> *encoder);
>
> void chv_set_phy_signal_level(struct intel_encoder *encoder,
> u32 deemph_reg_value, u32
> margin_reg_value,
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 17/17] drm/i915/intel_drv.h: switch to kernel types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (15 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 16/17] drm/i915/i915_drv.h: " Jani Nikula
@ 2019-01-16 9:15 ` Jani Nikula
2019-01-17 1:23 ` Souza, Jose
2019-01-16 9:22 ` [PATCH 00/17] drm/i915: switch to kernel fixed size types Chris Wilson
` (5 subsequent siblings)
22 siblings, 1 reply; 46+ messages in thread
From: Jani Nikula @ 2019-01-16 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Minor checkpatch fixes sprinkled on top of the changed lines.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 94 ++++++++++++++++----------------
1 file changed, 46 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e5a436c33307..33b733d37706 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -300,13 +300,12 @@ struct intel_panel {
/* Connector and platform specific backlight functions */
int (*setup)(struct intel_connector *connector, enum pipe pipe);
- uint32_t (*get)(struct intel_connector *connector);
- void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
+ u32 (*get)(struct intel_connector *connector);
+ void (*set)(const struct drm_connector_state *conn_state, u32 level);
void (*disable)(const struct drm_connector_state *conn_state);
void (*enable)(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
- uint32_t (*hz_to_pwm)(struct intel_connector *connector,
- uint32_t hz);
+ u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
void (*power)(struct intel_connector *, bool enable);
} backlight;
};
@@ -598,7 +597,7 @@ struct intel_initial_plane_config {
struct intel_scaler {
int in_use;
- uint32_t mode;
+ u32 mode;
};
struct intel_crtc_scaler_state {
@@ -636,7 +635,7 @@ struct intel_crtc_scaler_state {
struct intel_pipe_wm {
struct intel_wm_level wm[5];
- uint32_t linetime;
+ u32 linetime;
bool fbc_wm_enabled;
bool pipe_enabled;
bool sprites_enabled;
@@ -652,7 +651,7 @@ struct skl_plane_wm {
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
- uint32_t linetime;
+ u32 linetime;
};
enum vlv_wm_level {
@@ -665,7 +664,7 @@ enum vlv_wm_level {
struct vlv_wm_state {
struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
- uint8_t num_levels;
+ u8 num_levels;
bool cxsr;
};
@@ -878,13 +877,13 @@ struct intel_crtc_state {
/* Used by SDVO (and if we ever fix it, HDMI). */
unsigned pixel_multiplier;
- uint8_t lane_count;
+ u8 lane_count;
/*
* Used by platforms having DP/HDMI PHY with programmable lane
* latency optimization.
*/
- uint8_t lane_lat_optim_mask;
+ u8 lane_lat_optim_mask;
/* minimum acceptable voltage level */
u8 min_voltage_level;
@@ -928,7 +927,7 @@ struct intel_crtc_state {
struct intel_crtc_wm_state wm;
/* Gamma mode programmed on the pipe */
- uint32_t gamma_mode;
+ u32 gamma_mode;
/* bitmask of visible planes (enum plane_id) */
u8 active_planes;
@@ -1014,7 +1013,7 @@ struct intel_plane {
enum pipe pipe;
bool has_fbc;
bool has_ccs;
- uint32_t frontbuffer_bit;
+ u32 frontbuffer_bit;
struct {
u32 base, cntl, size;
@@ -1109,9 +1108,9 @@ enum link_m_n_set {
struct intel_dp_compliance_data {
unsigned long edid;
- uint8_t video_pattern;
- uint16_t hdisplay, vdisplay;
- uint8_t bpc;
+ u8 video_pattern;
+ u16 hdisplay, vdisplay;
+ u8 bpc;
};
struct intel_dp_compliance {
@@ -1124,18 +1123,18 @@ struct intel_dp_compliance {
struct intel_dp {
i915_reg_t output_reg;
- uint32_t DP;
+ u32 DP;
int link_rate;
- uint8_t lane_count;
- uint8_t sink_count;
+ u8 lane_count;
+ u8 sink_count;
bool link_mst;
bool link_trained;
bool has_audio;
bool reset_link_params;
- uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
- uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
- uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
- uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
+ u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+ u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
u8 fec_capable;
/* source rates */
@@ -1155,7 +1154,7 @@ struct intel_dp {
/* sink or branch descriptor */
struct drm_dp_desc desc;
struct drm_dp_aux aux;
- uint8_t train_set[4];
+ u8 train_set[4];
int panel_power_up_delay;
int panel_power_down_delay;
int panel_power_cycle_delay;
@@ -1197,14 +1196,13 @@ struct intel_dp {
struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
struct drm_dp_mst_topology_mgr mst_mgr;
- uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
+ u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
/*
* This function returns the value we have to program the AUX_CTL
* register with to kick off an AUX transaction.
*/
- uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
- int send_bytes,
- uint32_t aux_clock_divider);
+ u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
+ u32 aux_clock_divider);
i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
@@ -1238,7 +1236,7 @@ struct intel_digital_port {
struct intel_lspcon lspcon;
enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
bool release_cl2_override;
- uint8_t max_lanes;
+ u8 max_lanes;
/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
enum aux_ch aux_ch;
enum intel_display_power_domain ddi_io_power_domain;
@@ -1473,8 +1471,8 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
/* i915_irq.c */
-void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
-void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
+void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
+void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
@@ -1537,7 +1535,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
struct intel_crtc_state *crtc_state);
u32 bxt_signal_levels(struct intel_dp *intel_dp);
-uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
+u32 ddi_signal_levels(struct intel_dp *intel_dp);
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
u8 voltage_swing);
@@ -1677,11 +1675,11 @@ void intel_cleanup_plane_fb(struct drm_plane *plane,
int intel_plane_atomic_get_property(struct drm_plane *plane,
const struct drm_plane_state *state,
struct drm_property *property,
- uint64_t *val);
+ u64 *val);
int intel_plane_atomic_set_property(struct drm_plane *plane,
struct drm_plane_state *state,
struct drm_property *property,
- uint64_t val);
+ u64 val);
int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
struct drm_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
@@ -1801,10 +1799,10 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
struct intel_connector *intel_connector);
void intel_dp_set_link_params(struct intel_dp *intel_dp,
- int link_rate, uint8_t lane_count,
+ int link_rate, u8 lane_count,
bool link_mst);
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
- int link_rate, uint8_t lane_count);
+ int link_rate, u8 lane_count);
void intel_dp_start_link_train(struct intel_dp *intel_dp);
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
@@ -1836,7 +1834,7 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp);
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
-uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
+u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
void intel_plane_destroy(struct drm_plane *plane);
void intel_edp_drrs_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
@@ -1849,24 +1847,24 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
- uint8_t dp_train_pat);
+ u8 dp_train_pat);
void
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
-uint8_t
+u8
intel_dp_voltage_max(struct intel_dp *intel_dp);
-uint8_t
-intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
+u8
+intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
- uint8_t *link_bw, uint8_t *rate_select);
+ u8 *link_bw, u8 *rate_select);
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
bool
-intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
-uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
- int mode_clock, int mode_hdisplay);
-uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
- int mode_hdisplay);
+intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]);
+u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
+ int mode_clock, int mode_hdisplay);
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
+ int mode_hdisplay);
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
@@ -2324,11 +2322,11 @@ void intel_tv_init(struct drm_i915_private *dev_priv);
int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
const struct drm_connector_state *state,
struct drm_property *property,
- uint64_t *val);
+ u64 *val);
int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
struct drm_connector_state *state,
struct drm_property *property,
- uint64_t val);
+ u64 val);
int intel_digital_connector_atomic_check(struct drm_connector *conn,
struct drm_connector_state *new_state);
struct drm_connector_state *
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 17/17] drm/i915/intel_drv.h: switch to kernel types
2019-01-16 9:15 ` [PATCH 17/17] drm/i915/intel_drv.h: " Jani Nikula
@ 2019-01-17 1:23 ` Souza, Jose
0 siblings, 0 replies; 46+ messages in thread
From: Souza, Jose @ 2019-01-17 1:23 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 11790 bytes --]
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Minor checkpatch fixes sprinkled on top of the changed lines.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_drv.h | 94 ++++++++++++++++------------
> ----
> 1 file changed, 46 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index e5a436c33307..33b733d37706 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -300,13 +300,12 @@ struct intel_panel {
>
> /* Connector and platform specific backlight functions
> */
> int (*setup)(struct intel_connector *connector, enum
> pipe pipe);
> - uint32_t (*get)(struct intel_connector *connector);
> - void (*set)(const struct drm_connector_state
> *conn_state, uint32_t level);
> + u32 (*get)(struct intel_connector *connector);
> + void (*set)(const struct drm_connector_state
> *conn_state, u32 level);
> void (*disable)(const struct drm_connector_state
> *conn_state);
> void (*enable)(const struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state);
> - uint32_t (*hz_to_pwm)(struct intel_connector
> *connector,
> - uint32_t hz);
> + u32 (*hz_to_pwm)(struct intel_connector *connector, u32
> hz);
> void (*power)(struct intel_connector *, bool enable);
> } backlight;
> };
> @@ -598,7 +597,7 @@ struct intel_initial_plane_config {
>
> struct intel_scaler {
> int in_use;
> - uint32_t mode;
> + u32 mode;
> };
>
> struct intel_crtc_scaler_state {
> @@ -636,7 +635,7 @@ struct intel_crtc_scaler_state {
>
> struct intel_pipe_wm {
> struct intel_wm_level wm[5];
> - uint32_t linetime;
> + u32 linetime;
> bool fbc_wm_enabled;
> bool pipe_enabled;
> bool sprites_enabled;
> @@ -652,7 +651,7 @@ struct skl_plane_wm {
>
> struct skl_pipe_wm {
> struct skl_plane_wm planes[I915_MAX_PLANES];
> - uint32_t linetime;
> + u32 linetime;
> };
>
> enum vlv_wm_level {
> @@ -665,7 +664,7 @@ enum vlv_wm_level {
> struct vlv_wm_state {
> struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
> struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
> - uint8_t num_levels;
> + u8 num_levels;
> bool cxsr;
> };
>
> @@ -878,13 +877,13 @@ struct intel_crtc_state {
> /* Used by SDVO (and if we ever fix it, HDMI). */
> unsigned pixel_multiplier;
>
> - uint8_t lane_count;
> + u8 lane_count;
>
> /*
> * Used by platforms having DP/HDMI PHY with programmable lane
> * latency optimization.
> */
> - uint8_t lane_lat_optim_mask;
> + u8 lane_lat_optim_mask;
>
> /* minimum acceptable voltage level */
> u8 min_voltage_level;
> @@ -928,7 +927,7 @@ struct intel_crtc_state {
> struct intel_crtc_wm_state wm;
>
> /* Gamma mode programmed on the pipe */
> - uint32_t gamma_mode;
> + u32 gamma_mode;
>
> /* bitmask of visible planes (enum plane_id) */
> u8 active_planes;
> @@ -1014,7 +1013,7 @@ struct intel_plane {
> enum pipe pipe;
> bool has_fbc;
> bool has_ccs;
> - uint32_t frontbuffer_bit;
> + u32 frontbuffer_bit;
>
> struct {
> u32 base, cntl, size;
> @@ -1109,9 +1108,9 @@ enum link_m_n_set {
>
> struct intel_dp_compliance_data {
> unsigned long edid;
> - uint8_t video_pattern;
> - uint16_t hdisplay, vdisplay;
> - uint8_t bpc;
> + u8 video_pattern;
> + u16 hdisplay, vdisplay;
> + u8 bpc;
> };
>
> struct intel_dp_compliance {
> @@ -1124,18 +1123,18 @@ struct intel_dp_compliance {
>
> struct intel_dp {
> i915_reg_t output_reg;
> - uint32_t DP;
> + u32 DP;
> int link_rate;
> - uint8_t lane_count;
> - uint8_t sink_count;
> + u8 lane_count;
> + u8 sink_count;
> bool link_mst;
> bool link_trained;
> bool has_audio;
> bool reset_link_params;
> - uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
> - uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> - uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> - uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> + u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> + u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> u8 fec_capable;
> /* source rates */
> @@ -1155,7 +1154,7 @@ struct intel_dp {
> /* sink or branch descriptor */
> struct drm_dp_desc desc;
> struct drm_dp_aux aux;
> - uint8_t train_set[4];
> + u8 train_set[4];
> int panel_power_up_delay;
> int panel_power_down_delay;
> int panel_power_cycle_delay;
> @@ -1197,14 +1196,13 @@ struct intel_dp {
> struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
> struct drm_dp_mst_topology_mgr mst_mgr;
>
> - uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int
> index);
> + u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
> /*
> * This function returns the value we have to program the
> AUX_CTL
> * register with to kick off an AUX transaction.
> */
> - uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
> - int send_bytes,
> - uint32_t aux_clock_divider);
> + u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
> + u32 aux_clock_divider);
>
> i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
> i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
> @@ -1238,7 +1236,7 @@ struct intel_digital_port {
> struct intel_lspcon lspcon;
> enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
> bool release_cl2_override;
> - uint8_t max_lanes;
> + u8 max_lanes;
> /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
> enum aux_ch aux_ch;
> enum intel_display_power_domain ddi_io_power_domain;
> @@ -1473,8 +1471,8 @@ void intel_check_cpu_fifo_underruns(struct
> drm_i915_private *dev_priv);
> void intel_check_pch_fifo_underruns(struct drm_i915_private
> *dev_priv);
>
> /* i915_irq.c */
> -void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t
> mask);
> -void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t
> mask);
> +void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32
> mask);
> +void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32
> mask);
> void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
> void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32
> mask);
> void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
> @@ -1537,7 +1535,7 @@ void intel_ddi_set_vc_payload_alloc(const
> struct intel_crtc_state *crtc_state,
> void intel_ddi_compute_min_voltage_level(struct drm_i915_private
> *dev_priv,
> struct intel_crtc_state
> *crtc_state);
> u32 bxt_signal_levels(struct intel_dp *intel_dp);
> -uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> +u32 ddi_signal_levels(struct intel_dp *intel_dp);
> u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
> u8 voltage_swing);
> @@ -1677,11 +1675,11 @@ void intel_cleanup_plane_fb(struct drm_plane
> *plane,
> int intel_plane_atomic_get_property(struct drm_plane *plane,
> const struct drm_plane_state
> *state,
> struct drm_property *property,
> - uint64_t *val);
> + u64 *val);
> int intel_plane_atomic_set_property(struct drm_plane *plane,
> struct drm_plane_state *state,
> struct drm_property *property,
> - uint64_t val);
> + u64 val);
> int intel_plane_atomic_calc_changes(const struct intel_crtc_state
> *old_crtc_state,
> struct drm_crtc_state *crtc_state,
> const struct intel_plane_state
> *old_plane_state,
> @@ -1801,10 +1799,10 @@ bool intel_dp_init(struct drm_i915_private
> *dev_priv, i915_reg_t output_reg,
> bool intel_dp_init_connector(struct intel_digital_port
> *intel_dig_port,
> struct intel_connector *intel_connector);
> void intel_dp_set_link_params(struct intel_dp *intel_dp,
> - int link_rate, uint8_t lane_count,
> + int link_rate, u8 lane_count,
> bool link_mst);
> int intel_dp_get_link_train_fallback_values(struct intel_dp
> *intel_dp,
> - int link_rate, uint8_t
> lane_count);
> + int link_rate, u8
> lane_count);
> void intel_dp_start_link_train(struct intel_dp *intel_dp);
> void intel_dp_stop_link_train(struct intel_dp *intel_dp);
> int intel_dp_retrain_link(struct intel_encoder *encoder,
> @@ -1836,7 +1834,7 @@ int intel_dp_max_lane_count(struct intel_dp
> *intel_dp);
> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
> void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
> void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
> -uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
> +u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
> void intel_plane_destroy(struct drm_plane *plane);
> void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> @@ -1849,24 +1847,24 @@ void intel_edp_drrs_flush(struct
> drm_i915_private *dev_priv,
>
> void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> - uint8_t dp_train_pat);
> + u8 dp_train_pat);
> void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp);
> void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> -uint8_t
> +u8
> intel_dp_voltage_max(struct intel_dp *intel_dp);
> -uint8_t
> -intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t
> voltage_swing);
> +u8
> +intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8
> voltage_swing);
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int
> port_clock,
> - uint8_t *link_bw, uint8_t *rate_select);
> + u8 *link_bw, u8 *rate_select);
> bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
> bool
> -intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t
> link_status[DP_LINK_STATUS_SIZE]);
> -uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t
> lane_count,
> - int mode_clock, int
> mode_hdisplay);
> -uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int
> mode_clock,
> - int mode_hdisplay);
> +intel_dp_get_link_status(struct intel_dp *intel_dp, u8
> link_status[DP_LINK_STATUS_SIZE]);
> +u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
> + int mode_clock, int mode_hdisplay);
> +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int
> mode_clock,
> + int mode_hdisplay);
>
> /* intel_vdsc.c */
> int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> @@ -2324,11 +2322,11 @@ void intel_tv_init(struct drm_i915_private
> *dev_priv);
> int intel_digital_connector_atomic_get_property(struct drm_connector
> *connector,
> const struct
> drm_connector_state *state,
> struct drm_property
> *property,
> - uint64_t *val);
> + u64 *val);
> int intel_digital_connector_atomic_set_property(struct drm_connector
> *connector,
> struct
> drm_connector_state *state,
> struct drm_property
> *property,
> - uint64_t val);
> + u64 val);
> int intel_digital_connector_atomic_check(struct drm_connector *conn,
> struct drm_connector_state
> *new_state);
> struct drm_connector_state *
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 00/17] drm/i915: switch to kernel fixed size types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (16 preceding siblings ...)
2019-01-16 9:15 ` [PATCH 17/17] drm/i915/intel_drv.h: " Jani Nikula
@ 2019-01-16 9:22 ` Chris Wilson
2019-01-16 9:26 ` Tvrtko Ursulin
` (4 subsequent siblings)
22 siblings, 0 replies; 46+ messages in thread
From: Chris Wilson @ 2019-01-16 9:22 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Quoting Jani Nikula (2019-01-16 09:15:18)
> Hi all -
>
> I haven't cared all that much about using C99 fixed size types (uint32_t
> etc.) in the driver in addition to kernel types, as long as only one or
> the other is used in the same struct/function/file. But the increasing
> mixed use crossed some OCD threshold the other day. It gets ugly, and
> sets a precedent that mixed use is fine.
>
> Let's switch to kernel types exclusively, shall we?
>
> Each path in the series is independent of the others, and it's mostly
> one patch per file, apart from the first patch which gathers all the
> isolated uses into one patch. I've tried to order the series from least
> to most likely to cause conflicts with in-flight work per gut feeling.
>
> Please holler if you think some of these patches need to wait for some
> other, more important stuff to land first. This was mostly scripted,
> with a few manual edits on top, so pretty quick to redo on top later.
>
> After most of these have landed, I intend to drop PREFER_KERNEL_TYPES
> from the checkpatch ignore list, and enforce.
>
> BR,
> Jani.
>
>
> Jani Nikula (17):
> drm/i915: small isolated c99 types to kernel types switch
> drm/i915/crt: switch to kernel types
> drm/i915/sdvo: switch to kernel types
> drm/i915/lspcon: switch to kernel types
> drm/i915/debugfs: switch to kernel types
> drm/i915/irq: switch to kernel types
> drm/i915/cdclk: switch to kernel types
> drm/i915/dpll_mgr: switch to kernel types
> drm/i915/dp: switch to kernel types
> drm/i915/sprite: switch to kernel types
> drm/i915/color: switch to kernel types
> drm/i915/pm: switch to kernel types
> drm/i915/ddi: switch to kernel types
> drm/i915/csr: switch to kernel types
> drm/i915/display: switch to kernel types
> drm/i915/i915_drv.h: switch to kernel types
> drm/i915/intel_drv.h: switch to kernel types
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
I've reviewed the patches that touch the code I work with most, leaving
the display chunks which have the majority preference for stdint.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH 00/17] drm/i915: switch to kernel fixed size types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (17 preceding siblings ...)
2019-01-16 9:22 ` [PATCH 00/17] drm/i915: switch to kernel fixed size types Chris Wilson
@ 2019-01-16 9:26 ` Tvrtko Ursulin
2019-01-16 10:54 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
` (3 subsequent siblings)
22 siblings, 0 replies; 46+ messages in thread
From: Tvrtko Ursulin @ 2019-01-16 9:26 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 16/01/2019 09:15, Jani Nikula wrote:
> Hi all -
>
> I haven't cared all that much about using C99 fixed size types (uint32_t
> etc.) in the driver in addition to kernel types, as long as only one or
> the other is used in the same struct/function/file. But the increasing
> mixed use crossed some OCD threshold the other day. It gets ugly, and
> sets a precedent that mixed use is fine.
>
> Let's switch to kernel types exclusively, shall we?
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Holler if you need reviews as well.
Regards,
Tvrtko
> Each path in the series is independent of the others, and it's mostly
> one patch per file, apart from the first patch which gathers all the
> isolated uses into one patch. I've tried to order the series from least
> to most likely to cause conflicts with in-flight work per gut feeling.
>
> Please holler if you think some of these patches need to wait for some
> other, more important stuff to land first. This was mostly scripted,
> with a few manual edits on top, so pretty quick to redo on top later.
>
> After most of these have landed, I intend to drop PREFER_KERNEL_TYPES
> from the checkpatch ignore list, and enforce.
>
> BR,
> Jani.
>
>
> Jani Nikula (17):
> drm/i915: small isolated c99 types to kernel types switch
> drm/i915/crt: switch to kernel types
> drm/i915/sdvo: switch to kernel types
> drm/i915/lspcon: switch to kernel types
> drm/i915/debugfs: switch to kernel types
> drm/i915/irq: switch to kernel types
> drm/i915/cdclk: switch to kernel types
> drm/i915/dpll_mgr: switch to kernel types
> drm/i915/dp: switch to kernel types
> drm/i915/sprite: switch to kernel types
> drm/i915/color: switch to kernel types
> drm/i915/pm: switch to kernel types
> drm/i915/ddi: switch to kernel types
> drm/i915/csr: switch to kernel types
> drm/i915/display: switch to kernel types
> drm/i915/i915_drv.h: switch to kernel types
> drm/i915/intel_drv.h: switch to kernel types
>
> drivers/gpu/drm/i915/i915_debugfs.c | 22 +-
> drivers/gpu/drm/i915/i915_drv.h | 158 ++++++-------
> drivers/gpu/drm/i915/i915_gem.c | 14 +-
> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 8 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 10 +-
> drivers/gpu/drm/i915/i915_irq.c | 82 +++----
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 +-
> drivers/gpu/drm/i915/intel_atomic.c | 4 +-
> drivers/gpu/drm/i915/intel_atomic_plane.c | 4 +-
> drivers/gpu/drm/i915/intel_cdclk.c | 40 ++--
> drivers/gpu/drm/i915/intel_color.c | 40 ++--
> drivers/gpu/drm/i915/intel_crt.c | 22 +-
> drivers/gpu/drm/i915/intel_csr.c | 68 +++---
> drivers/gpu/drm/i915/intel_ddi.c | 52 ++---
> drivers/gpu/drm/i915/intel_display.c | 104 ++++-----
> drivers/gpu/drm/i915/intel_dp.c | 142 ++++++------
> drivers/gpu/drm/i915/intel_dp_link_training.c | 32 +--
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/intel_dpio_phy.c | 18 +-
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 145 ++++++------
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 53 +++--
> drivers/gpu/drm/i915/intel_drv.h | 94 ++++----
> drivers/gpu/drm/i915/intel_engine_cs.c | 12 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 12 +-
> drivers/gpu/drm/i915/intel_hdcp.c | 4 +-
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/intel_lspcon.c | 20 +-
> drivers/gpu/drm/i915/intel_pipe_crc.c | 18 +-
> drivers/gpu/drm/i915/intel_pm.c | 213 +++++++++---------
> drivers/gpu/drm/i915/intel_psr.c | 6 +-
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +-
> drivers/gpu/drm/i915/intel_sdvo.c | 78 +++----
> drivers/gpu/drm/i915/intel_sprite.c | 60 ++---
> 36 files changed, 782 insertions(+), 787 deletions(-)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: switch to kernel fixed size types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (18 preceding siblings ...)
2019-01-16 9:26 ` Tvrtko Ursulin
@ 2019-01-16 10:54 ` Patchwork
2019-01-16 11:34 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
22 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2019-01-16 10:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: switch to kernel fixed size types
URL : https://patchwork.freedesktop.org/series/55281/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: small isolated c99 types to kernel types switch
Okay!
Commit: drm/i915/crt: switch to kernel types
Okay!
Commit: drm/i915/sdvo: switch to kernel types
Okay!
Commit: drm/i915/lspcon: switch to kernel types
Okay!
Commit: drm/i915/debugfs: switch to kernel types
Okay!
Commit: drm/i915/irq: switch to kernel types
Okay!
Commit: drm/i915/cdclk: switch to kernel types
Okay!
Commit: drm/i915/dpll_mgr: switch to kernel types
Okay!
Commit: drm/i915/dp: switch to kernel types
-O:drivers/gpu/drm/i915/intel_dp.c:4355:27: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:4355:27: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:4355:27: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:4355:27: warning: expression using sizeof(void)
Commit: drm/i915/sprite: switch to kernel types
Okay!
Commit: drm/i915/color: switch to kernel types
Okay!
Commit: drm/i915/pm: switch to kernel types
-O:drivers/gpu/drm/i915/intel_pm.c:2734:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2734:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2735:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2735:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2736:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2736:35: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2989:17: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2989:17: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2991:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:2991:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2732:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2732:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2733:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2733:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2734:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2734:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2987:17: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2987:17: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2989:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:2989:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:4860:30: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_pm.c:4860:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:4857:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_pm.c:4857:30: warning: expression using sizeof(void)
Commit: drm/i915/ddi: switch to kernel types
Okay!
Commit: drm/i915/csr: switch to kernel types
Okay!
Commit: drm/i915/display: switch to kernel types
-O:drivers/gpu/drm/i915/intel_display.c:6774:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_display.c:6774:26: warning: expression using sizeof(void)
Commit: drm/i915/i915_drv.h: switch to kernel types
Okay!
Commit: drm/i915/intel_drv.h: switch to kernel types
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: switch to kernel fixed size types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (19 preceding siblings ...)
2019-01-16 10:54 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
@ 2019-01-16 11:34 ` Patchwork
2019-01-16 14:37 ` ✓ Fi.CI.IGT: " Patchwork
2019-01-16 17:05 ` [PATCH 00/17] " Ville Syrjälä
22 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2019-01-16 11:34 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: switch to kernel fixed size types
URL : https://patchwork.freedesktop.org/series/55281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5433 -> Patchwork_11305
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/55281/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_11305 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: PASS -> FAIL [fdo#104008]
#### Possible fixes ####
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160: DMESG-FAIL [fdo#108735] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Participating hosts (49 -> 42)
------------------------------
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y
Build changes
-------------
* Linux: CI_DRM_5433 -> Patchwork_11305
CI_DRM_5433: 8cd42452395a9812786bfa66ea6dec48345ba0ad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4773: 951e2b1a016b750544d0f42459b13b9c70631c68 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11305: 078c203e2e6af27bba190c5cd5a29033860d94c8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
078c203e2e6a drm/i915/intel_drv.h: switch to kernel types
a2996eb3a6f7 drm/i915/i915_drv.h: switch to kernel types
7e1d12f0ba69 drm/i915/display: switch to kernel types
797e9a39ba63 drm/i915/csr: switch to kernel types
c5b8961d3a76 drm/i915/ddi: switch to kernel types
9679206d8fda drm/i915/pm: switch to kernel types
d4e521bd8cdf drm/i915/color: switch to kernel types
3aef71fd7801 drm/i915/sprite: switch to kernel types
dec8f3670a1f drm/i915/dp: switch to kernel types
85fcd1ea659f drm/i915/dpll_mgr: switch to kernel types
aaea2428c5b7 drm/i915/cdclk: switch to kernel types
1c51fd336099 drm/i915/irq: switch to kernel types
e568c52b25bb drm/i915/debugfs: switch to kernel types
b32c744854f0 drm/i915/lspcon: switch to kernel types
25ba2a892e01 drm/i915/sdvo: switch to kernel types
d03428f011de drm/i915/crt: switch to kernel types
8986afd7c43c drm/i915: small isolated c99 types to kernel types switch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11305/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: switch to kernel fixed size types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (20 preceding siblings ...)
2019-01-16 11:34 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-01-16 14:37 ` Patchwork
2019-01-16 17:05 ` [PATCH 00/17] " Ville Syrjälä
22 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2019-01-16 14:37 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: switch to kernel fixed size types
URL : https://patchwork.freedesktop.org/series/55281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5433_full -> Patchwork_11305_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11305_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@runner@aborted}:
- shard-glk: FAIL -> ( 2 FAIL )
Known issues
------------
Here are the changes found in Patchwork_11305_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_userptr_blits@readonly-unsync:
- shard-iclb: PASS -> INCOMPLETE [fdo#108342]
* igt@kms_atomic_transition@plane-all-transition:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#109225]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-primary-rotation-180:
- shard-skl: NOTRUN -> FAIL [fdo#107725]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145] +1
* igt@kms_ccs@pipe-b-crc-primary-basic:
- shard-iclb: NOTRUN -> FAIL [fdo#107725]
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled:
- shard-skl: NOTRUN -> FAIL [fdo#108145] / [fdo#108472]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107882] +1
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: NOTRUN -> FAIL [fdo#105363] +1
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-apl: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_flip@flip-vs-modeset-vs-hang-interruptible:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724]
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: PASS -> FAIL [fdo#100368]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-skl: NOTRUN -> FAIL [fdo#105683]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#109247] / [fdo#109355] +13
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render:
- shard-iclb: NOTRUN -> FAIL [fdo#109247] / [fdo#109355] +2
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: PASS -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: PASS -> FAIL [fdo#103166] +2
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_psr@no_drrs:
- shard-iclb: PASS -> FAIL [fdo#108341]
* igt@kms_psr@primary_blt:
- shard-iclb: PASS -> FAIL [fdo#107383] +2
* igt@kms_psr@sprite_blt:
- shard-iclb: NOTRUN -> FAIL [fdo#107383]
* igt@pm_backlight@fade_with_suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107847]
* igt@pm_rpm@system-suspend-devices:
- shard-iclb: PASS -> DMESG-WARN [fdo#108654]
* igt@pm_rps@reset:
- shard-iclb: NOTRUN -> FAIL [fdo#102250] / [fdo#108059]
#### Possible fixes ####
* igt@gem_softpin@noreloc-s3:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
- shard-snb: INCOMPLETE [fdo#105411] -> PASS
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: FAIL [fdo#104873] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-hsw: {SKIP} [fdo#109271] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-iclb: INCOMPLETE [fdo#107713] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-iclb: FAIL [fdo#103166] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: DMESG-FAIL [fdo#108950] -> PASS
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@gem-mmap-cpu:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS
#### Warnings ####
* igt@i915_suspend@shrink:
- shard-skl: INCOMPLETE [fdo#106886] -> DMESG-WARN [fdo#107886] / [fdo#109244]
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-iclb: FAIL [fdo#103232] -> INCOMPLETE [fdo#107713]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-iclb: FAIL [fdo#103232] -> DMESG-WARN [fdo#107724] / [fdo#108336]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
[fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
[fdo#107882]: https://bugs.freedesktop.org/show_bug.cgi?id=107882
[fdo#107886]: https://bugs.freedesktop.org/show_bug.cgi?id=107886
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108342]: https://bugs.freedesktop.org/show_bug.cgi?id=108342
[fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109225]: https://bugs.freedesktop.org/show_bug.cgi?id=109225
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109281]: https://bugs.freedesktop.org/show_bug.cgi?id=109281
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109287]: https://bugs.freedesktop.org/show_bug.cgi?id=109287
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#109355]: https://bugs.freedesktop.org/show_bug.cgi?id=109355
[fdo#109358]: https://bugs.freedesktop.org/show_bug.cgi?id=109358
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5433 -> Patchwork_11305
CI_DRM_5433: 8cd42452395a9812786bfa66ea6dec48345ba0ad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4773: 951e2b1a016b750544d0f42459b13b9c70631c68 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11305: 078c203e2e6af27bba190c5cd5a29033860d94c8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11305/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH 00/17] drm/i915: switch to kernel fixed size types
2019-01-16 9:15 [PATCH 00/17] drm/i915: switch to kernel fixed size types Jani Nikula
` (21 preceding siblings ...)
2019-01-16 14:37 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-01-16 17:05 ` Ville Syrjälä
2019-01-17 7:29 ` Jani Nikula
22 siblings, 1 reply; 46+ messages in thread
From: Ville Syrjälä @ 2019-01-16 17:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Jan 16, 2019 at 11:15:18AM +0200, Jani Nikula wrote:
> Hi all -
>
> I haven't cared all that much about using C99 fixed size types (uint32_t
> etc.) in the driver in addition to kernel types, as long as only one or
> the other is used in the same struct/function/file. But the increasing
> mixed use crossed some OCD threshold the other day. It gets ugly, and
> sets a precedent that mixed use is fine.
>
> Let's switch to kernel types exclusively, shall we?
>
> Each path in the series is independent of the others, and it's mostly
> one patch per file, apart from the first patch which gathers all the
> isolated uses into one patch. I've tried to order the series from least
> to most likely to cause conflicts with in-flight work per gut feeling.
>
> Please holler if you think some of these patches need to wait for some
> other, more important stuff to land first. This was mostly scripted,
> with a few manual edits on top, so pretty quick to redo on top later.
>
> After most of these have landed, I intend to drop PREFER_KERNEL_TYPES
> from the checkpatch ignore list, and enforce.
Did a really quick scan through and the pattern matcher in the
brain didn't complain, so seems good enough to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> BR,
> Jani.
>
>
> Jani Nikula (17):
> drm/i915: small isolated c99 types to kernel types switch
> drm/i915/crt: switch to kernel types
> drm/i915/sdvo: switch to kernel types
> drm/i915/lspcon: switch to kernel types
> drm/i915/debugfs: switch to kernel types
> drm/i915/irq: switch to kernel types
> drm/i915/cdclk: switch to kernel types
> drm/i915/dpll_mgr: switch to kernel types
> drm/i915/dp: switch to kernel types
> drm/i915/sprite: switch to kernel types
> drm/i915/color: switch to kernel types
> drm/i915/pm: switch to kernel types
> drm/i915/ddi: switch to kernel types
> drm/i915/csr: switch to kernel types
> drm/i915/display: switch to kernel types
> drm/i915/i915_drv.h: switch to kernel types
> drm/i915/intel_drv.h: switch to kernel types
>
> drivers/gpu/drm/i915/i915_debugfs.c | 22 +-
> drivers/gpu/drm/i915/i915_drv.h | 158 ++++++-------
> drivers/gpu/drm/i915/i915_gem.c | 14 +-
> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 8 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 10 +-
> drivers/gpu/drm/i915/i915_irq.c | 82 +++----
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 +-
> drivers/gpu/drm/i915/intel_atomic.c | 4 +-
> drivers/gpu/drm/i915/intel_atomic_plane.c | 4 +-
> drivers/gpu/drm/i915/intel_cdclk.c | 40 ++--
> drivers/gpu/drm/i915/intel_color.c | 40 ++--
> drivers/gpu/drm/i915/intel_crt.c | 22 +-
> drivers/gpu/drm/i915/intel_csr.c | 68 +++---
> drivers/gpu/drm/i915/intel_ddi.c | 52 ++---
> drivers/gpu/drm/i915/intel_display.c | 104 ++++-----
> drivers/gpu/drm/i915/intel_dp.c | 142 ++++++------
> drivers/gpu/drm/i915/intel_dp_link_training.c | 32 +--
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/intel_dpio_phy.c | 18 +-
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 145 ++++++------
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 53 +++--
> drivers/gpu/drm/i915/intel_drv.h | 94 ++++----
> drivers/gpu/drm/i915/intel_engine_cs.c | 12 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 12 +-
> drivers/gpu/drm/i915/intel_hdcp.c | 4 +-
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/intel_lspcon.c | 20 +-
> drivers/gpu/drm/i915/intel_pipe_crc.c | 18 +-
> drivers/gpu/drm/i915/intel_pm.c | 213 +++++++++---------
> drivers/gpu/drm/i915/intel_psr.c | 6 +-
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +-
> drivers/gpu/drm/i915/intel_sdvo.c | 78 +++----
> drivers/gpu/drm/i915/intel_sprite.c | 60 ++---
> 36 files changed, 782 insertions(+), 787 deletions(-)
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH 00/17] drm/i915: switch to kernel fixed size types
2019-01-16 17:05 ` [PATCH 00/17] " Ville Syrjälä
@ 2019-01-17 7:29 ` Jani Nikula
0 siblings, 0 replies; 46+ messages in thread
From: Jani Nikula @ 2019-01-17 7:29 UTC (permalink / raw)
To: Ville Syrjälä, Chris Wilson, Souza, Jose,
Tvrtko Ursulin
Cc: intel-gfx
On Wed, 16 Jan 2019, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Jan 16, 2019 at 11:15:18AM +0200, Jani Nikula wrote:
>> Hi all -
>>
>> I haven't cared all that much about using C99 fixed size types (uint32_t
>> etc.) in the driver in addition to kernel types, as long as only one or
>> the other is used in the same struct/function/file. But the increasing
>> mixed use crossed some OCD threshold the other day. It gets ugly, and
>> sets a precedent that mixed use is fine.
>>
>> Let's switch to kernel types exclusively, shall we?
>>
>> Each path in the series is independent of the others, and it's mostly
>> one patch per file, apart from the first patch which gathers all the
>> isolated uses into one patch. I've tried to order the series from least
>> to most likely to cause conflicts with in-flight work per gut feeling.
>>
>> Please holler if you think some of these patches need to wait for some
>> other, more important stuff to land first. This was mostly scripted,
>> with a few manual edits on top, so pretty quick to redo on top later.
>>
>> After most of these have landed, I intend to drop PREFER_KERNEL_TYPES
>> from the checkpatch ignore list, and enforce.
>
> Did a really quick scan through and the pattern matcher in the
> brain didn't complain, so seems good enough to me.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks for the reviews Chris, Ville & José! I pushed the the patches
listed below for starters. Started small.
While I took care with the r-b's, I failed to record the acks from Chris
and Tvrtko. :( Apologies.
BR,
Jani.
Pushed now:
>> drm/i915: small isolated c99 types to kernel types switch
>> drm/i915/crt: switch to kernel types
>> drm/i915/lspcon: switch to kernel types
>> drm/i915/debugfs: switch to kernel types
>> drm/i915/irq: switch to kernel types
>> drm/i915/cdclk: switch to kernel types
>> drm/i915/dpll_mgr: switch to kernel types
>> drm/i915/dp: switch to kernel types
>> drm/i915/sprite: switch to kernel types
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread