[PATCH] drm/i915: list self-refresh as enabled on newer platforms

[PATCH] drm/i915: list self-refresh as enabled on newer platforms

[Jesse Barnes]

I guess this is a lie for 8xx, but newer stuff takes care of this for
us.

References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 91c945b..a8f42a7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1686,6 +1686,8 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev))
 		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+	else
+		sr_enabled = true; /* other platforms don't need enabling */
 
 	intel_runtime_pm_put(dev_priv);
 
-- 
1.9.1

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Re: [PATCH] drm/i915: list self-refresh as enabled on newer platforms

[Ville Syrjälä]

On Thu, Apr 02, 2015 at 11:18:49AM -0700, Jesse Barnes wrote:
> I guess this is a lie for 8xx, but newer stuff takes care of this for
> us.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 91c945b..a8f42a7 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1686,6 +1686,8 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>  	else if (IS_PINEVIEW(dev))
>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
> +	else
> +		sr_enabled = true; /* other platforms don't need enabling */

Not true actually.

The line between maxfifo and SR is a blurry one. We treat them as the
same thing. So I think this should just read out whatever registers
we set up in intel_set_memory_cxsr().

On ILK+ it should actually check if LP1+ watermarks are enabled or not.
And I can't recall enough details on SKL right now to have an idea what
should be done there.

That's all assuming we want this file to be at least somewhat useful.
I think the other good option is to just remove the file entirely and
depend on the new intel_watermark tool I wrote recently.

>  
>  	intel_runtime_pm_put(dev_priv);
>  
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915: list self-refresh as enabled on newer platforms

[Jesse Barnes]

On 04/02/2015 11:42 AM, Ville Syrjälä wrote:
> On Thu, Apr 02, 2015 at 11:18:49AM -0700, Jesse Barnes wrote:
>> I guess this is a lie for 8xx, but newer stuff takes care of this for
>> us.
>>
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
>> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 91c945b..a8f42a7 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1686,6 +1686,8 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>>  	else if (IS_PINEVIEW(dev))
>>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>> +	else
>> +		sr_enabled = true; /* other platforms don't need enabling */
> 
> Not true actually.
> 
> The line between maxfifo and SR is a blurry one. We treat them as the
> same thing. So I think this should just read out whatever registers
> we set up in intel_set_memory_cxsr().
> 
> On ILK+ it should actually check if LP1+ watermarks are enabled or not.
> And I can't recall enough details on SKL right now to have an idea what
> should be done there.
> 
> That's all assuming we want this file to be at least somewhat useful.
> I think the other good option is to just remove the file entirely and
> depend on the new intel_watermark tool I wrote recently.

Yeah, that might be a better option.  And beyond just this we want SR
residency anyway, so finding the debug regs for that and making a tool
is a better long term solution.

Jesse

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Re: [PATCH] drm/i915: list self-refresh as enabled on newer platforms

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6125
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -3              272/272              269/272
ILK                                  302/302              302/302
SNB                                  303/303              303/303
IVB                                  338/338              338/338
BYT                 -1              287/287              286/287
HSW                                  361/361              361/361
BDW                                  308/308              308/308
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt@gem_tiled_pread_pwrite      FAIL(3)PASS(10)      FAIL(1)PASS(1)
 PNV  igt@gem_userptr_blits@coherency-sync      CRASH(5)PASS(7)      CRASH(1)PASS(1)
 PNV  igt@gen3_render_tiledx_blits      FAIL(6)PASS(5)      FAIL(1)PASS(1)
*BYT  igt@gem_exec_bad_domains@conflicting-write-domain      PASS(17)      FAIL(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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[PATCH] drm/i915: Include VLV in self refresh status

[Ander Conselvan de Oliveira]

The line between maxfifo and SR is a blurry one. Since we treat them as
the same thing, just read out the registers set up in
intel_set_memory_cxsr().

References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

---

On 04/02/2015 11:42 AM, Ville Syrjälä wrote:
> On Thu, Apr 02, 2015 at 11:18:49AM -0700, Jesse Barnes wrote:
>> I guess this is a lie for 8xx, but newer stuff takes care of this for
>> us.
>>
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
>> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 91c945b..a8f42a7 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1686,6 +1686,8 @@ static int i915_sr_status(struct seq_file *m,
>> void *unused)
>>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>>  	else if (IS_PINEVIEW(dev))
>>  		sr_enabled = I915_READ(DSPFW3) &
>>  		PINEVIEW_SELF_REFRESH_EN;
>> +	else
>> +		sr_enabled = true; /* other platforms don't need
>> enabling */
>
> Not true actually.
>
> The line between maxfifo and SR is a blurry one. We treat them as the
> same thing. So I think this should just read out whatever registers
> we set up in intel_set_memory_cxsr().

Ville, does this patch does what you meant with the above sentence. I'm
clueless about self-refresh, so I just paraphrased you in the commit
message.

Ander

---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fece922..d80de9d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1731,6 +1731,8 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev))
 		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+	else if (IS_VALLEYVIEW(dev))
+		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	intel_runtime_pm_put(dev_priv);
 
-- 
2.1.0

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[PATCH] drm/i915: Include G4X/VLV/CHV in self refresh status

[Ander Conselvan de Oliveira]

Add all missing platforms handled by intel_set_memory_cxsr() to the
i915_sr_status debugfs entry.

v2: Add G4X too. (Ville)
    Clarify the change also affects CHV. (Ander)

References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fece922..564a6ba 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1725,12 +1725,15 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 
 	if (HAS_PCH_SPLIT(dev))
 		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
-	else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
+	else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
+		 IS_I945G(dev) || IS_I945GM(dev))
 		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 	else if (IS_I915GM(dev))
 		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev))
 		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+	else if (IS_VALLEYVIEW(dev))
+		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	intel_runtime_pm_put(dev_priv);
 
-- 
2.1.0

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Re: [PATCH] drm/i915: Include G4X/VLV/CHV in self refresh status

[Ville Syrjälä]

On Tue, Jun 02, 2015 at 02:17:47PM +0300, Ander Conselvan de Oliveira wrote:
> Add all missing platforms handled by intel_set_memory_cxsr() to the
> i915_sr_status debugfs entry.
> 
> v2: Add G4X too. (Ville)
>     Clarify the change also affects CHV. (Ander)
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

It's a good enough white lie for my taste. 
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I would also accept removing the entire file, but we can keep it if
people find some use for it.

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fece922..564a6ba 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1725,12 +1725,15 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  
>  	if (HAS_PCH_SPLIT(dev))
>  		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
> -	else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
> +	else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
> +		 IS_I945G(dev) || IS_I945GM(dev))
>  		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
>  	else if (IS_I915GM(dev))
>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>  	else if (IS_PINEVIEW(dev))
>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
> +	else if (IS_VALLEYVIEW(dev))
> +		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  
>  	intel_runtime_pm_put(dev_priv);
>  
> -- 
> 2.1.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915: Include G4X/VLV/CHV in self refresh status

[Jani Nikula]

On Tue, 02 Jun 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Jun 02, 2015 at 02:17:47PM +0300, Ander Conselvan de Oliveira wrote:
>> Add all missing platforms handled by intel_set_memory_cxsr() to the
>> i915_sr_status debugfs entry.
>> 
>> v2: Add G4X too. (Ville)
>>     Clarify the change also affects CHV. (Ander)
>> 
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
>> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
>
> It's a good enough white lie for my taste. 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I would also accept removing the entire file, but we can keep it if
> people find some use for it.

This doesn't do anything for skl, but the bug report is (also) about
skl.

BR,
Jani.


>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index fece922..564a6ba 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1725,12 +1725,15 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>>  
>>  	if (HAS_PCH_SPLIT(dev))
>>  		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
>> -	else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
>> +	else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
>> +		 IS_I945G(dev) || IS_I945GM(dev))
>>  		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
>>  	else if (IS_I915GM(dev))
>>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>>  	else if (IS_PINEVIEW(dev))
>>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>> +	else if (IS_VALLEYVIEW(dev))
>> +		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>>  
>>  	intel_runtime_pm_put(dev_priv);
>>  
>> -- 
>> 2.1.0
>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH] drm/i915: Include G4X/VLV/CHV in self refresh status

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6522
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  303/303              303/303
SNB                 -1              315/315              314/315
IVB                                  343/343              343/343
BYT                                  287/287              287/287
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*SNB  igt@pm_rpm@dpms-mode-unset-non-lpsp      PASS(1)      DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915: Include G4X/VLV/CHV in self refresh status

[Jani Nikula]

On Tue, 02 Jun 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Jun 02, 2015 at 02:17:47PM +0300, Ander Conselvan de Oliveira wrote:
>> Add all missing platforms handled by intel_set_memory_cxsr() to the
>> i915_sr_status debugfs entry.
>> 
>> v2: Add G4X too. (Ville)
>>     Clarify the change also affects CHV. (Ander)
>> 
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
>> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
>
> It's a good enough white lie for my taste. 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pushed to drm-intel-fixes, thanks for the patch and review.

BR,
Jani.

>
> I would also accept removing the entire file, but we can keep it if
> people find some use for it.
>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index fece922..564a6ba 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1725,12 +1725,15 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>>  
>>  	if (HAS_PCH_SPLIT(dev))
>>  		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
>> -	else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
>> +	else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
>> +		 IS_I945G(dev) || IS_I945GM(dev))
>>  		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
>>  	else if (IS_I915GM(dev))
>>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>>  	else if (IS_PINEVIEW(dev))
>>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>> +	else if (IS_VALLEYVIEW(dev))
>> +		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>>  
>>  	intel_runtime_pm_put(dev_priv);
>>  
>> -- 
>> 2.1.0
>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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