From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A270C52D6D for ; Mon, 5 Aug 2024 13:02:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F22510E1D7; Mon, 5 Aug 2024 13:02:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SrjUehLe"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 73BA010E1EA for ; Mon, 5 Aug 2024 13:02:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722862927; x=1754398927; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=mJxVo/eAOwU8FTfLmOuKJV96AQLTRILdugKOSL9TVTI=; b=SrjUehLecAgP7evXwZO970eo0o5fbd0cqcFFxGS4XkEQ0sqOym2XSI6U 7o7GNd9TGca2DMO+xndqBIFJtPGvXAQ8MvVPD9K/OwTclG0cSfBf29CTe Zz0Ony1Gj879+N+xh6fkp0ljYLCnzZXgmcvXYOMeyTdOduz9vusFMrH2A mRbW86vC5RSB7+De830IKTg+nC+0ioTugqt/odpyMX6k13aswdBh9H5ec U0q3e/h7y1/+zRKyCUw7uroiVdLj0ZUwWDS8SS+aK38WTiQd7Pf99Itai OUcQoCAFMK8pT+2DA0ijLTQP4G2RUFCUqlM3Xb5HSWK8G9mpbCnWHjbZs w==; X-CSE-ConnectionGUID: gYZX4UPwTtKtn27Vv3IiJA== X-CSE-MsgGUID: /7YoDN+7Tr25++PYxv9ANQ== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="20968256" X-IronPort-AV: E=Sophos;i="6.09,264,1716274800"; d="scan'208";a="20968256" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 06:02:03 -0700 X-CSE-ConnectionGUID: seiAkn0IQcyJFRLetZ92og== X-CSE-MsgGUID: 9ZV0/ufSQ4+s2ISA/wIONQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,264,1716274800"; d="scan'208";a="56716655" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.180]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 06:02:00 -0700 From: Jani Nikula To: Stanislav Lisovskiy , intel-gfx@lists.freedesktop.org Cc: jani.saarinen@intel.com, Stanislav.Lisovskiy@intel.com Subject: Re: [PATCH] drm/i915: Implement Dbuf overlap detection feature starting from LNL In-Reply-To: <20240805120031.1265-1-stanislav.lisovskiy@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20240805120031.1265-1-stanislav.lisovskiy@intel.com> Date: Mon, 05 Aug 2024 16:01:46 +0300 Message-ID: <87sevj5dj9.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 05 Aug 2024, Stanislav Lisovskiy wrote: > From LNL onwards there is a new hardware feature, which > allows to detect if the driver wrongly allocated DBuf > entries and they happen to overlap. If enabled this will > cause a specific interrupt to occur. > We now handle it in the driver, by writing correspondent > error message to kernel log. > > Signed-off-by: Stanislav Lisovskiy > --- > drivers/gpu/drm/i915/display/intel_display_device.c | 6 ++++++ > drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++ > drivers/gpu/drm/i915/display/intel_display_irq.c | 7 +++++++ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 4 files changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index dd7dce4b0e7a..b4f979bc59cf 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -1457,6 +1457,12 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 > if (IS_DISPLAY_VER(i915, 10, 12) && > (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) > display_runtime->has_dsc = 0; > + > + if (DISPLAY_VER(i915) >= 20 && > + !(dfsm & XE2LPD_DFSM_DBUF_OVERLAP_DISABLE)) > + display_runtime->has_dbuf_overlap_detection = 1; > + else > + display_runtime->has_dbuf_overlap_detection = 0; I'd initialize this to true in the __runtime_defaults init for LNL+, and only set it to false when dfsm says so. Similar to has_dsc above. And nitpick, please use true/false not 1/0 to initialize bool values. (Even though a bunch of code does use 1/0...) BR, Jani. > } > > if (DISPLAY_VER(i915) >= 20) { > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h > index 13453ea4daea..6b94ccd381bc 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > @@ -122,6 +122,7 @@ enum intel_display_subplatform { > #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) > #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13)) > #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) > +#define HAS_DBUF_OVERLAP_DETECTION(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dbuf_overlap_detection) > #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) > #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) > #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) > @@ -216,6 +217,7 @@ struct intel_display_runtime_info { > bool has_hdcp; > bool has_dmc; > bool has_dsc; > + bool has_dbuf_overlap_detection; > }; > > struct intel_display_device_info { > diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c > index 5219ba295c74..e0f1b54d9175 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_irq.c > +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c > @@ -896,6 +896,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) > { > bool found = false; > > + if (HAS_DBUF_OVERLAP_DETECTION(dev_priv)) { > + if (iir & XE2LPD_DBUF_OVERLAP_DETECTED) { > + drm_warn(&dev_priv->drm, "DBuf overlap detected\n"); > + found = true; > + } > + } > + > if (DISPLAY_VER(dev_priv) >= 14) { > if (iir & (XELPDP_PMDEMAND_RSP | > XELPDP_PMDEMAND_RSPTOUT_ERR)) { > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0e3d79227e3c..1e8b04d2f728 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2578,6 +2578,7 @@ > #define GEN8_DE_MISC_GSE REG_BIT(27) > #define GEN8_DE_EDP_PSR REG_BIT(19) > #define XELPDP_PMDEMAND_RSP REG_BIT(3) > +#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1) > > #define GEN8_PCU_ISR _MMIO(0x444e0) > #define GEN8_PCU_IMR _MMIO(0x444e4) > @@ -2863,6 +2864,7 @@ > #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) > #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) > #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) > +#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3) > > #define XE2LPD_DE_CAP _MMIO(0x41100) > #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) -- Jani Nikula, Intel