From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB267C4332F for ; Wed, 19 Oct 2022 23:43:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ACB9D10E8D2; Wed, 19 Oct 2022 23:43:28 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id D85C410E8D2; Wed, 19 Oct 2022 23:43:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666222997; x=1697758997; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=WsGDV6HZsVC/ZfBD66qJonoqyKnGtVIzH6dzcACyOgQ=; b=J1eWxBPZXxW8hErn+wxcQLqCawACIpVyzUNzsfcBwxLuDiGux9Cq50c3 9yMNJymxw263UaSR6hZNETjQovEtcpI7SSO25O4XlD6Csg4XQElVKMG3a LS3bWwwCVTsd6dTOCDBlulUNZi7mEM4AbweyqVTRC+GRcNK+gbPhwtC3g Z7y0ewHWVvlgdoDLsD0L8F+DkdQmPOXk4lFJxZdKES114EXtvqXm7/WMX efofcoBRexOD/KWmNA+ToT11fpUwb/pyOkdUDiz6ajDmhr738JZZQ6Sgy HL7RJZ/x0o7GTmVyhX3qwHReU+85YWsNk0T404GkuUpuWsV1vzfLjF9Cd w==; X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="305294911" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="305294911" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 16:43:17 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="874673029" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="874673029" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.69.147]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 16:43:16 -0700 Date: Wed, 19 Oct 2022 16:43:01 -0700 Message-ID: <87sfjjidmi.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Rodrigo Vivi In-Reply-To: References: <20221019052043.3193842-1-ashutosh.dixit@intel.com> <20221019052043.3193842-3-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 19 Oct 2022 07:58:13 -0700, Rodrigo Vivi wrote: > > On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > > index df21258976d86..5a743ae4dd11e 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > > struct drm_i915_private *i915 = rps_to_i915(rps); > > u32 cagf; > > > > - if (GRAPHICS_VER(i915) >= 12) > > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) > > + cagf = rpstat & MTL_CAGF_MASK; > > I believe we should advocate more the use of the REG_FIELD_GET > > cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat); > > > + else if (GRAPHICS_VER(i915) >= 12) > > cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; > > cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > // witht the proper REG_GENAMSK usage on the gen12_cagf_mask... > > > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > cagf = (rpstat >> 8) & 0xff; > > #define RPE_MASK REG_GENMASK(15, 8) > cagf = REG_FIELD_GET(RPE_MASK, rpstat) All these are now converted to REG_FIELD_GET in series version v8. > > @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps) > > struct intel_uncore *uncore = rps_to_uncore(rps); > ^ > > > u32 freq; > > > > - if (GRAPHICS_VER(i915) >= 12) { > > + /* > > + * For Gen12+ reading freq from HW does not need a forcewake and > > + * registers will return 0 freq when GT is in RC6 > > + */ > > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { > > + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1); > > here we should use directly the local uncore already declared above with > the same helper... and consistent with the following elses... Fixed. > > > + } else if (GRAPHICS_VER(i915) >= 12) { > > freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > > vlv_punit_get(i915); > > -- > > 2.38.0 > > Thanks. -- Ashutosh