From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A871ECAAD8 for ; Wed, 14 Sep 2022 00:19:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BDC6C10E708; Wed, 14 Sep 2022 00:19:30 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 86E6310E708 for ; Wed, 14 Sep 2022 00:19:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663114765; x=1694650765; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=5vJT8TDRpgG239hLMOWwQ6mJ5wyoYXcR8kJ8KIo1H70=; b=SE+8RckHgBUMI+I4vIlubZY9mcBv+n0u8LQWxZwlGmTiP7wvo4mTmxXE 5pRxVerS30iQHhh88gXHQCiMMfTd0OnYwz4hM9nMZi9G0ZfOHwdzJwq3K laauGizqUWtpm7Cbsw4VGLH52rtIXE/iLZBFyg2Xwfs+vY2dQchKHnuq5 aB4+SFc3G1jQXxBtdNlxzs2UEN4FnsvZUSbcUF1PAY/vB++JBoU+EtBW3 CMJX7/zhMwYKEV1sBngm7+Lo/vEC0JSmTc8etgzM7hWvsAgmJZdxEuJ24 Re5macOBWS/oDoxsdaQCMAXH8+xkoqj2ZLW67d3s5J8UsS4PH8xXg0OgO Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10469"; a="298294855" X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="298294855" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2022 17:19:24 -0700 X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="792130117" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.227.17]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2022 17:19:24 -0700 Date: Tue, 13 Sep 2022 17:19:24 -0700 Message-ID: <87sfkuerjn.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20220823204155.8178-6-umesh.nerlige.ramappa@intel.com> References: <20220823204155.8178-1-umesh.nerlige.ramappa@intel.com> <20220823204155.8178-6-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 05/19] drm/i915/perf: Enable commands per clock reporting in OA X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 23 Aug 2022 13:41:41 -0700, Umesh Nerlige Ramappa wrote: > Hi Umesh, > XEHPSDV and DG2 provide a way to configure bytes per clock vs commands > per clock reporting. Enable command per clock setting on enabling OA. What is the reason for selecting commands per clock vs bytes per clock? Also probably mention Bspec: 51762 in the commit message too. > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index efa7eda83edd..6fc4f0d8fc5a 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -2745,10 +2745,12 @@ static int > gen12_enable_metric_set(struct i915_perf_stream *stream, > struct i915_active *active) > { > + struct drm_i915_private *i915 = stream->perf->i915; > struct intel_uncore *uncore = stream->uncore; > struct i915_oa_config *oa_config = stream->oa_config; > bool periodic = stream->periodic; > u32 period_exponent = stream->period_exponent; > + u32 sqcnt1; > int ret; > > intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG, > @@ -2767,6 +2769,16 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, > (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT)) > : 0); > > + /* > + * Initialize Super Queue Internal Cnt Register > + * Set PMON Enable in order to collect valid metrics. > + * Enable commands per clock reporting in OA for XEHPSDV onward. > + */ > + sqcnt1 = GEN12_SQCNT1_PMON_ENABLE | > + (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0); Also from Bspec 0:Unitsof4cmd and 1:Unitsof128B so looks like bit 29 should be set to 0 for commands per clock setting? Or I am wrong? > + > + intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1); > + > /* > * Update all contexts prior writing the mux configurations as we need > * to make sure all slices/subslices are ON before writing to NOA > @@ -2816,6 +2828,8 @@ static void gen11_disable_metric_set(struct i915_perf_stream *stream) > static void gen12_disable_metric_set(struct i915_perf_stream *stream) > { > struct intel_uncore *uncore = stream->uncore; > + struct drm_i915_private *i915 = stream->perf->i915; > + u32 sqcnt1; > > /* Reset all contexts' slices/subslices configurations. */ > gen12_configure_all_contexts(stream, NULL, NULL); > @@ -2826,6 +2840,12 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream) > > /* Make sure we disable noa to save power. */ > intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0); > + > + sqcnt1 = GEN12_SQCNT1_PMON_ENABLE | > + (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0); > + > + /* Reset PMON Enable to save power. */ > + intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0); > } > > static void gen7_oa_enable(struct i915_perf_stream *stream) > diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h > index 0ef3562ff4aa..381d94101610 100644 > --- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h > +++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h > @@ -134,4 +134,8 @@ > #define GDT_CHICKEN_BITS _MMIO(0x9840) > #define GT_NOA_ENABLE 0x00000080 > > +#define GEN12_SQCNT1 _MMIO(0x8718) > +#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30) > +#define GEN12_SQCNT1_OABPC REG_BIT(29) > + > #endif /* __INTEL_PERF_OA_REGS__ */