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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 07/11] drm/i915: Store the m2 divider as a whole in bxt_clk_div X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 01 Mar 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Get rid of the pointless m2 int vs. frac split in bxt_clk_div > and just store the whole divider as one. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 33 +++++++++++-------- > 1 file changed, 19 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/= drm/i915/display/intel_dpll_mgr.c > index 899aa42a858f..4a82e630cbec 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -2085,8 +2085,7 @@ struct bxt_clk_div { > int clock; > u32 p1; > u32 p2; > - u32 m2_int; > - u32 m2_frac; > + u32 m2; > u32 n; >=20=20 > int vco; > @@ -2094,13 +2093,20 @@ struct bxt_clk_div { >=20=20 > /* pre-calculated values for DP linkrates */ > static const struct bxt_clk_div bxt_dp_clk_val[] =3D { > - { .clock =3D 162000, .p1 =3D 4, .p2 =3D 2, .m2_int =3D 32, .m2_frac =3D= 1677722, .n =3D 1, }, > - { .clock =3D 270000, .p1 =3D 4, .p2 =3D 1, .m2_int =3D 27, .m2_frac =3D= 0, .n =3D 1, }, > - { .clock =3D 540000, .p1 =3D 2, .p2 =3D 1, .m2_int =3D 27, .m2_frac =3D= 0, .n =3D 1, }, > - { .clock =3D 216000, .p1 =3D 3, .p2 =3D 2, .m2_int =3D 32, .m2_frac =3D= 1677722, .n =3D 1, }, > - { .clock =3D 243000, .p1 =3D 4, .p2 =3D 1, .m2_int =3D 24, .m2_frac =3D= 1258291, .n =3D 1, }, > - { .clock =3D 324000, .p1 =3D 4, .p2 =3D 1, .m2_int =3D 32, .m2_frac =3D= 1677722, .n =3D 1, }, > - { .clock =3D 432000, .p1 =3D 3, .p2 =3D 1, .m2_int =3D 32, .m2_frac =3D= 1677722, .n =3D 1, }, > + { .clock =3D 162000, .p1 =3D 4, .p2 =3D 2, .n =3D 1, > + .m2 =3D 0x819999a /* .m2_int =3D 32, m2_frac =3D 1677722 */ }, > + { .clock =3D 270000, .p1 =3D 4, .p2 =3D 1, .n =3D 1, > + .m2 =3D 0x6c00000 /* .m2_int =3D 27, m2_frac =3D 0 */ }, > + { .clock =3D 540000, .p1 =3D 2, .p2 =3D 1, .n =3D 1, > + .m2 =3D 0x6c00000 /* .m2_int =3D 27, m2_frac =3D 0 */ }, > + { .clock =3D 216000, .p1 =3D 3, .p2 =3D 2, .n =3D 1, > + .m2 =3D 0x819999a /* .m2_int =3D 32, m2_frac =3D 1677722 */ }, > + { .clock =3D 243000, .p1 =3D 4, .p2 =3D 1, .n =3D 1, > + .m2 =3D 0x6133333 /* .m2_int =3D 24, m2_frac =3D 1258291 */ }, > + { .clock =3D 324000, .p1 =3D 4, .p2 =3D 1, .n =3D 1, > + .m2 =3D 0x819999a /* .m2_int =3D 32, m2_frac =3D 1677722 */ }, > + { .clock =3D 432000, .p1 =3D 3, .p2 =3D 1, .n =3D 1, > + .m2 =3D 0x819999a /* .m2_int =3D 32, m2_frac =3D 1677722 */ }, Mmh, I guess here I would've added some macros to construct m2 from m2_int and m2_frac. #define M2_INT_SHIFT 22 #define M2_FRAC_MASK 0x3fffff #define M2(int, frac) ((int) << M2_INT_SHIFT) | (frac)) And you get this: { .clock =3D 432000, .p1 =3D 3, .p2 =3D 1, .m2 =3D M2(32, 1677722), .n =3D= 1, }, No need to retain the int/frac in comments. Can also use REG_FIELD_PREP/GET if you want to over-engineer... > }; >=20=20 > static bool > @@ -2127,8 +2133,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *= crtc_state, > clk_div->p2 =3D best_clock.p2; > drm_WARN_ON(&i915->drm, best_clock.m1 !=3D 2); > clk_div->n =3D best_clock.n; > - clk_div->m2_int =3D best_clock.m2 >> 22; > - clk_div->m2_frac =3D best_clock.m2 & ((1 << 22) - 1); > + clk_div->m2 =3D best_clock.m2; >=20=20 > clk_div->vco =3D best_clock.vco; >=20=20 > @@ -2197,11 +2202,11 @@ static bool bxt_ddi_set_dpll_hw_state(struct inte= l_crtc_state *crtc_state, > lanestagger =3D 0x02; >=20=20 > dpll_hw_state->ebb0 =3D PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div-= >p2); > - dpll_hw_state->pll0 =3D clk_div->m2_int; > + dpll_hw_state->pll0 =3D clk_div->m2 >> 22; > dpll_hw_state->pll1 =3D PORT_PLL_N(clk_div->n); > - dpll_hw_state->pll2 =3D clk_div->m2_frac; > + dpll_hw_state->pll2 =3D clk_div->m2 & 0x3fffff; >=20=20 > - if (clk_div->m2_frac) > + if (clk_div->m2 & 0x3fffff) > dpll_hw_state->pll3 =3D PORT_PLL_M2_FRAC_ENABLE; Also could reuse the shift and mask macros here. Other than that, the direction seems good. BR, Jani. >=20=20 > dpll_hw_state->pll6 =3D prop_coef | PORT_PLL_INT_COEFF(int_coef); --=20 Jani Nikula, Intel Open Source Graphics Center