From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n Date: Tue, 16 Oct 2012 14:49:58 +0300 Message-ID: <87sj9ek55l.fsf@intel.com> References: <1350327102-4463-1-git-send-email-przanoni@gmail.com> <1350327102-4463-8-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id AD50B9EB5C for ; Tue, 16 Oct 2012 04:50:02 -0700 (PDT) In-Reply-To: <1350327102-4463-8-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni , intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Mon, 15 Oct 2012, Paulo Zanoni wrote: > From: Paulo Zanoni > > Much simpler and looks more like the M/N code inside intel_display.c. Reviewed-by: Jani Nikula > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_dp.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index b10f35b..52b5453 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -794,9 +794,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, > mode->clock, adjusted_mode->clock, &m_n); > > if (HAS_PCH_SPLIT(dev)) { > - I915_WRITE(TRANSDATA_M1(pipe), > - ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | > - m_n.gmch_m); > + I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); > I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); > I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); > I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); > @@ -807,8 +805,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, > I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); > } else { > I915_WRITE(PIPE_GMCH_DATA_M(pipe), > - ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | > - m_n.gmch_m); > + TU_SIZE(m_n.tu) | m_n.gmch_m); > I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); > I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); > I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx