From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Anholt Subject: Re: [PATCH 9/9] drm/i915: swizzling support for snb/ivb Date: Fri, 11 Nov 2011 08:50:30 -0800 Message-ID: <87sjluob6x.fsf@eliezer.anholt.net> References: <1320931087-1557-1-git-send-email-daniel.vetter@ffwll.ch> <1320931087-1557-10-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0652590456==" Return-path: In-Reply-To: <1320931087-1557-10-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org --===============0652590456== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha1; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Thu, 10 Nov 2011 14:18:07 +0100, Daniel Vetter = wrote: > We have to do this manually. Somebody had a Great Idea. >=20 > Signed-Off-by: Daniel Vetter People playing with this when not strictly required is scary to me. Manually swizzling was a world of hurt. I got to play with things like "when the management engine is enabled, it carves out the top N MB of one of the dimms, and the corresponding N MB of the other dimm doesn't get swizzled, and you lose". > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i91= 5/i915_gem_tiling.c > index 861223b..af0a2fc 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -93,8 +93,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) > uint32_t swizzle_y =3D I915_BIT_6_SWIZZLE_UNKNOWN; >=20=20 > if (INTEL_INFO(dev)->gen >=3D 6) { > - swizzle_x =3D I915_BIT_6_SWIZZLE_NONE; > - swizzle_y =3D I915_BIT_6_SWIZZLE_NONE; > + uint32_t dimm_c0, dimm_c1; > + dimm_c0 =3D I915_READ(MAD_DIMM_C0); > + dimm_c1 =3D I915_READ(MAD_DIMM_C1); > + dimm_c0 &=3D MAD_DIMM_A_SIZE_MASK | MAD_DIMM_A_SIZE_MASK; > + dimm_c1 &=3D MAD_DIMM_A_SIZE_MASK | MAD_DIMM_A_SIZE_MASK; > + /* Enable swizzling when the channels are populated with > + * identically sized dimms. */ > + if (dimm_c0 =3D=3D dimm_c1) { > + swizzle_x =3D I915_BIT_6_SWIZZLE_9_10; > + swizzle_y =3D I915_BIT_6_SWIZZLE_9; > + } else { > + swizzle_x =3D I915_BIT_6_SWIZZLE_NONE; > + swizzle_y =3D I915_BIT_6_SWIZZLE_NONE; > + } > } else if (IS_GEN5(dev)) { > /* On Ironlake whatever DRAM config, GPU always do > * same swizzling setup. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 0a0b6b1..a62fa95 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -327,6 +327,8 @@ > #define ARB_MODE 0x04030 > #define ARB_MODE_SWIZZLE_SNB (1<<4) > #define ARB_MODE_SWIZZLE_IVB (1<<5) > +#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) > +#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) > #define RENDER_HWS_PGA_GEN7 (0x04080) > #define BSD_HWS_PGA_GEN7 (0x04180) > #define BLT_HWS_PGA_GEN7 (0x04280) --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iEYEARECAAYFAk69UlYACgkQHUdvYGzw6vd4lgCfeD2wI1Us6h/6B3caLnQV5UUd KjUAoI28BPcPEmDSdl+mR3ScuPW+uzoE =OQxa -----END PGP SIGNATURE----- --=-=-=-- --===============0652590456== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0652590456==--