* [PATCH 1/9] drm/i915/color: prefer display->platform.<platform> checks
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-12 5:01 ` Shankar, Uma
2025-03-11 18:00 ` [PATCH 2/9] drm/i915/connector: convert intel_connector.c to struct intel_display Jani Nikula
` (17 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
This let's us drop the dependency on i915_drv.h.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index cfe14162231d..bbf6df7ebb95 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -22,7 +22,7 @@
*
*/
-#include "i915_drv.h"
+#include "i915_utils.h"
#include "i9xx_plane_regs.h"
#include "intel_color.h"
#include "intel_color_regs.h"
@@ -405,14 +405,13 @@ static void icl_read_csc(struct intel_crtc_state *crtc_state)
static bool ilk_limited_range(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- struct drm_i915_private *i915 = to_i915(display->drm);
/* icl+ have dedicated output CSC */
if (DISPLAY_VER(display) >= 11)
return false;
/* pre-hsw have TRANSCONF_COLOR_RANGE_SELECT */
- if (DISPLAY_VER(display) < 7 || IS_IVYBRIDGE(i915))
+ if (DISPLAY_VER(display) < 7 || display->platform.ivybridge)
return false;
return crtc_state->limited_color_range;
@@ -516,7 +515,6 @@ static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
static void ilk_assign_csc(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- struct drm_i915_private *i915 = to_i915(display->drm);
bool limited_color_range = ilk_csc_limited_range(crtc_state);
if (crtc_state->hw.ctm) {
@@ -538,7 +536,7 @@ static void ilk_assign_csc(struct intel_crtc_state *crtc_state)
* LUT is needed but CSC is not we need to load an
* identity matrix.
*/
- drm_WARN_ON(display->drm, !IS_GEMINILAKE(i915));
+ drm_WARN_ON(display->drm, !display->platform.geminilake);
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_identity);
} else {
@@ -3983,12 +3981,10 @@ int intel_color_init(struct intel_display *display)
void intel_color_init_hooks(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
if (HAS_GMCH(display)) {
- if (IS_CHERRYVIEW(i915))
+ if (display->platform.cherryview)
display->funcs.color = &chv_color_funcs;
- else if (IS_VALLEYVIEW(i915))
+ else if (display->platform.valleyview)
display->funcs.color = &vlv_color_funcs;
else if (DISPLAY_VER(display) >= 4)
display->funcs.color = &i965_color_funcs;
@@ -4005,7 +4001,7 @@ void intel_color_init_hooks(struct intel_display *display)
display->funcs.color = &skl_color_funcs;
else if (DISPLAY_VER(display) == 8)
display->funcs.color = &bdw_color_funcs;
- else if (IS_HASWELL(i915))
+ else if (display->platform.haswell)
display->funcs.color = &hsw_color_funcs;
else if (DISPLAY_VER(display) == 7)
display->funcs.color = &ivb_color_funcs;
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* RE: [PATCH 1/9] drm/i915/color: prefer display->platform.<platform> checks
2025-03-11 18:00 ` [PATCH 1/9] drm/i915/color: prefer display->platform.<platform> checks Jani Nikula
@ 2025-03-12 5:01 ` Shankar, Uma
0 siblings, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 5:01 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 1/9] drm/i915/color: prefer display->platform.<platform> checks
>
> This let's us drop the dependency on i915_drv.h.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++----------
> 1 file changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index cfe14162231d..bbf6df7ebb95 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -22,7 +22,7 @@
> *
> */
>
> -#include "i915_drv.h"
> +#include "i915_utils.h"
> #include "i9xx_plane_regs.h"
> #include "intel_color.h"
> #include "intel_color_regs.h"
> @@ -405,14 +405,13 @@ static void icl_read_csc(struct intel_crtc_state
> *crtc_state) static bool ilk_limited_range(const struct intel_crtc_state
> *crtc_state) {
> struct intel_display *display = to_intel_display(crtc_state);
> - struct drm_i915_private *i915 = to_i915(display->drm);
>
> /* icl+ have dedicated output CSC */
> if (DISPLAY_VER(display) >= 11)
> return false;
>
> /* pre-hsw have TRANSCONF_COLOR_RANGE_SELECT */
> - if (DISPLAY_VER(display) < 7 || IS_IVYBRIDGE(i915))
> + if (DISPLAY_VER(display) < 7 || display->platform.ivybridge)
> return false;
>
> return crtc_state->limited_color_range; @@ -516,7 +515,6 @@ static
> void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, static void
> ilk_assign_csc(struct intel_crtc_state *crtc_state) {
> struct intel_display *display = to_intel_display(crtc_state);
> - struct drm_i915_private *i915 = to_i915(display->drm);
> bool limited_color_range = ilk_csc_limited_range(crtc_state);
>
> if (crtc_state->hw.ctm) {
> @@ -538,7 +536,7 @@ static void ilk_assign_csc(struct intel_crtc_state
> *crtc_state)
> * LUT is needed but CSC is not we need to load an
> * identity matrix.
> */
> - drm_WARN_ON(display->drm, !IS_GEMINILAKE(i915));
> + drm_WARN_ON(display->drm, !display->platform.geminilake);
>
> ilk_csc_copy(display, &crtc_state->csc,
> &ilk_csc_matrix_identity);
> } else {
> @@ -3983,12 +3981,10 @@ int intel_color_init(struct intel_display *display)
>
> void intel_color_init_hooks(struct intel_display *display) {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> -
> if (HAS_GMCH(display)) {
> - if (IS_CHERRYVIEW(i915))
> + if (display->platform.cherryview)
> display->funcs.color = &chv_color_funcs;
> - else if (IS_VALLEYVIEW(i915))
> + else if (display->platform.valleyview)
> display->funcs.color = &vlv_color_funcs;
> else if (DISPLAY_VER(display) >= 4)
> display->funcs.color = &i965_color_funcs; @@ -4005,7
> +4001,7 @@ void intel_color_init_hooks(struct intel_display *display)
> display->funcs.color = &skl_color_funcs;
> else if (DISPLAY_VER(display) == 8)
> display->funcs.color = &bdw_color_funcs;
> - else if (IS_HASWELL(i915))
> + else if (display->platform.haswell)
> display->funcs.color = &hsw_color_funcs;
> else if (DISPLAY_VER(display) == 7)
> display->funcs.color = &ivb_color_funcs;
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 2/9] drm/i915/connector: convert intel_connector.c to struct intel_display
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
2025-03-11 18:00 ` [PATCH 1/9] drm/i915/color: prefer display->platform.<platform> checks Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-12 5:06 ` Shankar, Uma
2025-03-11 18:00 ` [PATCH 3/9] drm/i915/hotplug: convert intel_hotplug.[ch] " Jani Nikula
` (16 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_connector.c to struct
intel_display. i915_inject_probe_failure() remains the only call that
requires i915 pointer.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_connector.c | 45 ++++++++++---------
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c
index e42357bd9e80..6c81c9f2fd09 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -31,8 +31,10 @@
#include <drm/drm_probe_helper.h>
#include "i915_drv.h"
+#include "i915_utils.h"
#include "intel_backlight.h"
#include "intel_connector.h"
+#include "intel_display_core.h"
#include "intel_display_debugfs.h"
#include "intel_display_types.h"
#include "intel_hdcp.h"
@@ -154,13 +156,14 @@ void intel_connector_destroy(struct drm_connector *connector)
int intel_connector_register(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct drm_i915_private *i915 = to_i915(connector->dev);
int ret;
ret = intel_backlight_device_register(intel_connector);
if (ret)
goto err;
- if (i915_inject_probe_failure(to_i915(connector->dev))) {
+ if (i915_inject_probe_failure(i915)) {
ret = -EFAULT;
goto err_backlight;
}
@@ -204,10 +207,10 @@ bool intel_connector_get_hw_state(struct intel_connector *connector)
enum pipe intel_connector_get_pipe(struct intel_connector *connector)
{
- struct drm_device *dev = connector->base.dev;
+ struct intel_display *display = to_intel_display(connector);
- drm_WARN_ON(dev,
- !drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+ drm_WARN_ON(display->drm,
+ !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
if (!connector->base.state->crtc)
return INVALID_PIPE;
@@ -264,20 +267,19 @@ static const struct drm_prop_enum_list force_audio_names[] = {
void
intel_attach_force_audio_property(struct drm_connector *connector)
{
- struct drm_device *dev = connector->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_property *prop;
- prop = dev_priv->display.properties.force_audio;
+ prop = display->properties.force_audio;
if (prop == NULL) {
- prop = drm_property_create_enum(dev, 0,
- "audio",
- force_audio_names,
- ARRAY_SIZE(force_audio_names));
+ prop = drm_property_create_enum(display->drm, 0,
+ "audio",
+ force_audio_names,
+ ARRAY_SIZE(force_audio_names));
if (prop == NULL)
return;
- dev_priv->display.properties.force_audio = prop;
+ display->properties.force_audio = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
}
@@ -291,20 +293,19 @@ static const struct drm_prop_enum_list broadcast_rgb_names[] = {
void
intel_attach_broadcast_rgb_property(struct drm_connector *connector)
{
- struct drm_device *dev = connector->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_property *prop;
- prop = dev_priv->display.properties.broadcast_rgb;
+ prop = display->properties.broadcast_rgb;
if (prop == NULL) {
- prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
- "Broadcast RGB",
- broadcast_rgb_names,
- ARRAY_SIZE(broadcast_rgb_names));
+ prop = drm_property_create_enum(display->drm, DRM_MODE_PROP_ENUM,
+ "Broadcast RGB",
+ broadcast_rgb_names,
+ ARRAY_SIZE(broadcast_rgb_names));
if (prop == NULL)
return;
- dev_priv->display.properties.broadcast_rgb = prop;
+ display->properties.broadcast_rgb = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
@@ -336,14 +337,14 @@ intel_attach_dp_colorspace_property(struct drm_connector *connector)
void
intel_attach_scaling_mode_property(struct drm_connector *connector)
{
- struct drm_i915_private *i915 = to_i915(connector->dev);
+ struct intel_display *display = to_intel_display(connector->dev);
u32 scaling_modes;
scaling_modes = BIT(DRM_MODE_SCALE_ASPECT) |
BIT(DRM_MODE_SCALE_FULLSCREEN);
/* On GMCH platforms borders are only possible on the LVDS port */
- if (!HAS_GMCH(i915) || connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
+ if (!HAS_GMCH(display) || connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
scaling_modes |= BIT(DRM_MODE_SCALE_CENTER);
drm_connector_attach_scaling_mode_property(connector, scaling_modes);
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* RE: [PATCH 2/9] drm/i915/connector: convert intel_connector.c to struct intel_display
2025-03-11 18:00 ` [PATCH 2/9] drm/i915/connector: convert intel_connector.c to struct intel_display Jani Nikula
@ 2025-03-12 5:06 ` Shankar, Uma
0 siblings, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 5:06 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 2/9] drm/i915/connector: convert intel_connector.c to struct
> intel_display
>
> Going forward, struct intel_display is the main display device data pointer.
> Convert as much as possible of intel_connector.c to struct intel_display.
> i915_inject_probe_failure() remains the only call that requires i915 pointer.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_connector.c | 45 ++++++++++---------
> 1 file changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_connector.c
> b/drivers/gpu/drm/i915/display/intel_connector.c
> index e42357bd9e80..6c81c9f2fd09 100644
> --- a/drivers/gpu/drm/i915/display/intel_connector.c
> +++ b/drivers/gpu/drm/i915/display/intel_connector.c
> @@ -31,8 +31,10 @@
> #include <drm/drm_probe_helper.h>
>
> #include "i915_drv.h"
> +#include "i915_utils.h"
> #include "intel_backlight.h"
> #include "intel_connector.h"
> +#include "intel_display_core.h"
> #include "intel_display_debugfs.h"
> #include "intel_display_types.h"
> #include "intel_hdcp.h"
> @@ -154,13 +156,14 @@ void intel_connector_destroy(struct drm_connector
> *connector) int intel_connector_register(struct drm_connector *connector) {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> + struct drm_i915_private *i915 = to_i915(connector->dev);
> int ret;
>
> ret = intel_backlight_device_register(intel_connector);
> if (ret)
> goto err;
>
> - if (i915_inject_probe_failure(to_i915(connector->dev))) {
> + if (i915_inject_probe_failure(i915)) {
> ret = -EFAULT;
> goto err_backlight;
> }
> @@ -204,10 +207,10 @@ bool intel_connector_get_hw_state(struct
> intel_connector *connector)
>
> enum pipe intel_connector_get_pipe(struct intel_connector *connector) {
> - struct drm_device *dev = connector->base.dev;
> + struct intel_display *display = to_intel_display(connector);
>
> - drm_WARN_ON(dev,
> - !drm_modeset_is_locked(&dev-
> >mode_config.connection_mutex));
> + drm_WARN_ON(display->drm,
> +
> +!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
>
> if (!connector->base.state->crtc)
> return INVALID_PIPE;
> @@ -264,20 +267,19 @@ static const struct drm_prop_enum_list
> force_audio_names[] = { void intel_attach_force_audio_property(struct
> drm_connector *connector) {
> - struct drm_device *dev = connector->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_property *prop;
>
> - prop = dev_priv->display.properties.force_audio;
> + prop = display->properties.force_audio;
> if (prop == NULL) {
> - prop = drm_property_create_enum(dev, 0,
> - "audio",
> - force_audio_names,
> - ARRAY_SIZE(force_audio_names));
> + prop = drm_property_create_enum(display->drm, 0,
> + "audio",
> + force_audio_names,
> +
> ARRAY_SIZE(force_audio_names));
> if (prop == NULL)
> return;
>
> - dev_priv->display.properties.force_audio = prop;
> + display->properties.force_audio = prop;
> }
> drm_object_attach_property(&connector->base, prop, 0); } @@ -291,20
> +293,19 @@ static const struct drm_prop_enum_list broadcast_rgb_names[] = {
> void intel_attach_broadcast_rgb_property(struct drm_connector *connector) {
> - struct drm_device *dev = connector->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_property *prop;
>
> - prop = dev_priv->display.properties.broadcast_rgb;
> + prop = display->properties.broadcast_rgb;
> if (prop == NULL) {
> - prop = drm_property_create_enum(dev,
> DRM_MODE_PROP_ENUM,
> - "Broadcast RGB",
> - broadcast_rgb_names,
> - ARRAY_SIZE(broadcast_rgb_names));
> + prop = drm_property_create_enum(display->drm,
> DRM_MODE_PROP_ENUM,
> + "Broadcast RGB",
> + broadcast_rgb_names,
> +
> ARRAY_SIZE(broadcast_rgb_names));
> if (prop == NULL)
> return;
>
> - dev_priv->display.properties.broadcast_rgb = prop;
> + display->properties.broadcast_rgb = prop;
> }
>
> drm_object_attach_property(&connector->base, prop, 0); @@ -336,14
> +337,14 @@ intel_attach_dp_colorspace_property(struct drm_connector
> *connector) void intel_attach_scaling_mode_property(struct drm_connector
> *connector) {
> - struct drm_i915_private *i915 = to_i915(connector->dev);
> + struct intel_display *display = to_intel_display(connector->dev);
> u32 scaling_modes;
>
> scaling_modes = BIT(DRM_MODE_SCALE_ASPECT) |
> BIT(DRM_MODE_SCALE_FULLSCREEN);
>
> /* On GMCH platforms borders are only possible on the LVDS port */
> - if (!HAS_GMCH(i915) || connector->connector_type ==
> DRM_MODE_CONNECTOR_LVDS)
> + if (!HAS_GMCH(display) || connector->connector_type ==
> +DRM_MODE_CONNECTOR_LVDS)
> scaling_modes |= BIT(DRM_MODE_SCALE_CENTER);
>
> drm_connector_attach_scaling_mode_property(connector,
> scaling_modes);
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 3/9] drm/i915/hotplug: convert intel_hotplug.[ch] to struct intel_display
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
2025-03-11 18:00 ` [PATCH 1/9] drm/i915/color: prefer display->platform.<platform> checks Jani Nikula
2025-03-11 18:00 ` [PATCH 2/9] drm/i915/connector: convert intel_connector.c to struct intel_display Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-12 5:13 ` Shankar, Uma
2025-03-11 18:00 ` [PATCH 4/9] drm/i915/hotplug: convert hotplug debugfs " Jani Nikula
` (15 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_hotplug.[ch] to struct
intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../drm/i915/display/intel_display_driver.c | 14 +-
.../i915/display/intel_display_power_well.c | 6 +-
.../drm/i915/display/intel_display_reset.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 332 ++++++++++--------
drivers/gpu/drm/i915/display/intel_hotplug.h | 26 +-
.../gpu/drm/i915/display/intel_hotplug_irq.c | 24 +-
drivers/gpu/drm/i915/i915_driver.c | 14 +-
drivers/gpu/drm/i915/i915_irq.c | 3 +-
drivers/gpu/drm/xe/display/xe_display.c | 26 +-
11 files changed, 240 insertions(+), 213 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index fdedf65bee53..f42b5a69eed5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -844,7 +844,7 @@ void intel_display_debugfs_register(struct intel_display *display)
intel_dmc_debugfs_register(display);
intel_dp_test_debugfs_register(display);
intel_fbc_debugfs_register(display);
- intel_hpd_debugfs_register(i915);
+ intel_hpd_debugfs_register(display);
intel_opregion_debugfs_register(display);
intel_psr_debugfs_register(display);
intel_wm_debugfs_register(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 31740a677dd8..ae60ccb21520 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -315,11 +315,9 @@ static void set_display_access(struct intel_display *display,
*/
void intel_display_driver_enable_user_access(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
set_display_access(display, true, NULL);
- intel_hpd_enable_detection_work(i915);
+ intel_hpd_enable_detection_work(display);
}
/**
@@ -341,9 +339,7 @@ void intel_display_driver_enable_user_access(struct intel_display *display)
*/
void intel_display_driver_disable_user_access(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
- intel_hpd_disable_detection_work(i915);
+ intel_hpd_disable_detection_work(display);
set_display_access(display, false, current);
}
@@ -524,7 +520,7 @@ int intel_display_driver_probe(struct intel_display *display)
intel_overlay_setup(display);
/* Only enable hotplug handling once the fbdev is fully set up. */
- intel_hpd_init(i915);
+ intel_hpd_init(display);
skl_watermark_ipc_init(i915);
@@ -558,7 +554,7 @@ void intel_display_driver_register(struct intel_display *display)
* fbdev->async_cookie.
*/
drm_kms_helper_poll_init(display->drm);
- intel_hpd_poll_disable(i915);
+ intel_hpd_poll_disable(display);
intel_fbdev_setup(i915);
@@ -600,7 +596,7 @@ void intel_display_driver_remove_noirq(struct intel_display *display)
* Due to the hpd irq storm handling the hotplug work can re-arm the
* poll handlers. Hence disable polling after hpd handling is shut down.
*/
- intel_hpd_poll_fini(i915);
+ intel_hpd_poll_fini(display);
intel_unregister_dsm_handler();
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 8ec87ffd87d2..daf2a0cbb157 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1236,8 +1236,8 @@ static void vlv_display_power_well_init(struct intel_display *display)
if (display->power.domains.initializing)
return;
- intel_hpd_init(dev_priv);
- intel_hpd_poll_disable(dev_priv);
+ intel_hpd_init(display);
+ intel_hpd_poll_disable(display);
/* Re-enable the ADPA, if we have one */
for_each_intel_encoder(display->drm, encoder) {
@@ -1265,7 +1265,7 @@ static void vlv_display_power_well_deinit(struct intel_display *display)
/* Prevent us from re-enabling polling on accident in late suspend */
if (!display->drm->dev->power.is_suspended)
- intel_hpd_poll_enable(dev_priv);
+ intel_hpd_poll_enable(display);
}
static void vlv_display_power_well_enable(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c
index 1f2798404f2c..1dbd3e841df3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reset.c
+++ b/drivers/gpu/drm/i915/display/intel_display_reset.c
@@ -107,14 +107,14 @@ void intel_display_reset_finish(struct intel_display *display, bool test_only)
intel_display_driver_init_hw(display);
intel_clock_gating_init(i915);
intel_cx0_pll_power_save_wa(display);
- intel_hpd_init(i915);
+ intel_hpd_init(display);
ret = __intel_display_driver_resume(display, state, ctx);
if (ret)
drm_err(display->drm,
"Restoring old state failed with %i\n", ret);
- intel_hpd_poll_disable(i915);
+ intel_hpd_poll_disable(display);
}
drm_atomic_state_put(state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a236b5fc7a3d..7d074770d793 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6117,7 +6117,7 @@ static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
spin_unlock_irq(&i915->irq_lock);
if (need_work)
- intel_hpd_schedule_detection(i915);
+ intel_hpd_schedule_detection(display);
}
static const struct drm_connector_funcs intel_dp_connector_funcs = {
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index c69b1f5fd160..9bde28ce1979 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -118,7 +118,7 @@ intel_connector_hpd_pin(struct intel_connector *connector)
/**
* intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin
- * @dev_priv: private driver data pointer
+ * @display: display device
* @pin: the pin to gather stats on
* @long_hpd: whether the HPD IRQ was long or short
*
@@ -127,13 +127,13 @@ intel_connector_hpd_pin(struct intel_connector *connector)
* responsible for further action.
*
* The number of IRQs that are allowed within @HPD_STORM_DETECT_PERIOD is
- * stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
+ * stored in @display->hotplug.hpd_storm_threshold which defaults to
* @HPD_STORM_DEFAULT_THRESHOLD. Long IRQs count as +10 to this threshold, and
* short IRQs count as +1. If this threshold is exceeded, it's considered an
* IRQ storm and the IRQ state is set to @HPD_MARK_DISABLED.
*
* By default, most systems will only count long IRQs towards
- * &dev_priv->display.hotplug.hpd_storm_threshold. However, some older systems also
+ * &display->hotplug.hpd_storm_threshold. However, some older systems also
* suffer from short IRQ storms and must also track these. Because short IRQ
* storms are naturally caused by sideband interactions with DP MST devices,
* short IRQ detection is only enabled for systems without DP MST support.
@@ -145,10 +145,10 @@ intel_connector_hpd_pin(struct intel_connector *connector)
*
* Return true if an IRQ storm was detected on @pin.
*/
-static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
+static bool intel_hpd_irq_storm_detect(struct intel_display *display,
enum hpd_pin pin, bool long_hpd)
{
- struct intel_hotplug *hpd = &dev_priv->display.hotplug;
+ struct intel_hotplug *hpd = &display->hotplug;
unsigned long start = hpd->stats[pin].last_jiffies;
unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
const int increment = long_hpd ? 10 : 1;
@@ -156,7 +156,7 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
bool storm = false;
if (!threshold ||
- (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled))
+ (!long_hpd && !display->hotplug.hpd_short_storm_enabled))
return false;
if (!time_in_range(jiffies, start, end)) {
@@ -167,11 +167,11 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
hpd->stats[pin].count += increment;
if (hpd->stats[pin].count > threshold) {
hpd->stats[pin].state = HPD_MARK_DISABLED;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"HPD interrupt storm detected on PIN %d\n", pin);
storm = true;
} else {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Received HPD interrupt on PIN %d - cnt: %d\n",
pin,
hpd->stats[pin].count);
@@ -180,56 +180,65 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
return storm;
}
-static bool detection_work_enabled(struct drm_i915_private *i915)
+static bool detection_work_enabled(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
lockdep_assert_held(&i915->irq_lock);
- return i915->display.hotplug.detection_work_enabled;
+ return display->hotplug.detection_work_enabled;
}
static bool
-mod_delayed_detection_work(struct drm_i915_private *i915, struct delayed_work *work, int delay)
+mod_delayed_detection_work(struct intel_display *display, struct delayed_work *work, int delay)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
lockdep_assert_held(&i915->irq_lock);
- if (!detection_work_enabled(i915))
+ if (!detection_work_enabled(display))
return false;
return mod_delayed_work(i915->unordered_wq, work, delay);
}
static bool
-queue_delayed_detection_work(struct drm_i915_private *i915, struct delayed_work *work, int delay)
+queue_delayed_detection_work(struct intel_display *display, struct delayed_work *work, int delay)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
lockdep_assert_held(&i915->irq_lock);
- if (!detection_work_enabled(i915))
+ if (!detection_work_enabled(display))
return false;
return queue_delayed_work(i915->unordered_wq, work, delay);
}
static bool
-queue_detection_work(struct drm_i915_private *i915, struct work_struct *work)
+queue_detection_work(struct intel_display *display, struct work_struct *work)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
lockdep_assert_held(&i915->irq_lock);
- if (!detection_work_enabled(i915))
+ if (!detection_work_enabled(display))
return false;
return queue_work(i915->unordered_wq, work);
}
static void
-intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
+intel_hpd_irq_storm_switch_to_polling(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
bool hpd_disabled = false;
lockdep_assert_held(&dev_priv->irq_lock);
- drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
enum hpd_pin pin;
@@ -238,15 +247,15 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
pin = intel_connector_hpd_pin(connector);
if (pin == HPD_NONE ||
- dev_priv->display.hotplug.stats[pin].state != HPD_MARK_DISABLED)
+ display->hotplug.stats[pin].state != HPD_MARK_DISABLED)
continue;
- drm_info(&dev_priv->drm,
+ drm_info(display->drm,
"HPD interrupt storm detected on connector %s: "
"switching from hotplug detection to polling\n",
connector->base.name);
- dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
+ display->hotplug.stats[pin].state = HPD_DISABLED;
connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT;
hpd_disabled = true;
@@ -255,18 +264,18 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
/* Enable polling and queue hotplug re-enabling. */
if (hpd_disabled) {
- drm_kms_helper_poll_reschedule(&dev_priv->drm);
- mod_delayed_detection_work(dev_priv,
- &dev_priv->display.hotplug.reenable_work,
+ drm_kms_helper_poll_reschedule(display->drm);
+ mod_delayed_detection_work(display,
+ &display->hotplug.reenable_work,
msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
}
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
{
- struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv),
- display.hotplug.reenable_work.work);
+ struct intel_display *display =
+ container_of(work, typeof(*display), hotplug.reenable_work.work);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
intel_wakeref_t wakeref;
@@ -276,15 +285,15 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
spin_lock_irq(&dev_priv->irq_lock);
- drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
pin = intel_connector_hpd_pin(connector);
if (pin == HPD_NONE ||
- dev_priv->display.hotplug.stats[pin].state != HPD_DISABLED)
+ display->hotplug.stats[pin].state != HPD_DISABLED)
continue;
if (connector->base.polled != connector->polled)
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"Reenabling HPD on connector %s\n",
connector->base.name);
connector->base.polled = connector->polled;
@@ -292,8 +301,8 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
drm_connector_list_iter_end(&conn_iter);
for_each_hpd_pin(pin) {
- if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
- dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
+ if (display->hotplug.stats[pin].state == HPD_DISABLED)
+ display->hotplug.stats[pin].state = HPD_ENABLED;
}
intel_hpd_irq_setup(dev_priv);
@@ -407,7 +416,7 @@ static void i915_digport_work_func(struct work_struct *work)
spin_unlock_irq(&dev_priv->irq_lock);
- for_each_intel_encoder(&dev_priv->drm, encoder) {
+ for_each_intel_encoder(display->drm, encoder) {
struct intel_digital_port *dig_port;
enum hpd_pin pin = encoder->hpd_pin;
bool long_hpd, short_hpd;
@@ -433,9 +442,9 @@ static void i915_digport_work_func(struct work_struct *work)
if (old_bits) {
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->display.hotplug.event_bits |= old_bits;
- queue_delayed_detection_work(dev_priv,
- &dev_priv->display.hotplug.hotplug_work, 0);
+ display->hotplug.event_bits |= old_bits;
+ queue_delayed_detection_work(display,
+ &display->hotplug.hotplug_work, 0);
spin_unlock_irq(&dev_priv->irq_lock);
}
}
@@ -481,8 +490,8 @@ static void i915_hotplug_work_func(struct work_struct *work)
int changed_connectors = 0;
u32 blocked_hpd_pin_mask;
- mutex_lock(&dev_priv->drm.mode_config.mutex);
- drm_dbg_kms(&dev_priv->drm, "running encoder hotplug functions\n");
+ mutex_lock(&display->drm->mode_config.mutex);
+ drm_dbg_kms(display->drm, "running encoder hotplug functions\n");
spin_lock_irq(&dev_priv->irq_lock);
@@ -493,18 +502,18 @@ static void i915_hotplug_work_func(struct work_struct *work)
hotplug->retry_bits &= ~hpd_retry_bits;
/* Enable polling for connectors which had HPD IRQ storms */
- intel_hpd_irq_storm_switch_to_polling(dev_priv);
+ intel_hpd_irq_storm_switch_to_polling(display);
spin_unlock_irq(&dev_priv->irq_lock);
/* Skip calling encode hotplug handlers if ignore long HPD set*/
- if (dev_priv->display.hotplug.ignore_long_hpd) {
- drm_dbg_kms(&dev_priv->drm, "Ignore HPD flag on - skip encoder hotplug handlers\n");
- mutex_unlock(&dev_priv->drm.mode_config.mutex);
+ if (display->hotplug.ignore_long_hpd) {
+ drm_dbg_kms(display->drm, "Ignore HPD flag on - skip encoder hotplug handlers\n");
+ mutex_unlock(&display->drm->mode_config.mutex);
return;
}
- drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
enum hpd_pin pin;
u32 hpd_bit;
@@ -523,7 +532,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
else
connector->hotplug_retries++;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Connector %s (pin %i) received hotplug event. (retry %d)\n",
connector->base.name, pin,
connector->hotplug_retries);
@@ -546,12 +555,12 @@ static void i915_hotplug_work_func(struct work_struct *work)
}
}
drm_connector_list_iter_end(&conn_iter);
- mutex_unlock(&dev_priv->drm.mode_config.mutex);
+ mutex_unlock(&display->drm->mode_config.mutex);
if (changed_connectors == 1)
drm_kms_helper_connector_hotplug_event(first_changed_connector);
else if (changed_connectors > 0)
- drm_kms_helper_hotplug_event(&dev_priv->drm);
+ drm_kms_helper_hotplug_event(display->drm);
if (first_changed_connector)
drm_connector_put(first_changed_connector);
@@ -560,10 +569,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
retry &= ~changed;
if (retry) {
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->display.hotplug.retry_bits |= retry;
+ display->hotplug.retry_bits |= retry;
- mod_delayed_detection_work(dev_priv,
- &dev_priv->display.hotplug.hotplug_work,
+ mod_delayed_detection_work(display,
+ &display->hotplug.hotplug_work,
msecs_to_jiffies(HPD_RETRY_DELAY));
spin_unlock_irq(&dev_priv->irq_lock);
}
@@ -572,7 +581,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
/**
* intel_hpd_irq_handler - main hotplug irq handler
- * @dev_priv: drm_i915_private
+ * @display: display device
* @pin_mask: a mask of hpd pins that have triggered the irq
* @long_mask: a mask of hpd pins that may be long hpd pulses
*
@@ -586,10 +595,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
* Here, we do hotplug irq storm detection and mitigation, and pass further
* processing to appropriate bottom halves.
*/
-void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
+void intel_hpd_irq_handler(struct intel_display *display,
u32 pin_mask, u32 long_mask)
{
- struct intel_display *display = to_intel_display(&dev_priv->drm);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_encoder *encoder;
bool storm_detected = false;
bool queue_dig = false, queue_hp = false;
@@ -608,7 +617,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
* as each pin may have up to two encoders (HDMI and DP) and
* only the one of them (DP) will have ->hpd_pulse().
*/
- for_each_intel_encoder(&dev_priv->drm, encoder) {
+ for_each_intel_encoder(display->drm, encoder) {
bool long_hpd;
pin = encoder->hpd_pin;
@@ -620,7 +629,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
long_hpd = long_mask & BIT(pin);
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"digital hpd on [ENCODER:%d:%s] - %s\n",
encoder->base.base.id, encoder->base.name,
long_hpd ? "long" : "short");
@@ -630,10 +639,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (long_hpd) {
long_hpd_pulse_mask |= BIT(pin);
- dev_priv->display.hotplug.long_hpd_pin_mask |= BIT(pin);
+ display->hotplug.long_hpd_pin_mask |= BIT(pin);
} else {
short_hpd_pulse_mask |= BIT(pin);
- dev_priv->display.hotplug.short_hpd_pin_mask |= BIT(pin);
+ display->hotplug.short_hpd_pin_mask |= BIT(pin);
}
}
@@ -644,20 +653,20 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!(BIT(pin) & pin_mask))
continue;
- if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED) {
+ if (display->hotplug.stats[pin].state == HPD_DISABLED) {
/*
* On GMCH platforms the interrupt mask bits only
* prevent irq generation, not the setting of the
* hotplug bits itself. So only WARN about unexpected
* interrupts on saner platforms.
*/
- drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv),
+ drm_WARN_ONCE(display->drm, !HAS_GMCH(display),
"Received HPD interrupt on pin %d although disabled\n",
pin);
continue;
}
- if (dev_priv->display.hotplug.stats[pin].state != HPD_ENABLED)
+ if (display->hotplug.stats[pin].state != HPD_ENABLED)
continue;
/*
@@ -668,15 +677,15 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
long_hpd = long_hpd_pulse_mask & BIT(pin);
} else {
- dev_priv->display.hotplug.event_bits |= BIT(pin);
+ display->hotplug.event_bits |= BIT(pin);
long_hpd = true;
if (!hpd_pin_is_blocked(display, pin))
queue_hp = true;
}
- if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) {
- dev_priv->display.hotplug.event_bits &= ~BIT(pin);
+ if (intel_hpd_irq_storm_detect(display, pin, long_hpd)) {
+ display->hotplug.event_bits &= ~BIT(pin);
storm_detected = true;
queue_hp = true;
}
@@ -696,17 +705,17 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
* deadlock.
*/
if (queue_dig)
- queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work);
+ queue_work(display->hotplug.dp_wq, &display->hotplug.dig_port_work);
if (queue_hp)
- queue_delayed_detection_work(dev_priv,
- &dev_priv->display.hotplug.hotplug_work, 0);
+ queue_delayed_detection_work(display,
+ &display->hotplug.hotplug_work, 0);
spin_unlock(&dev_priv->irq_lock);
}
/**
* intel_hpd_init - initializes and enables hpd support
- * @dev_priv: i915 device instance
+ * @display: display device instance
*
* This function enables the hotplug support. It requires that interrupts have
* already been enabled with intel_irq_init_hw(). From this point on hotplug and
@@ -718,16 +727,17 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
*
* Also see: intel_hpd_poll_enable() and intel_hpd_poll_disable().
*/
-void intel_hpd_init(struct drm_i915_private *dev_priv)
+void intel_hpd_init(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int i;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
for_each_hpd_pin(i) {
- dev_priv->display.hotplug.stats[i].count = 0;
- dev_priv->display.hotplug.stats[i].state = HPD_ENABLED;
+ display->hotplug.stats[i].count = 0;
+ display->hotplug.stats[i].state = HPD_ENABLED;
}
/*
@@ -739,19 +749,19 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
-static void i915_hpd_poll_detect_connectors(struct drm_i915_private *i915)
+static void i915_hpd_poll_detect_connectors(struct intel_display *display)
{
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
struct intel_connector *first_changed_connector = NULL;
int changed = 0;
- mutex_lock(&i915->drm.mode_config.mutex);
+ mutex_lock(&display->drm->mode_config.mutex);
- if (!i915->drm.mode_config.poll_enabled)
+ if (!display->drm->mode_config.poll_enabled)
goto out;
- drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
if (!(connector->base.polled & DRM_CONNECTOR_POLL_HPD))
continue;
@@ -769,7 +779,7 @@ static void i915_hpd_poll_detect_connectors(struct drm_i915_private *i915)
drm_connector_list_iter_end(&conn_iter);
out:
- mutex_unlock(&i915->drm.mode_config.mutex);
+ mutex_unlock(&display->drm->mode_config.mutex);
if (!changed)
return;
@@ -777,25 +787,24 @@ static void i915_hpd_poll_detect_connectors(struct drm_i915_private *i915)
if (changed == 1)
drm_kms_helper_connector_hotplug_event(&first_changed_connector->base);
else
- drm_kms_helper_hotplug_event(&i915->drm);
+ drm_kms_helper_hotplug_event(display->drm);
drm_connector_put(&first_changed_connector->base);
}
static void i915_hpd_poll_init_work(struct work_struct *work)
{
- struct drm_i915_private *dev_priv =
- container_of(work, struct drm_i915_private,
- display.hotplug.poll_init_work);
- struct intel_display *display = &dev_priv->display;
+ struct intel_display *display =
+ container_of(work, typeof(*display), hotplug.poll_init_work);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
intel_wakeref_t wakeref;
bool enabled;
- mutex_lock(&dev_priv->drm.mode_config.mutex);
+ mutex_lock(&display->drm->mode_config.mutex);
- enabled = READ_ONCE(dev_priv->display.hotplug.poll_enabled);
+ enabled = READ_ONCE(display->hotplug.poll_enabled);
/*
* Prevent taking a power reference from this sequence of
* i915_hpd_poll_init_work() -> drm_helper_hpd_irq_event() ->
@@ -805,14 +814,14 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
if (!enabled) {
wakeref = intel_display_power_get(display,
POWER_DOMAIN_DISPLAY_CORE);
- drm_WARN_ON(&dev_priv->drm,
- READ_ONCE(dev_priv->display.hotplug.poll_enabled));
- cancel_work(&dev_priv->display.hotplug.poll_init_work);
+ drm_WARN_ON(display->drm,
+ READ_ONCE(display->hotplug.poll_enabled));
+ cancel_work(&display->hotplug.poll_init_work);
}
spin_lock_irq(&dev_priv->irq_lock);
- drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
enum hpd_pin pin;
@@ -820,7 +829,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
if (pin == HPD_NONE)
continue;
- if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
+ if (display->hotplug.stats[pin].state == HPD_DISABLED)
continue;
connector->base.polled = connector->polled;
@@ -834,16 +843,16 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
spin_unlock_irq(&dev_priv->irq_lock);
if (enabled)
- drm_kms_helper_poll_reschedule(&dev_priv->drm);
+ drm_kms_helper_poll_reschedule(display->drm);
- mutex_unlock(&dev_priv->drm.mode_config.mutex);
+ mutex_unlock(&display->drm->mode_config.mutex);
/*
* We might have missed any hotplugs that happened while we were
* in the middle of disabling polling
*/
if (!enabled) {
- i915_hpd_poll_detect_connectors(dev_priv);
+ i915_hpd_poll_detect_connectors(display);
intel_display_power_put(display,
POWER_DOMAIN_DISPLAY_CORE,
@@ -853,7 +862,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
/**
* intel_hpd_poll_enable - enable polling for connectors with hpd
- * @dev_priv: i915 device instance
+ * @display: display device instance
*
* This function enables polling for all connectors which support HPD.
* Under certain conditions HPD may not be functional. On most Intel GPUs,
@@ -867,15 +876,14 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
*
* Also see: intel_hpd_init() and intel_hpd_poll_disable().
*/
-void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
+void intel_hpd_poll_enable(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
- if (!HAS_DISPLAY(dev_priv) ||
- !intel_display_device_enabled(display))
+ if (!HAS_DISPLAY(display) || !intel_display_device_enabled(display))
return;
- WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true);
+ WRITE_ONCE(display->hotplug.poll_enabled, true);
/*
* We might already be holding dev->mode_config.mutex, so do this in a
@@ -884,14 +892,14 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
* this worker anyway
*/
spin_lock_irq(&dev_priv->irq_lock);
- queue_detection_work(dev_priv,
- &dev_priv->display.hotplug.poll_init_work);
+ queue_detection_work(display,
+ &display->hotplug.poll_init_work);
spin_unlock_irq(&dev_priv->irq_lock);
}
/**
* intel_hpd_poll_disable - disable polling for connectors with hpd
- * @dev_priv: i915 device instance
+ * @display: display device instance
*
* This function disables polling for all connectors which support HPD.
* Under certain conditions HPD may not be functional. On most Intel GPUs,
@@ -908,26 +916,28 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
*
* Also see: intel_hpd_init() and intel_hpd_poll_enable().
*/
-void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
+void intel_hpd_poll_disable(struct intel_display *display)
{
- if (!HAS_DISPLAY(dev_priv))
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ if (!HAS_DISPLAY(display))
return;
- WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, false);
+ WRITE_ONCE(display->hotplug.poll_enabled, false);
spin_lock_irq(&dev_priv->irq_lock);
- queue_detection_work(dev_priv,
- &dev_priv->display.hotplug.poll_init_work);
+ queue_detection_work(display,
+ &display->hotplug.poll_init_work);
spin_unlock_irq(&dev_priv->irq_lock);
}
-void intel_hpd_poll_fini(struct drm_i915_private *i915)
+void intel_hpd_poll_fini(struct intel_display *display)
{
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
/* Kill all the work that may have been queued by hpd. */
- drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
intel_connector_cancel_modeset_retry_work(connector);
intel_hdcp_cancel_works(connector);
@@ -935,70 +945,70 @@ void intel_hpd_poll_fini(struct drm_i915_private *i915)
drm_connector_list_iter_end(&conn_iter);
}
-void intel_hpd_init_early(struct drm_i915_private *i915)
+void intel_hpd_init_early(struct intel_display *display)
{
- INIT_DELAYED_WORK(&i915->display.hotplug.hotplug_work,
+ INIT_DELAYED_WORK(&display->hotplug.hotplug_work,
i915_hotplug_work_func);
- INIT_WORK(&i915->display.hotplug.dig_port_work, i915_digport_work_func);
- INIT_WORK(&i915->display.hotplug.poll_init_work, i915_hpd_poll_init_work);
- INIT_DELAYED_WORK(&i915->display.hotplug.reenable_work,
+ INIT_WORK(&display->hotplug.dig_port_work, i915_digport_work_func);
+ INIT_WORK(&display->hotplug.poll_init_work, i915_hpd_poll_init_work);
+ INIT_DELAYED_WORK(&display->hotplug.reenable_work,
intel_hpd_irq_storm_reenable_work);
- i915->display.hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
+ display->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
/* If we have MST support, we want to avoid doing short HPD IRQ storm
* detection, as short HPD storms will occur as a natural part of
* sideband messaging with MST.
* On older platforms however, IRQ storms can occur with both long and
* short pulses, as seen on some G4x systems.
*/
- i915->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(i915);
+ display->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(display);
}
-static bool cancel_all_detection_work(struct drm_i915_private *i915)
+static bool cancel_all_detection_work(struct intel_display *display)
{
bool was_pending = false;
- if (cancel_delayed_work_sync(&i915->display.hotplug.hotplug_work))
+ if (cancel_delayed_work_sync(&display->hotplug.hotplug_work))
was_pending = true;
- if (cancel_work_sync(&i915->display.hotplug.poll_init_work))
+ if (cancel_work_sync(&display->hotplug.poll_init_work))
was_pending = true;
- if (cancel_delayed_work_sync(&i915->display.hotplug.reenable_work))
+ if (cancel_delayed_work_sync(&display->hotplug.reenable_work))
was_pending = true;
return was_pending;
}
-void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
+void intel_hpd_cancel_work(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&dev_priv->drm);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
spin_lock_irq(&dev_priv->irq_lock);
drm_WARN_ON(display->drm, get_blocked_hpd_pin_mask(display));
- dev_priv->display.hotplug.long_hpd_pin_mask = 0;
- dev_priv->display.hotplug.short_hpd_pin_mask = 0;
- dev_priv->display.hotplug.event_bits = 0;
- dev_priv->display.hotplug.retry_bits = 0;
+ display->hotplug.long_hpd_pin_mask = 0;
+ display->hotplug.short_hpd_pin_mask = 0;
+ display->hotplug.event_bits = 0;
+ display->hotplug.retry_bits = 0;
spin_unlock_irq(&dev_priv->irq_lock);
- cancel_work_sync(&dev_priv->display.hotplug.dig_port_work);
+ cancel_work_sync(&display->hotplug.dig_port_work);
/*
* All other work triggered by hotplug events should be canceled by
* now.
*/
- if (cancel_all_detection_work(dev_priv))
- drm_dbg_kms(&dev_priv->drm, "Hotplug detection work still active\n");
+ if (cancel_all_detection_work(display))
+ drm_dbg_kms(display->drm, "Hotplug detection work still active\n");
}
-static void queue_work_for_missed_irqs(struct drm_i915_private *i915)
+static void queue_work_for_missed_irqs(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_hotplug *hotplug = &display->hotplug;
bool queue_hp_work = false;
u32 blocked_hpd_pin_mask;
@@ -1011,7 +1021,7 @@ static void queue_work_for_missed_irqs(struct drm_i915_private *i915)
queue_hp_work = true;
for_each_hpd_pin(pin) {
- switch (i915->display.hotplug.stats[pin].state) {
+ switch (display->hotplug.stats[pin].state) {
case HPD_MARK_DISABLED:
queue_hp_work = true;
break;
@@ -1019,7 +1029,7 @@ static void queue_work_for_missed_irqs(struct drm_i915_private *i915)
case HPD_ENABLED:
break;
default:
- MISSING_CASE(i915->display.hotplug.stats[pin].state);
+ MISSING_CASE(display->hotplug.stats[pin].state);
}
}
@@ -1027,7 +1037,7 @@ static void queue_work_for_missed_irqs(struct drm_i915_private *i915)
queue_work(hotplug->dp_wq, &hotplug->dig_port_work);
if (queue_hp_work)
- queue_delayed_detection_work(i915, &i915->display.hotplug.hotplug_work, 0);
+ queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0);
}
static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin)
@@ -1121,7 +1131,7 @@ void intel_hpd_unblock(struct intel_encoder *encoder)
spin_lock_irq(&i915->irq_lock);
if (unblock_hpd_pin(display, encoder->hpd_pin))
- queue_work_for_missed_irqs(i915);
+ queue_work_for_missed_irqs(display);
spin_unlock_irq(&i915->irq_lock);
}
@@ -1156,30 +1166,35 @@ void intel_hpd_clear_and_unblock(struct intel_encoder *encoder)
spin_unlock_irq(&i915->irq_lock);
}
-void intel_hpd_enable_detection_work(struct drm_i915_private *i915)
+void intel_hpd_enable_detection_work(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
spin_lock_irq(&i915->irq_lock);
- i915->display.hotplug.detection_work_enabled = true;
- queue_work_for_missed_irqs(i915);
+ display->hotplug.detection_work_enabled = true;
+ queue_work_for_missed_irqs(display);
spin_unlock_irq(&i915->irq_lock);
}
-void intel_hpd_disable_detection_work(struct drm_i915_private *i915)
+void intel_hpd_disable_detection_work(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
spin_lock_irq(&i915->irq_lock);
- i915->display.hotplug.detection_work_enabled = false;
+ display->hotplug.detection_work_enabled = false;
spin_unlock_irq(&i915->irq_lock);
- cancel_all_detection_work(i915);
+ cancel_all_detection_work(display);
}
-bool intel_hpd_schedule_detection(struct drm_i915_private *i915)
+bool intel_hpd_schedule_detection(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
unsigned long flags;
bool ret;
spin_lock_irqsave(&i915->irq_lock, flags);
- ret = queue_delayed_detection_work(i915, &i915->display.hotplug.hotplug_work, 0);
+ ret = queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0);
spin_unlock_irqrestore(&i915->irq_lock, flags);
return ret;
@@ -1188,14 +1203,15 @@ bool intel_hpd_schedule_detection(struct drm_i915_private *i915)
static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
- struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
+ struct intel_display *display = &dev_priv->display;
+ struct intel_hotplug *hotplug = &display->hotplug;
/* Synchronize with everything first in case there's been an HPD
* storm, but we haven't finished handling it in the kernel yet
*/
intel_synchronize_irq(dev_priv);
- flush_work(&dev_priv->display.hotplug.dig_port_work);
- flush_delayed_work(&dev_priv->display.hotplug.hotplug_work);
+ flush_work(&display->hotplug.dig_port_work);
+ flush_delayed_work(&display->hotplug.hotplug_work);
seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
seq_printf(m, "Detected: %s\n",
@@ -1210,7 +1226,8 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
+ struct intel_display *display = &dev_priv->display;
+ struct intel_hotplug *hotplug = &display->hotplug;
unsigned int new_threshold;
int i;
char *newline;
@@ -1235,11 +1252,11 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
return -EINVAL;
if (new_threshold > 0)
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Setting HPD storm detection threshold to %d\n",
new_threshold);
else
- drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm detection\n");
+ drm_dbg_kms(display->drm, "Disabling HPD storm detection\n");
spin_lock_irq(&dev_priv->irq_lock);
hotplug->hpd_storm_threshold = new_threshold;
@@ -1249,7 +1266,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
spin_unlock_irq(&dev_priv->irq_lock);
/* Re-enable hpd immediately if we were in an irq storm */
- flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
+ flush_delayed_work(&display->hotplug.reenable_work);
return len;
}
@@ -1271,9 +1288,10 @@ static const struct file_operations i915_hpd_storm_ctl_fops = {
static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = &dev_priv->display;
seq_printf(m, "Enabled: %s\n",
- str_yes_no(dev_priv->display.hotplug.hpd_short_storm_enabled));
+ str_yes_no(display->hotplug.hpd_short_storm_enabled));
return 0;
}
@@ -1291,7 +1309,8 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
+ struct intel_display *display = &dev_priv->display;
+ struct intel_hotplug *hotplug = &display->hotplug;
char *newline;
char tmp[16];
int i;
@@ -1312,11 +1331,11 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
/* Reset to the "default" state for this system */
if (strcmp(tmp, "reset") == 0)
- new_state = !HAS_DP_MST(dev_priv);
+ new_state = !HAS_DP_MST(display);
else if (kstrtobool(tmp, &new_state) != 0)
return -EINVAL;
- drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n",
+ drm_dbg_kms(display->drm, "%sabling HPD short storm detection\n",
new_state ? "En" : "Dis");
spin_lock_irq(&dev_priv->irq_lock);
@@ -1327,7 +1346,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
spin_unlock_irq(&dev_priv->irq_lock);
/* Re-enable hpd immediately if we were in an irq storm */
- flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
+ flush_delayed_work(&display->hotplug.reenable_work);
return len;
}
@@ -1341,14 +1360,15 @@ static const struct file_operations i915_hpd_short_storm_ctl_fops = {
.write = i915_hpd_short_storm_ctl_write,
};
-void intel_hpd_debugfs_register(struct drm_i915_private *i915)
+void intel_hpd_debugfs_register(struct intel_display *display)
{
- struct drm_minor *minor = i915->drm.primary;
+ struct drm_minor *minor = display->drm->primary;
+ struct drm_i915_private *i915 = to_i915(display->drm);
debugfs_create_file("i915_hpd_storm_ctl", 0644, minor->debugfs_root,
i915, &i915_hpd_storm_ctl_fops);
debugfs_create_file("i915_hpd_short_storm_ctl", 0644, minor->debugfs_root,
i915, &i915_hpd_short_storm_ctl_fops);
debugfs_create_bool("i915_ignore_long_hpd", 0644, minor->debugfs_root,
- &i915->display.hotplug.ignore_long_hpd);
+ &display->hotplug.ignore_long_hpd);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h
index f189b871904e..edc41c9d3d65 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.h
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
@@ -8,31 +8,31 @@
#include <linux/types.h>
-struct drm_i915_private;
+enum port;
struct intel_connector;
struct intel_digital_port;
+struct intel_display;
struct intel_encoder;
-enum port;
-void intel_hpd_poll_enable(struct drm_i915_private *dev_priv);
-void intel_hpd_poll_disable(struct drm_i915_private *dev_priv);
-void intel_hpd_poll_fini(struct drm_i915_private *i915);
+void intel_hpd_poll_enable(struct intel_display *display);
+void intel_hpd_poll_disable(struct intel_display *display);
+void intel_hpd_poll_fini(struct intel_display *display);
enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder,
struct intel_connector *connector);
-void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
+void intel_hpd_irq_handler(struct intel_display *display,
u32 pin_mask, u32 long_mask);
void intel_hpd_trigger_irq(struct intel_digital_port *dig_port);
-void intel_hpd_init(struct drm_i915_private *dev_priv);
-void intel_hpd_init_early(struct drm_i915_private *i915);
-void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
+void intel_hpd_init(struct intel_display *display);
+void intel_hpd_init_early(struct intel_display *display);
+void intel_hpd_cancel_work(struct intel_display *display);
enum hpd_pin intel_hpd_pin_default(enum port port);
void intel_hpd_block(struct intel_encoder *encoder);
void intel_hpd_unblock(struct intel_encoder *encoder);
void intel_hpd_clear_and_unblock(struct intel_encoder *encoder);
-void intel_hpd_debugfs_register(struct drm_i915_private *i915);
+void intel_hpd_debugfs_register(struct intel_display *display);
-void intel_hpd_enable_detection_work(struct drm_i915_private *i915);
-void intel_hpd_disable_detection_work(struct drm_i915_private *i915);
-bool intel_hpd_schedule_detection(struct drm_i915_private *i915);
+void intel_hpd_enable_detection_work(struct intel_display *display);
+void intel_hpd_disable_detection_work(struct intel_display *display);
+bool intel_hpd_schedule_detection(struct intel_display *display);
#endif /* __INTEL_HOTPLUG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 2137ac7b882a..e6320838df59 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -472,7 +472,7 @@ void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status)
dev_priv->display.hotplug.hpd,
i9xx_port_hotplug_long_detect);
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ intel_hpd_irq_handler(display, pin_mask, long_mask);
}
if ((IS_G4X(dev_priv) ||
@@ -483,6 +483,7 @@ void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status)
void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
{
+ struct intel_display *display = &dev_priv->display;
u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
/*
@@ -509,7 +510,7 @@ void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
dev_priv->display.hotplug.pch_hpd,
pch_port_hotplug_long_detect);
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ intel_hpd_irq_handler(display, pin_mask, long_mask);
}
void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
@@ -543,7 +544,7 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
"pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
hotplug_trigger, pin_mask, long_mask);
- intel_hpd_irq_handler(i915, pin_mask, long_mask);
+ intel_hpd_irq_handler(display, pin_mask, long_mask);
}
if (trigger_aux)
@@ -587,7 +588,7 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
}
if (pin_mask)
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ intel_hpd_irq_handler(display, pin_mask, long_mask);
if (pch_iir & SDE_GMBUS_ICP)
intel_gmbus_irq_handler(display);
@@ -624,7 +625,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
}
if (pin_mask)
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ intel_hpd_irq_handler(display, pin_mask, long_mask);
if (pch_iir & SDE_GMBUS_CPT)
intel_gmbus_irq_handler(display);
@@ -632,6 +633,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
{
+ struct intel_display *display = &dev_priv->display;
u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
@@ -641,11 +643,12 @@ void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
dev_priv->display.hotplug.hpd,
ilk_port_hotplug_long_detect);
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ intel_hpd_irq_handler(display, pin_mask, long_mask);
}
void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
{
+ struct intel_display *display = &dev_priv->display;
u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
@@ -655,11 +658,12 @@ void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
dev_priv->display.hotplug.hpd,
bxt_port_hotplug_long_detect);
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ intel_hpd_irq_handler(display, pin_mask, long_mask);
}
void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
{
+ struct intel_display *display = &dev_priv->display;
u32 pin_mask = 0, long_mask = 0;
u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
@@ -687,7 +691,7 @@ void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
}
if (pin_mask)
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ intel_hpd_irq_handler(display, pin_mask, long_mask);
else
drm_err(&dev_priv->drm,
"Unexpected DE HPD interrupt 0x%08x\n", iir);
@@ -1467,9 +1471,11 @@ void intel_hpd_irq_setup(struct drm_i915_private *i915)
void intel_hotplug_irq_init(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
+
intel_hpd_init_pins(i915);
- intel_hpd_init_early(i915);
+ intel_hpd_init_early(display);
if (HAS_GMCH(i915)) {
if (I915_HAS_HOTPLUG(i915))
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index ce3cc93ea211..510e240c000b 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -981,7 +981,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_dp_mst_suspend(display);
intel_irq_suspend(i915);
- intel_hpd_cancel_work(i915);
+ intel_hpd_cancel_work(display);
if (HAS_DISPLAY(i915))
intel_display_driver_suspend_access(display);
@@ -1064,7 +1064,7 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_display_driver_suspend(display);
intel_irq_suspend(dev_priv);
- intel_hpd_cancel_work(dev_priv);
+ intel_hpd_cancel_work(display);
if (HAS_DISPLAY(dev_priv))
intel_display_driver_suspend_access(display);
@@ -1227,7 +1227,7 @@ static int i915_drm_resume(struct drm_device *dev)
if (HAS_DISPLAY(dev_priv))
intel_display_driver_resume_access(display);
- intel_hpd_init(dev_priv);
+ intel_hpd_init(display);
intel_display_driver_resume(display);
@@ -1235,7 +1235,7 @@ static int i915_drm_resume(struct drm_device *dev)
intel_display_driver_enable_user_access(display);
drm_kms_helper_poll_enable(dev);
}
- intel_hpd_poll_disable(dev_priv);
+ intel_hpd_poll_disable(display);
intel_opregion_resume(display);
@@ -1575,7 +1575,7 @@ static int intel_runtime_suspend(struct device *kdev)
assert_forcewakes_inactive(&dev_priv->uncore);
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
- intel_hpd_poll_enable(dev_priv);
+ intel_hpd_poll_enable(display);
drm_dbg(&dev_priv->drm, "Device suspended\n");
return 0;
@@ -1633,8 +1633,8 @@ static int intel_runtime_resume(struct device *kdev)
* everyone else do it here.
*/
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
- intel_hpd_init(dev_priv);
- intel_hpd_poll_disable(dev_priv);
+ intel_hpd_init(display);
+ intel_hpd_poll_disable(display);
}
skl_watermark_ipc_update(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 37ca4a35daf2..de53615571be 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1280,6 +1280,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
*/
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
int irq = to_pci_dev(dev_priv->drm.dev)->irq;
if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled))
@@ -1289,7 +1290,7 @@ void intel_irq_uninstall(struct drm_i915_private *dev_priv)
free_irq(irq, dev_priv);
- intel_hpd_cancel_work(dev_priv);
+ intel_hpd_cancel_work(display);
dev_priv->irqs_enabled = false;
}
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 0b0aca7a25af..263459323bf7 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -173,7 +173,7 @@ static void xe_display_fini(void *arg)
struct xe_device *xe = arg;
struct intel_display *display = &xe->display;
- intel_hpd_poll_fini(xe);
+ intel_hpd_poll_fini(display);
intel_hdcp_component_fini(display);
intel_audio_deinit(display);
intel_display_driver_remove(display);
@@ -305,7 +305,7 @@ static void xe_display_enable_d3cold(struct xe_device *xe)
intel_dmc_suspend(display);
if (has_display(xe))
- intel_hpd_poll_enable(xe);
+ intel_hpd_poll_enable(display);
}
static void xe_display_disable_d3cold(struct xe_device *xe)
@@ -322,10 +322,10 @@ static void xe_display_disable_d3cold(struct xe_device *xe)
intel_display_driver_init_hw(display);
- intel_hpd_init(xe);
+ intel_hpd_init(display);
if (has_display(xe))
- intel_hpd_poll_disable(xe);
+ intel_hpd_poll_disable(display);
intel_opregion_resume(display);
@@ -355,7 +355,7 @@ void xe_display_pm_suspend(struct xe_device *xe)
xe_display_flush_cleanup_work(xe);
- intel_hpd_cancel_work(xe);
+ intel_hpd_cancel_work(display);
if (has_display(xe)) {
intel_display_driver_suspend_access(display);
@@ -385,7 +385,7 @@ void xe_display_pm_shutdown(struct xe_device *xe)
xe_display_flush_cleanup_work(xe);
intel_dp_mst_suspend(display);
- intel_hpd_cancel_work(xe);
+ intel_hpd_cancel_work(display);
if (has_display(xe))
intel_display_driver_suspend_access(display);
@@ -400,6 +400,8 @@ void xe_display_pm_shutdown(struct xe_device *xe)
void xe_display_pm_runtime_suspend(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
@@ -408,7 +410,7 @@ void xe_display_pm_runtime_suspend(struct xe_device *xe)
return;
}
- intel_hpd_poll_enable(xe);
+ intel_hpd_poll_enable(display);
}
void xe_display_pm_suspend_late(struct xe_device *xe)
@@ -482,7 +484,7 @@ void xe_display_pm_resume(struct xe_device *xe)
if (has_display(xe))
intel_display_driver_resume_access(display);
- intel_hpd_init(xe);
+ intel_hpd_init(display);
if (has_display(xe)) {
intel_display_driver_resume(display);
@@ -491,7 +493,7 @@ void xe_display_pm_resume(struct xe_device *xe)
}
if (has_display(xe))
- intel_hpd_poll_disable(xe);
+ intel_hpd_poll_disable(display);
intel_opregion_resume(display);
@@ -502,6 +504,8 @@ void xe_display_pm_resume(struct xe_device *xe)
void xe_display_pm_runtime_resume(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
@@ -510,8 +514,8 @@ void xe_display_pm_runtime_resume(struct xe_device *xe)
return;
}
- intel_hpd_init(xe);
- intel_hpd_poll_disable(xe);
+ intel_hpd_init(display);
+ intel_hpd_poll_disable(display);
skl_watermark_ipc_update(xe);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* RE: [PATCH 3/9] drm/i915/hotplug: convert intel_hotplug.[ch] to struct intel_display
2025-03-11 18:00 ` [PATCH 3/9] drm/i915/hotplug: convert intel_hotplug.[ch] " Jani Nikula
@ 2025-03-12 5:13 ` Shankar, Uma
0 siblings, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 5:13 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 3/9] drm/i915/hotplug: convert intel_hotplug.[ch] to struct
> intel_display
>
> Going forward, struct intel_display is the main display device data
> pointer. Convert as much as possible of intel_hotplug.[ch] to struct
> intel_display.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> .../drm/i915/display/intel_display_driver.c | 14 +-
> .../i915/display/intel_display_power_well.c | 6 +-
> .../drm/i915/display/intel_display_reset.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hotplug.c | 332 ++++++++++--------
> drivers/gpu/drm/i915/display/intel_hotplug.h | 26 +-
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 24 +-
> drivers/gpu/drm/i915/i915_driver.c | 14 +-
> drivers/gpu/drm/i915/i915_irq.c | 3 +-
> drivers/gpu/drm/xe/display/xe_display.c | 26 +-
> 11 files changed, 240 insertions(+), 213 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index fdedf65bee53..f42b5a69eed5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -844,7 +844,7 @@ void intel_display_debugfs_register(struct intel_display
> *display)
> intel_dmc_debugfs_register(display);
> intel_dp_test_debugfs_register(display);
> intel_fbc_debugfs_register(display);
> - intel_hpd_debugfs_register(i915);
> + intel_hpd_debugfs_register(display);
> intel_opregion_debugfs_register(display);
> intel_psr_debugfs_register(display);
> intel_wm_debugfs_register(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 31740a677dd8..ae60ccb21520 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -315,11 +315,9 @@ static void set_display_access(struct intel_display
> *display,
> */
> void intel_display_driver_enable_user_access(struct intel_display *display)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> -
> set_display_access(display, true, NULL);
>
> - intel_hpd_enable_detection_work(i915);
> + intel_hpd_enable_detection_work(display);
> }
>
> /**
> @@ -341,9 +339,7 @@ void intel_display_driver_enable_user_access(struct
> intel_display *display)
> */
> void intel_display_driver_disable_user_access(struct intel_display *display)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> -
> - intel_hpd_disable_detection_work(i915);
> + intel_hpd_disable_detection_work(display);
>
> set_display_access(display, false, current);
> }
> @@ -524,7 +520,7 @@ int intel_display_driver_probe(struct intel_display
> *display)
> intel_overlay_setup(display);
>
> /* Only enable hotplug handling once the fbdev is fully set up. */
> - intel_hpd_init(i915);
> + intel_hpd_init(display);
>
> skl_watermark_ipc_init(i915);
>
> @@ -558,7 +554,7 @@ void intel_display_driver_register(struct intel_display
> *display)
> * fbdev->async_cookie.
> */
> drm_kms_helper_poll_init(display->drm);
> - intel_hpd_poll_disable(i915);
> + intel_hpd_poll_disable(display);
>
> intel_fbdev_setup(i915);
>
> @@ -600,7 +596,7 @@ void intel_display_driver_remove_noirq(struct
> intel_display *display)
> * Due to the hpd irq storm handling the hotplug work can re-arm the
> * poll handlers. Hence disable polling after hpd handling is shut down.
> */
> - intel_hpd_poll_fini(i915);
> + intel_hpd_poll_fini(display);
>
> intel_unregister_dsm_handler();
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 8ec87ffd87d2..daf2a0cbb157 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1236,8 +1236,8 @@ static void vlv_display_power_well_init(struct
> intel_display *display)
> if (display->power.domains.initializing)
> return;
>
> - intel_hpd_init(dev_priv);
> - intel_hpd_poll_disable(dev_priv);
> + intel_hpd_init(display);
> + intel_hpd_poll_disable(display);
>
> /* Re-enable the ADPA, if we have one */
> for_each_intel_encoder(display->drm, encoder) {
> @@ -1265,7 +1265,7 @@ static void vlv_display_power_well_deinit(struct
> intel_display *display)
>
> /* Prevent us from re-enabling polling on accident in late suspend */
> if (!display->drm->dev->power.is_suspended)
> - intel_hpd_poll_enable(dev_priv);
> + intel_hpd_poll_enable(display);
> }
>
> static void vlv_display_power_well_enable(struct intel_display *display,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c
> b/drivers/gpu/drm/i915/display/intel_display_reset.c
> index 1f2798404f2c..1dbd3e841df3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reset.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c
> @@ -107,14 +107,14 @@ void intel_display_reset_finish(struct intel_display
> *display, bool test_only)
> intel_display_driver_init_hw(display);
> intel_clock_gating_init(i915);
> intel_cx0_pll_power_save_wa(display);
> - intel_hpd_init(i915);
> + intel_hpd_init(display);
>
> ret = __intel_display_driver_resume(display, state, ctx);
> if (ret)
> drm_err(display->drm,
> "Restoring old state failed with %i\n", ret);
>
> - intel_hpd_poll_disable(i915);
> + intel_hpd_poll_disable(display);
> }
>
> drm_atomic_state_put(state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index a236b5fc7a3d..7d074770d793 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6117,7 +6117,7 @@ static void intel_dp_oob_hotplug_event(struct
> drm_connector *connector,
> spin_unlock_irq(&i915->irq_lock);
>
> if (need_work)
> - intel_hpd_schedule_detection(i915);
> + intel_hpd_schedule_detection(display);
> }
>
> static const struct drm_connector_funcs intel_dp_connector_funcs = {
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index c69b1f5fd160..9bde28ce1979 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -118,7 +118,7 @@ intel_connector_hpd_pin(struct intel_connector
> *connector)
>
> /**
> * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin
> - * @dev_priv: private driver data pointer
> + * @display: display device
> * @pin: the pin to gather stats on
> * @long_hpd: whether the HPD IRQ was long or short
> *
> @@ -127,13 +127,13 @@ intel_connector_hpd_pin(struct intel_connector
> *connector)
> * responsible for further action.
> *
> * The number of IRQs that are allowed within @HPD_STORM_DETECT_PERIOD
> is
> - * stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
> + * stored in @display->hotplug.hpd_storm_threshold which defaults to
> * @HPD_STORM_DEFAULT_THRESHOLD. Long IRQs count as +10 to this
> threshold, and
> * short IRQs count as +1. If this threshold is exceeded, it's considered an
> * IRQ storm and the IRQ state is set to @HPD_MARK_DISABLED.
> *
> * By default, most systems will only count long IRQs towards
> - * &dev_priv->display.hotplug.hpd_storm_threshold. However, some older
> systems also
> + * &display->hotplug.hpd_storm_threshold. However, some older systems also
> * suffer from short IRQ storms and must also track these. Because short IRQ
> * storms are naturally caused by sideband interactions with DP MST devices,
> * short IRQ detection is only enabled for systems without DP MST support.
> @@ -145,10 +145,10 @@ intel_connector_hpd_pin(struct intel_connector
> *connector)
> *
> * Return true if an IRQ storm was detected on @pin.
> */
> -static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
> +static bool intel_hpd_irq_storm_detect(struct intel_display *display,
> enum hpd_pin pin, bool long_hpd)
> {
> - struct intel_hotplug *hpd = &dev_priv->display.hotplug;
> + struct intel_hotplug *hpd = &display->hotplug;
> unsigned long start = hpd->stats[pin].last_jiffies;
> unsigned long end = start +
> msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
> const int increment = long_hpd ? 10 : 1;
> @@ -156,7 +156,7 @@ static bool intel_hpd_irq_storm_detect(struct
> drm_i915_private *dev_priv,
> bool storm = false;
>
> if (!threshold ||
> - (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled))
> + (!long_hpd && !display->hotplug.hpd_short_storm_enabled))
> return false;
>
> if (!time_in_range(jiffies, start, end)) {
> @@ -167,11 +167,11 @@ static bool intel_hpd_irq_storm_detect(struct
> drm_i915_private *dev_priv,
> hpd->stats[pin].count += increment;
> if (hpd->stats[pin].count > threshold) {
> hpd->stats[pin].state = HPD_MARK_DISABLED;
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "HPD interrupt storm detected on PIN %d\n", pin);
> storm = true;
> } else {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Received HPD interrupt on PIN %d - cnt: %d\n",
> pin,
> hpd->stats[pin].count);
> @@ -180,56 +180,65 @@ static bool intel_hpd_irq_storm_detect(struct
> drm_i915_private *dev_priv,
> return storm;
> }
>
> -static bool detection_work_enabled(struct drm_i915_private *i915)
> +static bool detection_work_enabled(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> lockdep_assert_held(&i915->irq_lock);
>
> - return i915->display.hotplug.detection_work_enabled;
> + return display->hotplug.detection_work_enabled;
> }
>
> static bool
> -mod_delayed_detection_work(struct drm_i915_private *i915, struct
> delayed_work *work, int delay)
> +mod_delayed_detection_work(struct intel_display *display, struct delayed_work
> *work, int delay)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> lockdep_assert_held(&i915->irq_lock);
>
> - if (!detection_work_enabled(i915))
> + if (!detection_work_enabled(display))
> return false;
>
> return mod_delayed_work(i915->unordered_wq, work, delay);
> }
>
> static bool
> -queue_delayed_detection_work(struct drm_i915_private *i915, struct
> delayed_work *work, int delay)
> +queue_delayed_detection_work(struct intel_display *display, struct
> delayed_work *work, int delay)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> lockdep_assert_held(&i915->irq_lock);
>
> - if (!detection_work_enabled(i915))
> + if (!detection_work_enabled(display))
> return false;
>
> return queue_delayed_work(i915->unordered_wq, work, delay);
> }
>
> static bool
> -queue_detection_work(struct drm_i915_private *i915, struct work_struct
> *work)
> +queue_detection_work(struct intel_display *display, struct work_struct *work)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> lockdep_assert_held(&i915->irq_lock);
>
> - if (!detection_work_enabled(i915))
> + if (!detection_work_enabled(display))
> return false;
>
> return queue_work(i915->unordered_wq, work);
> }
>
> static void
> -intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
> +intel_hpd_irq_storm_switch_to_polling(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct drm_connector_list_iter conn_iter;
> struct intel_connector *connector;
> bool hpd_disabled = false;
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> enum hpd_pin pin;
>
> @@ -238,15 +247,15 @@ intel_hpd_irq_storm_switch_to_polling(struct
> drm_i915_private *dev_priv)
>
> pin = intel_connector_hpd_pin(connector);
> if (pin == HPD_NONE ||
> - dev_priv->display.hotplug.stats[pin].state !=
> HPD_MARK_DISABLED)
> + display->hotplug.stats[pin].state != HPD_MARK_DISABLED)
> continue;
>
> - drm_info(&dev_priv->drm,
> + drm_info(display->drm,
> "HPD interrupt storm detected on connector %s: "
> "switching from hotplug detection to polling\n",
> connector->base.name);
>
> - dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
> + display->hotplug.stats[pin].state = HPD_DISABLED;
> connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
> DRM_CONNECTOR_POLL_DISCONNECT;
> hpd_disabled = true;
> @@ -255,18 +264,18 @@ intel_hpd_irq_storm_switch_to_polling(struct
> drm_i915_private *dev_priv)
>
> /* Enable polling and queue hotplug re-enabling. */
> if (hpd_disabled) {
> - drm_kms_helper_poll_reschedule(&dev_priv->drm);
> - mod_delayed_detection_work(dev_priv,
> - &dev_priv-
> >display.hotplug.reenable_work,
> + drm_kms_helper_poll_reschedule(display->drm);
> + mod_delayed_detection_work(display,
> + &display->hotplug.reenable_work,
>
> msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
> }
> }
>
> static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> {
> - struct drm_i915_private *dev_priv =
> - container_of(work, typeof(*dev_priv),
> - display.hotplug.reenable_work.work);
> + struct intel_display *display =
> + container_of(work, typeof(*display),
> hotplug.reenable_work.work);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct drm_connector_list_iter conn_iter;
> struct intel_connector *connector;
> intel_wakeref_t wakeref;
> @@ -276,15 +285,15 @@ static void intel_hpd_irq_storm_reenable_work(struct
> work_struct *work)
>
> spin_lock_irq(&dev_priv->irq_lock);
>
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> pin = intel_connector_hpd_pin(connector);
> if (pin == HPD_NONE ||
> - dev_priv->display.hotplug.stats[pin].state != HPD_DISABLED)
> + display->hotplug.stats[pin].state != HPD_DISABLED)
> continue;
>
> if (connector->base.polled != connector->polled)
> - drm_dbg(&dev_priv->drm,
> + drm_dbg(display->drm,
> "Reenabling HPD on connector %s\n",
> connector->base.name);
> connector->base.polled = connector->polled;
> @@ -292,8 +301,8 @@ static void intel_hpd_irq_storm_reenable_work(struct
> work_struct *work)
> drm_connector_list_iter_end(&conn_iter);
>
> for_each_hpd_pin(pin) {
> - if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
> - dev_priv->display.hotplug.stats[pin].state =
> HPD_ENABLED;
> + if (display->hotplug.stats[pin].state == HPD_DISABLED)
> + display->hotplug.stats[pin].state = HPD_ENABLED;
> }
>
> intel_hpd_irq_setup(dev_priv);
> @@ -407,7 +416,7 @@ static void i915_digport_work_func(struct work_struct
> *work)
>
> spin_unlock_irq(&dev_priv->irq_lock);
>
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> + for_each_intel_encoder(display->drm, encoder) {
> struct intel_digital_port *dig_port;
> enum hpd_pin pin = encoder->hpd_pin;
> bool long_hpd, short_hpd;
> @@ -433,9 +442,9 @@ static void i915_digport_work_func(struct work_struct
> *work)
>
> if (old_bits) {
> spin_lock_irq(&dev_priv->irq_lock);
> - dev_priv->display.hotplug.event_bits |= old_bits;
> - queue_delayed_detection_work(dev_priv,
> - &dev_priv-
> >display.hotplug.hotplug_work, 0);
> + display->hotplug.event_bits |= old_bits;
> + queue_delayed_detection_work(display,
> + &display->hotplug.hotplug_work, 0);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
> }
> @@ -481,8 +490,8 @@ static void i915_hotplug_work_func(struct work_struct
> *work)
> int changed_connectors = 0;
> u32 blocked_hpd_pin_mask;
>
> - mutex_lock(&dev_priv->drm.mode_config.mutex);
> - drm_dbg_kms(&dev_priv->drm, "running encoder hotplug functions\n");
> + mutex_lock(&display->drm->mode_config.mutex);
> + drm_dbg_kms(display->drm, "running encoder hotplug functions\n");
>
> spin_lock_irq(&dev_priv->irq_lock);
>
> @@ -493,18 +502,18 @@ static void i915_hotplug_work_func(struct work_struct
> *work)
> hotplug->retry_bits &= ~hpd_retry_bits;
>
> /* Enable polling for connectors which had HPD IRQ storms */
> - intel_hpd_irq_storm_switch_to_polling(dev_priv);
> + intel_hpd_irq_storm_switch_to_polling(display);
>
> spin_unlock_irq(&dev_priv->irq_lock);
>
> /* Skip calling encode hotplug handlers if ignore long HPD set*/
> - if (dev_priv->display.hotplug.ignore_long_hpd) {
> - drm_dbg_kms(&dev_priv->drm, "Ignore HPD flag on - skip
> encoder hotplug handlers\n");
> - mutex_unlock(&dev_priv->drm.mode_config.mutex);
> + if (display->hotplug.ignore_long_hpd) {
> + drm_dbg_kms(display->drm, "Ignore HPD flag on - skip encoder
> hotplug handlers\n");
> + mutex_unlock(&display->drm->mode_config.mutex);
> return;
> }
>
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> enum hpd_pin pin;
> u32 hpd_bit;
> @@ -523,7 +532,7 @@ static void i915_hotplug_work_func(struct work_struct
> *work)
> else
> connector->hotplug_retries++;
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Connector %s (pin %i) received hotplug
> event. (retry %d)\n",
> connector->base.name, pin,
> connector->hotplug_retries);
> @@ -546,12 +555,12 @@ static void i915_hotplug_work_func(struct work_struct
> *work)
> }
> }
> drm_connector_list_iter_end(&conn_iter);
> - mutex_unlock(&dev_priv->drm.mode_config.mutex);
> + mutex_unlock(&display->drm->mode_config.mutex);
>
> if (changed_connectors == 1)
>
> drm_kms_helper_connector_hotplug_event(first_changed_connector);
> else if (changed_connectors > 0)
> - drm_kms_helper_hotplug_event(&dev_priv->drm);
> + drm_kms_helper_hotplug_event(display->drm);
>
> if (first_changed_connector)
> drm_connector_put(first_changed_connector);
> @@ -560,10 +569,10 @@ static void i915_hotplug_work_func(struct work_struct
> *work)
> retry &= ~changed;
> if (retry) {
> spin_lock_irq(&dev_priv->irq_lock);
> - dev_priv->display.hotplug.retry_bits |= retry;
> + display->hotplug.retry_bits |= retry;
>
> - mod_delayed_detection_work(dev_priv,
> - &dev_priv-
> >display.hotplug.hotplug_work,
> + mod_delayed_detection_work(display,
> + &display->hotplug.hotplug_work,
>
> msecs_to_jiffies(HPD_RETRY_DELAY));
> spin_unlock_irq(&dev_priv->irq_lock);
> }
> @@ -572,7 +581,7 @@ static void i915_hotplug_work_func(struct work_struct
> *work)
>
> /**
> * intel_hpd_irq_handler - main hotplug irq handler
> - * @dev_priv: drm_i915_private
> + * @display: display device
> * @pin_mask: a mask of hpd pins that have triggered the irq
> * @long_mask: a mask of hpd pins that may be long hpd pulses
> *
> @@ -586,10 +595,10 @@ static void i915_hotplug_work_func(struct work_struct
> *work)
> * Here, we do hotplug irq storm detection and mitigation, and pass further
> * processing to appropriate bottom halves.
> */
> -void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> +void intel_hpd_irq_handler(struct intel_display *display,
> u32 pin_mask, u32 long_mask)
> {
> - struct intel_display *display = to_intel_display(&dev_priv->drm);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_encoder *encoder;
> bool storm_detected = false;
> bool queue_dig = false, queue_hp = false;
> @@ -608,7 +617,7 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
> * as each pin may have up to two encoders (HDMI and DP) and
> * only the one of them (DP) will have ->hpd_pulse().
> */
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> + for_each_intel_encoder(display->drm, encoder) {
> bool long_hpd;
>
> pin = encoder->hpd_pin;
> @@ -620,7 +629,7 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
>
> long_hpd = long_mask & BIT(pin);
>
> - drm_dbg(&dev_priv->drm,
> + drm_dbg(display->drm,
> "digital hpd on [ENCODER:%d:%s] - %s\n",
> encoder->base.base.id, encoder->base.name,
> long_hpd ? "long" : "short");
> @@ -630,10 +639,10 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
>
> if (long_hpd) {
> long_hpd_pulse_mask |= BIT(pin);
> - dev_priv->display.hotplug.long_hpd_pin_mask |=
> BIT(pin);
> + display->hotplug.long_hpd_pin_mask |= BIT(pin);
> } else {
> short_hpd_pulse_mask |= BIT(pin);
> - dev_priv->display.hotplug.short_hpd_pin_mask |=
> BIT(pin);
> + display->hotplug.short_hpd_pin_mask |= BIT(pin);
> }
> }
>
> @@ -644,20 +653,20 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
> if (!(BIT(pin) & pin_mask))
> continue;
>
> - if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
> {
> + if (display->hotplug.stats[pin].state == HPD_DISABLED) {
> /*
> * On GMCH platforms the interrupt mask bits only
> * prevent irq generation, not the setting of the
> * hotplug bits itself. So only WARN about unexpected
> * interrupts on saner platforms.
> */
> - drm_WARN_ONCE(&dev_priv->drm,
> !HAS_GMCH(dev_priv),
> + drm_WARN_ONCE(display->drm, !HAS_GMCH(display),
> "Received HPD interrupt on pin %d although
> disabled\n",
> pin);
> continue;
> }
>
> - if (dev_priv->display.hotplug.stats[pin].state != HPD_ENABLED)
> + if (display->hotplug.stats[pin].state != HPD_ENABLED)
> continue;
>
> /*
> @@ -668,15 +677,15 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
> if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin)))
> {
> long_hpd = long_hpd_pulse_mask & BIT(pin);
> } else {
> - dev_priv->display.hotplug.event_bits |= BIT(pin);
> + display->hotplug.event_bits |= BIT(pin);
> long_hpd = true;
>
> if (!hpd_pin_is_blocked(display, pin))
> queue_hp = true;
> }
>
> - if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) {
> - dev_priv->display.hotplug.event_bits &= ~BIT(pin);
> + if (intel_hpd_irq_storm_detect(display, pin, long_hpd)) {
> + display->hotplug.event_bits &= ~BIT(pin);
> storm_detected = true;
> queue_hp = true;
> }
> @@ -696,17 +705,17 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
> * deadlock.
> */
> if (queue_dig)
> - queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv-
> >display.hotplug.dig_port_work);
> + queue_work(display->hotplug.dp_wq, &display-
> >hotplug.dig_port_work);
> if (queue_hp)
> - queue_delayed_detection_work(dev_priv,
> - &dev_priv-
> >display.hotplug.hotplug_work, 0);
> + queue_delayed_detection_work(display,
> + &display->hotplug.hotplug_work, 0);
>
> spin_unlock(&dev_priv->irq_lock);
> }
>
> /**
> * intel_hpd_init - initializes and enables hpd support
> - * @dev_priv: i915 device instance
> + * @display: display device instance
> *
> * This function enables the hotplug support. It requires that interrupts have
> * already been enabled with intel_irq_init_hw(). From this point on hotplug and
> @@ -718,16 +727,17 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
> *
> * Also see: intel_hpd_poll_enable() and intel_hpd_poll_disable().
> */
> -void intel_hpd_init(struct drm_i915_private *dev_priv)
> +void intel_hpd_init(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int i;
>
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(display))
> return;
>
> for_each_hpd_pin(i) {
> - dev_priv->display.hotplug.stats[i].count = 0;
> - dev_priv->display.hotplug.stats[i].state = HPD_ENABLED;
> + display->hotplug.stats[i].count = 0;
> + display->hotplug.stats[i].state = HPD_ENABLED;
> }
>
> /*
> @@ -739,19 +749,19 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> -static void i915_hpd_poll_detect_connectors(struct drm_i915_private *i915)
> +static void i915_hpd_poll_detect_connectors(struct intel_display *display)
> {
> struct drm_connector_list_iter conn_iter;
> struct intel_connector *connector;
> struct intel_connector *first_changed_connector = NULL;
> int changed = 0;
>
> - mutex_lock(&i915->drm.mode_config.mutex);
> + mutex_lock(&display->drm->mode_config.mutex);
>
> - if (!i915->drm.mode_config.poll_enabled)
> + if (!display->drm->mode_config.poll_enabled)
> goto out;
>
> - drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> if (!(connector->base.polled & DRM_CONNECTOR_POLL_HPD))
> continue;
> @@ -769,7 +779,7 @@ static void i915_hpd_poll_detect_connectors(struct
> drm_i915_private *i915)
> drm_connector_list_iter_end(&conn_iter);
>
> out:
> - mutex_unlock(&i915->drm.mode_config.mutex);
> + mutex_unlock(&display->drm->mode_config.mutex);
>
> if (!changed)
> return;
> @@ -777,25 +787,24 @@ static void i915_hpd_poll_detect_connectors(struct
> drm_i915_private *i915)
> if (changed == 1)
>
> drm_kms_helper_connector_hotplug_event(&first_changed_connector-
> >base);
> else
> - drm_kms_helper_hotplug_event(&i915->drm);
> + drm_kms_helper_hotplug_event(display->drm);
>
> drm_connector_put(&first_changed_connector->base);
> }
>
> static void i915_hpd_poll_init_work(struct work_struct *work)
> {
> - struct drm_i915_private *dev_priv =
> - container_of(work, struct drm_i915_private,
> - display.hotplug.poll_init_work);
> - struct intel_display *display = &dev_priv->display;
> + struct intel_display *display =
> + container_of(work, typeof(*display), hotplug.poll_init_work);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct drm_connector_list_iter conn_iter;
> struct intel_connector *connector;
> intel_wakeref_t wakeref;
> bool enabled;
>
> - mutex_lock(&dev_priv->drm.mode_config.mutex);
> + mutex_lock(&display->drm->mode_config.mutex);
>
> - enabled = READ_ONCE(dev_priv->display.hotplug.poll_enabled);
> + enabled = READ_ONCE(display->hotplug.poll_enabled);
> /*
> * Prevent taking a power reference from this sequence of
> * i915_hpd_poll_init_work() -> drm_helper_hpd_irq_event() ->
> @@ -805,14 +814,14 @@ static void i915_hpd_poll_init_work(struct work_struct
> *work)
> if (!enabled) {
> wakeref = intel_display_power_get(display,
>
> POWER_DOMAIN_DISPLAY_CORE);
> - drm_WARN_ON(&dev_priv->drm,
> - READ_ONCE(dev_priv-
> >display.hotplug.poll_enabled));
> - cancel_work(&dev_priv->display.hotplug.poll_init_work);
> + drm_WARN_ON(display->drm,
> + READ_ONCE(display->hotplug.poll_enabled));
> + cancel_work(&display->hotplug.poll_init_work);
> }
>
> spin_lock_irq(&dev_priv->irq_lock);
>
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> enum hpd_pin pin;
>
> @@ -820,7 +829,7 @@ static void i915_hpd_poll_init_work(struct work_struct
> *work)
> if (pin == HPD_NONE)
> continue;
>
> - if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
> + if (display->hotplug.stats[pin].state == HPD_DISABLED)
> continue;
>
> connector->base.polled = connector->polled;
> @@ -834,16 +843,16 @@ static void i915_hpd_poll_init_work(struct work_struct
> *work)
> spin_unlock_irq(&dev_priv->irq_lock);
>
> if (enabled)
> - drm_kms_helper_poll_reschedule(&dev_priv->drm);
> + drm_kms_helper_poll_reschedule(display->drm);
>
> - mutex_unlock(&dev_priv->drm.mode_config.mutex);
> + mutex_unlock(&display->drm->mode_config.mutex);
>
> /*
> * We might have missed any hotplugs that happened while we were
> * in the middle of disabling polling
> */
> if (!enabled) {
> - i915_hpd_poll_detect_connectors(dev_priv);
> + i915_hpd_poll_detect_connectors(display);
>
> intel_display_power_put(display,
> POWER_DOMAIN_DISPLAY_CORE,
> @@ -853,7 +862,7 @@ static void i915_hpd_poll_init_work(struct work_struct
> *work)
>
> /**
> * intel_hpd_poll_enable - enable polling for connectors with hpd
> - * @dev_priv: i915 device instance
> + * @display: display device instance
> *
> * This function enables polling for all connectors which support HPD.
> * Under certain conditions HPD may not be functional. On most Intel GPUs,
> @@ -867,15 +876,14 @@ static void i915_hpd_poll_init_work(struct work_struct
> *work)
> *
> * Also see: intel_hpd_init() and intel_hpd_poll_disable().
> */
> -void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
> +void intel_hpd_poll_enable(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> - if (!HAS_DISPLAY(dev_priv) ||
> - !intel_display_device_enabled(display))
> + if (!HAS_DISPLAY(display) || !intel_display_device_enabled(display))
> return;
>
> - WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true);
> + WRITE_ONCE(display->hotplug.poll_enabled, true);
>
> /*
> * We might already be holding dev->mode_config.mutex, so do this in a
> @@ -884,14 +892,14 @@ void intel_hpd_poll_enable(struct drm_i915_private
> *dev_priv)
> * this worker anyway
> */
> spin_lock_irq(&dev_priv->irq_lock);
> - queue_detection_work(dev_priv,
> - &dev_priv->display.hotplug.poll_init_work);
> + queue_detection_work(display,
> + &display->hotplug.poll_init_work);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> /**
> * intel_hpd_poll_disable - disable polling for connectors with hpd
> - * @dev_priv: i915 device instance
> + * @display: display device instance
> *
> * This function disables polling for all connectors which support HPD.
> * Under certain conditions HPD may not be functional. On most Intel GPUs,
> @@ -908,26 +916,28 @@ void intel_hpd_poll_enable(struct drm_i915_private
> *dev_priv)
> *
> * Also see: intel_hpd_init() and intel_hpd_poll_enable().
> */
> -void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
> +void intel_hpd_poll_disable(struct intel_display *display)
> {
> - if (!HAS_DISPLAY(dev_priv))
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> + if (!HAS_DISPLAY(display))
> return;
>
> - WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, false);
> + WRITE_ONCE(display->hotplug.poll_enabled, false);
>
> spin_lock_irq(&dev_priv->irq_lock);
> - queue_detection_work(dev_priv,
> - &dev_priv->display.hotplug.poll_init_work);
> + queue_detection_work(display,
> + &display->hotplug.poll_init_work);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> -void intel_hpd_poll_fini(struct drm_i915_private *i915)
> +void intel_hpd_poll_fini(struct intel_display *display)
> {
> struct intel_connector *connector;
> struct drm_connector_list_iter conn_iter;
>
> /* Kill all the work that may have been queued by hpd. */
> - drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> intel_connector_cancel_modeset_retry_work(connector);
> intel_hdcp_cancel_works(connector);
> @@ -935,70 +945,70 @@ void intel_hpd_poll_fini(struct drm_i915_private
> *i915)
> drm_connector_list_iter_end(&conn_iter);
> }
>
> -void intel_hpd_init_early(struct drm_i915_private *i915)
> +void intel_hpd_init_early(struct intel_display *display)
> {
> - INIT_DELAYED_WORK(&i915->display.hotplug.hotplug_work,
> + INIT_DELAYED_WORK(&display->hotplug.hotplug_work,
> i915_hotplug_work_func);
> - INIT_WORK(&i915->display.hotplug.dig_port_work,
> i915_digport_work_func);
> - INIT_WORK(&i915->display.hotplug.poll_init_work,
> i915_hpd_poll_init_work);
> - INIT_DELAYED_WORK(&i915->display.hotplug.reenable_work,
> + INIT_WORK(&display->hotplug.dig_port_work, i915_digport_work_func);
> + INIT_WORK(&display->hotplug.poll_init_work, i915_hpd_poll_init_work);
> + INIT_DELAYED_WORK(&display->hotplug.reenable_work,
> intel_hpd_irq_storm_reenable_work);
>
> - i915->display.hotplug.hpd_storm_threshold =
> HPD_STORM_DEFAULT_THRESHOLD;
> + display->hotplug.hpd_storm_threshold =
> HPD_STORM_DEFAULT_THRESHOLD;
> /* If we have MST support, we want to avoid doing short HPD IRQ storm
> * detection, as short HPD storms will occur as a natural part of
> * sideband messaging with MST.
> * On older platforms however, IRQ storms can occur with both long and
> * short pulses, as seen on some G4x systems.
> */
> - i915->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(i915);
> + display->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(display);
> }
>
> -static bool cancel_all_detection_work(struct drm_i915_private *i915)
> +static bool cancel_all_detection_work(struct intel_display *display)
> {
> bool was_pending = false;
>
> - if (cancel_delayed_work_sync(&i915->display.hotplug.hotplug_work))
> + if (cancel_delayed_work_sync(&display->hotplug.hotplug_work))
> was_pending = true;
> - if (cancel_work_sync(&i915->display.hotplug.poll_init_work))
> + if (cancel_work_sync(&display->hotplug.poll_init_work))
> was_pending = true;
> - if (cancel_delayed_work_sync(&i915->display.hotplug.reenable_work))
> + if (cancel_delayed_work_sync(&display->hotplug.reenable_work))
> was_pending = true;
>
> return was_pending;
> }
>
> -void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
> +void intel_hpd_cancel_work(struct intel_display *display)
> {
> - struct intel_display *display = to_intel_display(&dev_priv->drm);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(display))
> return;
>
> spin_lock_irq(&dev_priv->irq_lock);
>
> drm_WARN_ON(display->drm, get_blocked_hpd_pin_mask(display));
>
> - dev_priv->display.hotplug.long_hpd_pin_mask = 0;
> - dev_priv->display.hotplug.short_hpd_pin_mask = 0;
> - dev_priv->display.hotplug.event_bits = 0;
> - dev_priv->display.hotplug.retry_bits = 0;
> + display->hotplug.long_hpd_pin_mask = 0;
> + display->hotplug.short_hpd_pin_mask = 0;
> + display->hotplug.event_bits = 0;
> + display->hotplug.retry_bits = 0;
>
> spin_unlock_irq(&dev_priv->irq_lock);
>
> - cancel_work_sync(&dev_priv->display.hotplug.dig_port_work);
> + cancel_work_sync(&display->hotplug.dig_port_work);
>
> /*
> * All other work triggered by hotplug events should be canceled by
> * now.
> */
> - if (cancel_all_detection_work(dev_priv))
> - drm_dbg_kms(&dev_priv->drm, "Hotplug detection work still
> active\n");
> + if (cancel_all_detection_work(display))
> + drm_dbg_kms(display->drm, "Hotplug detection work still
> active\n");
> }
>
> -static void queue_work_for_missed_irqs(struct drm_i915_private *i915)
> +static void queue_work_for_missed_irqs(struct intel_display *display)
> {
> - struct intel_display *display = to_intel_display(&i915->drm);
> + struct drm_i915_private *i915 = to_i915(display->drm);
> struct intel_hotplug *hotplug = &display->hotplug;
> bool queue_hp_work = false;
> u32 blocked_hpd_pin_mask;
> @@ -1011,7 +1021,7 @@ static void queue_work_for_missed_irqs(struct
> drm_i915_private *i915)
> queue_hp_work = true;
>
> for_each_hpd_pin(pin) {
> - switch (i915->display.hotplug.stats[pin].state) {
> + switch (display->hotplug.stats[pin].state) {
> case HPD_MARK_DISABLED:
> queue_hp_work = true;
> break;
> @@ -1019,7 +1029,7 @@ static void queue_work_for_missed_irqs(struct
> drm_i915_private *i915)
> case HPD_ENABLED:
> break;
> default:
> - MISSING_CASE(i915->display.hotplug.stats[pin].state);
> + MISSING_CASE(display->hotplug.stats[pin].state);
> }
> }
>
> @@ -1027,7 +1037,7 @@ static void queue_work_for_missed_irqs(struct
> drm_i915_private *i915)
> queue_work(hotplug->dp_wq, &hotplug->dig_port_work);
>
> if (queue_hp_work)
> - queue_delayed_detection_work(i915, &i915-
> >display.hotplug.hotplug_work, 0);
> + queue_delayed_detection_work(display, &display-
> >hotplug.hotplug_work, 0);
> }
>
> static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin)
> @@ -1121,7 +1131,7 @@ void intel_hpd_unblock(struct intel_encoder *encoder)
> spin_lock_irq(&i915->irq_lock);
>
> if (unblock_hpd_pin(display, encoder->hpd_pin))
> - queue_work_for_missed_irqs(i915);
> + queue_work_for_missed_irqs(display);
>
> spin_unlock_irq(&i915->irq_lock);
> }
> @@ -1156,30 +1166,35 @@ void intel_hpd_clear_and_unblock(struct
> intel_encoder *encoder)
> spin_unlock_irq(&i915->irq_lock);
> }
>
> -void intel_hpd_enable_detection_work(struct drm_i915_private *i915)
> +void intel_hpd_enable_detection_work(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> spin_lock_irq(&i915->irq_lock);
> - i915->display.hotplug.detection_work_enabled = true;
> - queue_work_for_missed_irqs(i915);
> + display->hotplug.detection_work_enabled = true;
> + queue_work_for_missed_irqs(display);
> spin_unlock_irq(&i915->irq_lock);
> }
>
> -void intel_hpd_disable_detection_work(struct drm_i915_private *i915)
> +void intel_hpd_disable_detection_work(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> spin_lock_irq(&i915->irq_lock);
> - i915->display.hotplug.detection_work_enabled = false;
> + display->hotplug.detection_work_enabled = false;
> spin_unlock_irq(&i915->irq_lock);
>
> - cancel_all_detection_work(i915);
> + cancel_all_detection_work(display);
> }
>
> -bool intel_hpd_schedule_detection(struct drm_i915_private *i915)
> +bool intel_hpd_schedule_detection(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> unsigned long flags;
> bool ret;
>
> spin_lock_irqsave(&i915->irq_lock, flags);
> - ret = queue_delayed_detection_work(i915, &i915-
> >display.hotplug.hotplug_work, 0);
> + ret = queue_delayed_detection_work(display, &display-
> >hotplug.hotplug_work, 0);
> spin_unlock_irqrestore(&i915->irq_lock, flags);
>
> return ret;
> @@ -1188,14 +1203,15 @@ bool intel_hpd_schedule_detection(struct
> drm_i915_private *i915)
> static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = m->private;
> - struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
> + struct intel_display *display = &dev_priv->display;
> + struct intel_hotplug *hotplug = &display->hotplug;
>
> /* Synchronize with everything first in case there's been an HPD
> * storm, but we haven't finished handling it in the kernel yet
> */
> intel_synchronize_irq(dev_priv);
> - flush_work(&dev_priv->display.hotplug.dig_port_work);
> - flush_delayed_work(&dev_priv->display.hotplug.hotplug_work);
> + flush_work(&display->hotplug.dig_port_work);
> + flush_delayed_work(&display->hotplug.hotplug_work);
>
> seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
> seq_printf(m, "Detected: %s\n",
> @@ -1210,7 +1226,8 @@ static ssize_t i915_hpd_storm_ctl_write(struct file
> *file,
> {
> struct seq_file *m = file->private_data;
> struct drm_i915_private *dev_priv = m->private;
> - struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
> + struct intel_display *display = &dev_priv->display;
> + struct intel_hotplug *hotplug = &display->hotplug;
> unsigned int new_threshold;
> int i;
> char *newline;
> @@ -1235,11 +1252,11 @@ static ssize_t i915_hpd_storm_ctl_write(struct file
> *file,
> return -EINVAL;
>
> if (new_threshold > 0)
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Setting HPD storm detection threshold to %d\n",
> new_threshold);
> else
> - drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm
> detection\n");
> + drm_dbg_kms(display->drm, "Disabling HPD storm detection\n");
>
> spin_lock_irq(&dev_priv->irq_lock);
> hotplug->hpd_storm_threshold = new_threshold;
> @@ -1249,7 +1266,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file
> *file,
> spin_unlock_irq(&dev_priv->irq_lock);
>
> /* Re-enable hpd immediately if we were in an irq storm */
> - flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
> + flush_delayed_work(&display->hotplug.reenable_work);
>
> return len;
> }
> @@ -1271,9 +1288,10 @@ static const struct file_operations
> i915_hpd_storm_ctl_fops = {
> static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = m->private;
> + struct intel_display *display = &dev_priv->display;
>
> seq_printf(m, "Enabled: %s\n",
> - str_yes_no(dev_priv-
> >display.hotplug.hpd_short_storm_enabled));
> + str_yes_no(display->hotplug.hpd_short_storm_enabled));
>
> return 0;
> }
> @@ -1291,7 +1309,8 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct
> file *file,
> {
> struct seq_file *m = file->private_data;
> struct drm_i915_private *dev_priv = m->private;
> - struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
> + struct intel_display *display = &dev_priv->display;
> + struct intel_hotplug *hotplug = &display->hotplug;
> char *newline;
> char tmp[16];
> int i;
> @@ -1312,11 +1331,11 @@ static ssize_t
> i915_hpd_short_storm_ctl_write(struct file *file,
>
> /* Reset to the "default" state for this system */
> if (strcmp(tmp, "reset") == 0)
> - new_state = !HAS_DP_MST(dev_priv);
> + new_state = !HAS_DP_MST(display);
> else if (kstrtobool(tmp, &new_state) != 0)
> return -EINVAL;
>
> - drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n",
> + drm_dbg_kms(display->drm, "%sabling HPD short storm detection\n",
> new_state ? "En" : "Dis");
>
> spin_lock_irq(&dev_priv->irq_lock);
> @@ -1327,7 +1346,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct
> file *file,
> spin_unlock_irq(&dev_priv->irq_lock);
>
> /* Re-enable hpd immediately if we were in an irq storm */
> - flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
> + flush_delayed_work(&display->hotplug.reenable_work);
>
> return len;
> }
> @@ -1341,14 +1360,15 @@ static const struct file_operations
> i915_hpd_short_storm_ctl_fops = {
> .write = i915_hpd_short_storm_ctl_write,
> };
>
> -void intel_hpd_debugfs_register(struct drm_i915_private *i915)
> +void intel_hpd_debugfs_register(struct intel_display *display)
> {
> - struct drm_minor *minor = i915->drm.primary;
> + struct drm_minor *minor = display->drm->primary;
> + struct drm_i915_private *i915 = to_i915(display->drm);
>
> debugfs_create_file("i915_hpd_storm_ctl", 0644, minor->debugfs_root,
> i915, &i915_hpd_storm_ctl_fops);
> debugfs_create_file("i915_hpd_short_storm_ctl", 0644, minor-
> >debugfs_root,
> i915, &i915_hpd_short_storm_ctl_fops);
> debugfs_create_bool("i915_ignore_long_hpd", 0644, minor-
> >debugfs_root,
> - &i915->display.hotplug.ignore_long_hpd);
> + &display->hotplug.ignore_long_hpd);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h
> b/drivers/gpu/drm/i915/display/intel_hotplug.h
> index f189b871904e..edc41c9d3d65 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.h
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
> @@ -8,31 +8,31 @@
>
> #include <linux/types.h>
>
> -struct drm_i915_private;
> +enum port;
> struct intel_connector;
> struct intel_digital_port;
> +struct intel_display;
> struct intel_encoder;
> -enum port;
>
> -void intel_hpd_poll_enable(struct drm_i915_private *dev_priv);
> -void intel_hpd_poll_disable(struct drm_i915_private *dev_priv);
> -void intel_hpd_poll_fini(struct drm_i915_private *i915);
> +void intel_hpd_poll_enable(struct intel_display *display);
> +void intel_hpd_poll_disable(struct intel_display *display);
> +void intel_hpd_poll_fini(struct intel_display *display);
> enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder,
> struct intel_connector *connector);
> -void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> +void intel_hpd_irq_handler(struct intel_display *display,
> u32 pin_mask, u32 long_mask);
> void intel_hpd_trigger_irq(struct intel_digital_port *dig_port);
> -void intel_hpd_init(struct drm_i915_private *dev_priv);
> -void intel_hpd_init_early(struct drm_i915_private *i915);
> -void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
> +void intel_hpd_init(struct intel_display *display);
> +void intel_hpd_init_early(struct intel_display *display);
> +void intel_hpd_cancel_work(struct intel_display *display);
> enum hpd_pin intel_hpd_pin_default(enum port port);
> void intel_hpd_block(struct intel_encoder *encoder);
> void intel_hpd_unblock(struct intel_encoder *encoder);
> void intel_hpd_clear_and_unblock(struct intel_encoder *encoder);
> -void intel_hpd_debugfs_register(struct drm_i915_private *i915);
> +void intel_hpd_debugfs_register(struct intel_display *display);
>
> -void intel_hpd_enable_detection_work(struct drm_i915_private *i915);
> -void intel_hpd_disable_detection_work(struct drm_i915_private *i915);
> -bool intel_hpd_schedule_detection(struct drm_i915_private *i915);
> +void intel_hpd_enable_detection_work(struct intel_display *display);
> +void intel_hpd_disable_detection_work(struct intel_display *display);
> +bool intel_hpd_schedule_detection(struct intel_display *display);
>
> #endif /* __INTEL_HOTPLUG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 2137ac7b882a..e6320838df59 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -472,7 +472,7 @@ void i9xx_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 hotplug_status)
> dev_priv->display.hotplug.hpd,
> i9xx_port_hotplug_long_detect);
>
> - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> + intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> if ((IS_G4X(dev_priv) ||
> @@ -483,6 +483,7 @@ void i9xx_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 hotplug_status)
>
> void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_trigger)
> {
> + struct intel_display *display = &dev_priv->display;
> u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
>
> /*
> @@ -509,7 +510,7 @@ void ibx_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 hotplug_trigger)
> dev_priv->display.hotplug.pch_hpd,
> pch_port_hotplug_long_detect);
>
> - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> + intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
> @@ -543,7 +544,7 @@ void xelpdp_pica_irq_handler(struct drm_i915_private
> *i915, u32 iir)
> "pica hotplug event received, stat 0x%08x, pins 0x%08x,
> long 0x%08x\n",
> hotplug_trigger, pin_mask, long_mask);
>
> - intel_hpd_irq_handler(i915, pin_mask, long_mask);
> + intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> if (trigger_aux)
> @@ -587,7 +588,7 @@ void icp_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
> }
>
> if (pin_mask)
> - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> + intel_hpd_irq_handler(display, pin_mask, long_mask);
>
> if (pch_iir & SDE_GMBUS_ICP)
> intel_gmbus_irq_handler(display);
> @@ -624,7 +625,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
> }
>
> if (pin_mask)
> - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> + intel_hpd_irq_handler(display, pin_mask, long_mask);
>
> if (pch_iir & SDE_GMBUS_CPT)
> intel_gmbus_irq_handler(display);
> @@ -632,6 +633,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
>
> void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_trigger)
> {
> + struct intel_display *display = &dev_priv->display;
> u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
>
> dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
> @@ -641,11 +643,12 @@ void ilk_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 hotplug_trigger)
> dev_priv->display.hotplug.hpd,
> ilk_port_hotplug_long_detect);
>
> - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> + intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_trigger)
> {
> + struct intel_display *display = &dev_priv->display;
> u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
>
> dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> PCH_PORT_HOTPLUG, 0, 0);
> @@ -655,11 +658,12 @@ void bxt_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 hotplug_trigger)
> dev_priv->display.hotplug.hpd,
> bxt_port_hotplug_long_detect);
>
> - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> + intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> {
> + struct intel_display *display = &dev_priv->display;
> u32 pin_mask = 0, long_mask = 0;
> u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
> u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
> @@ -687,7 +691,7 @@ void gen11_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> }
>
> if (pin_mask)
> - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> + intel_hpd_irq_handler(display, pin_mask, long_mask);
> else
> drm_err(&dev_priv->drm,
> "Unexpected DE HPD interrupt 0x%08x\n", iir);
> @@ -1467,9 +1471,11 @@ void intel_hpd_irq_setup(struct drm_i915_private
> *i915)
>
> void intel_hotplug_irq_init(struct drm_i915_private *i915)
> {
> + struct intel_display *display = &i915->display;
> +
> intel_hpd_init_pins(i915);
>
> - intel_hpd_init_early(i915);
> + intel_hpd_init_early(display);
>
> if (HAS_GMCH(i915)) {
> if (I915_HAS_HOTPLUG(i915))
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index ce3cc93ea211..510e240c000b 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -981,7 +981,7 @@ void i915_driver_shutdown(struct drm_i915_private
> *i915)
> intel_dp_mst_suspend(display);
>
> intel_irq_suspend(i915);
> - intel_hpd_cancel_work(i915);
> + intel_hpd_cancel_work(display);
>
> if (HAS_DISPLAY(i915))
> intel_display_driver_suspend_access(display);
> @@ -1064,7 +1064,7 @@ static int i915_drm_suspend(struct drm_device *dev)
> intel_display_driver_suspend(display);
>
> intel_irq_suspend(dev_priv);
> - intel_hpd_cancel_work(dev_priv);
> + intel_hpd_cancel_work(display);
>
> if (HAS_DISPLAY(dev_priv))
> intel_display_driver_suspend_access(display);
> @@ -1227,7 +1227,7 @@ static int i915_drm_resume(struct drm_device *dev)
> if (HAS_DISPLAY(dev_priv))
> intel_display_driver_resume_access(display);
>
> - intel_hpd_init(dev_priv);
> + intel_hpd_init(display);
>
> intel_display_driver_resume(display);
>
> @@ -1235,7 +1235,7 @@ static int i915_drm_resume(struct drm_device *dev)
> intel_display_driver_enable_user_access(display);
> drm_kms_helper_poll_enable(dev);
> }
> - intel_hpd_poll_disable(dev_priv);
> + intel_hpd_poll_disable(display);
>
> intel_opregion_resume(display);
>
> @@ -1575,7 +1575,7 @@ static int intel_runtime_suspend(struct device *kdev)
> assert_forcewakes_inactive(&dev_priv->uncore);
>
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
> - intel_hpd_poll_enable(dev_priv);
> + intel_hpd_poll_enable(display);
>
> drm_dbg(&dev_priv->drm, "Device suspended\n");
> return 0;
> @@ -1633,8 +1633,8 @@ static int intel_runtime_resume(struct device *kdev)
> * everyone else do it here.
> */
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
> - intel_hpd_init(dev_priv);
> - intel_hpd_poll_disable(dev_priv);
> + intel_hpd_init(display);
> + intel_hpd_poll_disable(display);
> }
>
> skl_watermark_ipc_update(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 37ca4a35daf2..de53615571be 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1280,6 +1280,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
> */
> void intel_irq_uninstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> int irq = to_pci_dev(dev_priv->drm.dev)->irq;
>
> if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled))
> @@ -1289,7 +1290,7 @@ void intel_irq_uninstall(struct drm_i915_private
> *dev_priv)
>
> free_irq(irq, dev_priv);
>
> - intel_hpd_cancel_work(dev_priv);
> + intel_hpd_cancel_work(display);
> dev_priv->irqs_enabled = false;
> }
>
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c
> b/drivers/gpu/drm/xe/display/xe_display.c
> index 0b0aca7a25af..263459323bf7 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -173,7 +173,7 @@ static void xe_display_fini(void *arg)
> struct xe_device *xe = arg;
> struct intel_display *display = &xe->display;
>
> - intel_hpd_poll_fini(xe);
> + intel_hpd_poll_fini(display);
> intel_hdcp_component_fini(display);
> intel_audio_deinit(display);
> intel_display_driver_remove(display);
> @@ -305,7 +305,7 @@ static void xe_display_enable_d3cold(struct xe_device
> *xe)
> intel_dmc_suspend(display);
>
> if (has_display(xe))
> - intel_hpd_poll_enable(xe);
> + intel_hpd_poll_enable(display);
> }
>
> static void xe_display_disable_d3cold(struct xe_device *xe)
> @@ -322,10 +322,10 @@ static void xe_display_disable_d3cold(struct xe_device
> *xe)
>
> intel_display_driver_init_hw(display);
>
> - intel_hpd_init(xe);
> + intel_hpd_init(display);
>
> if (has_display(xe))
> - intel_hpd_poll_disable(xe);
> + intel_hpd_poll_disable(display);
>
> intel_opregion_resume(display);
>
> @@ -355,7 +355,7 @@ void xe_display_pm_suspend(struct xe_device *xe)
>
> xe_display_flush_cleanup_work(xe);
>
> - intel_hpd_cancel_work(xe);
> + intel_hpd_cancel_work(display);
>
> if (has_display(xe)) {
> intel_display_driver_suspend_access(display);
> @@ -385,7 +385,7 @@ void xe_display_pm_shutdown(struct xe_device *xe)
>
> xe_display_flush_cleanup_work(xe);
> intel_dp_mst_suspend(display);
> - intel_hpd_cancel_work(xe);
> + intel_hpd_cancel_work(display);
>
> if (has_display(xe))
> intel_display_driver_suspend_access(display);
> @@ -400,6 +400,8 @@ void xe_display_pm_shutdown(struct xe_device *xe)
>
> void xe_display_pm_runtime_suspend(struct xe_device *xe)
> {
> + struct intel_display *display = &xe->display;
> +
> if (!xe->info.probe_display)
> return;
>
> @@ -408,7 +410,7 @@ void xe_display_pm_runtime_suspend(struct xe_device
> *xe)
> return;
> }
>
> - intel_hpd_poll_enable(xe);
> + intel_hpd_poll_enable(display);
> }
>
> void xe_display_pm_suspend_late(struct xe_device *xe)
> @@ -482,7 +484,7 @@ void xe_display_pm_resume(struct xe_device *xe)
> if (has_display(xe))
> intel_display_driver_resume_access(display);
>
> - intel_hpd_init(xe);
> + intel_hpd_init(display);
>
> if (has_display(xe)) {
> intel_display_driver_resume(display);
> @@ -491,7 +493,7 @@ void xe_display_pm_resume(struct xe_device *xe)
> }
>
> if (has_display(xe))
> - intel_hpd_poll_disable(xe);
> + intel_hpd_poll_disable(display);
>
> intel_opregion_resume(display);
>
> @@ -502,6 +504,8 @@ void xe_display_pm_resume(struct xe_device *xe)
>
> void xe_display_pm_runtime_resume(struct xe_device *xe)
> {
> + struct intel_display *display = &xe->display;
> +
> if (!xe->info.probe_display)
> return;
>
> @@ -510,8 +514,8 @@ void xe_display_pm_runtime_resume(struct xe_device
> *xe)
> return;
> }
>
> - intel_hpd_init(xe);
> - intel_hpd_poll_disable(xe);
> + intel_hpd_init(display);
> + intel_hpd_poll_disable(display);
> skl_watermark_ipc_update(xe);
> }
>
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 4/9] drm/i915/hotplug: convert hotplug debugfs to struct intel_display
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (2 preceding siblings ...)
2025-03-11 18:00 ` [PATCH 3/9] drm/i915/hotplug: convert intel_hotplug.[ch] " Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-12 5:17 ` Shankar, Uma
2025-03-11 18:00 ` [PATCH 5/9] drm/i915/hotplug: convert hotplug irq handling to intel_de_*() Jani Nikula
` (14 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Pass struct intel_display as the cookie to debugfs functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 9bde28ce1979..7683b3ce124d 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -1202,8 +1202,8 @@ bool intel_hpd_schedule_detection(struct intel_display *display)
static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
{
- struct drm_i915_private *dev_priv = m->private;
- struct intel_display *display = &dev_priv->display;
+ struct intel_display *display = m->private;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_hotplug *hotplug = &display->hotplug;
/* Synchronize with everything first in case there's been an HPD
@@ -1225,8 +1225,8 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
loff_t *offp)
{
struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
- struct intel_display *display = &dev_priv->display;
+ struct intel_display *display = m->private;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_hotplug *hotplug = &display->hotplug;
unsigned int new_threshold;
int i;
@@ -1287,8 +1287,7 @@ static const struct file_operations i915_hpd_storm_ctl_fops = {
static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
{
- struct drm_i915_private *dev_priv = m->private;
- struct intel_display *display = &dev_priv->display;
+ struct intel_display *display = m->private;
seq_printf(m, "Enabled: %s\n",
str_yes_no(display->hotplug.hpd_short_storm_enabled));
@@ -1308,8 +1307,8 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
size_t len, loff_t *offp)
{
struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
- struct intel_display *display = &dev_priv->display;
+ struct intel_display *display = m->private;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_hotplug *hotplug = &display->hotplug;
char *newline;
char tmp[16];
@@ -1363,12 +1362,11 @@ static const struct file_operations i915_hpd_short_storm_ctl_fops = {
void intel_hpd_debugfs_register(struct intel_display *display)
{
struct drm_minor *minor = display->drm->primary;
- struct drm_i915_private *i915 = to_i915(display->drm);
debugfs_create_file("i915_hpd_storm_ctl", 0644, minor->debugfs_root,
- i915, &i915_hpd_storm_ctl_fops);
+ display, &i915_hpd_storm_ctl_fops);
debugfs_create_file("i915_hpd_short_storm_ctl", 0644, minor->debugfs_root,
- i915, &i915_hpd_short_storm_ctl_fops);
+ display, &i915_hpd_short_storm_ctl_fops);
debugfs_create_bool("i915_ignore_long_hpd", 0644, minor->debugfs_root,
&display->hotplug.ignore_long_hpd);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* RE: [PATCH 4/9] drm/i915/hotplug: convert hotplug debugfs to struct intel_display
2025-03-11 18:00 ` [PATCH 4/9] drm/i915/hotplug: convert hotplug debugfs " Jani Nikula
@ 2025-03-12 5:17 ` Shankar, Uma
0 siblings, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 5:17 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 4/9] drm/i915/hotplug: convert hotplug debugfs to struct
> intel_display
>
> Pass struct intel_display as the cookie to debugfs functions.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hotplug.c | 20 +++++++++-----------
> 1 file changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 9bde28ce1979..7683b3ce124d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -1202,8 +1202,8 @@ bool intel_hpd_schedule_detection(struct intel_display
> *display)
>
> static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) {
> - struct drm_i915_private *dev_priv = m->private;
> - struct intel_display *display = &dev_priv->display;
> + struct intel_display *display = m->private;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_hotplug *hotplug = &display->hotplug;
>
> /* Synchronize with everything first in case there's been an HPD @@ -
> 1225,8 +1225,8 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
> loff_t *offp)
> {
> struct seq_file *m = file->private_data;
> - struct drm_i915_private *dev_priv = m->private;
> - struct intel_display *display = &dev_priv->display;
> + struct intel_display *display = m->private;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_hotplug *hotplug = &display->hotplug;
> unsigned int new_threshold;
> int i;
> @@ -1287,8 +1287,7 @@ static const struct file_operations
> i915_hpd_storm_ctl_fops = {
>
> static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data) {
> - struct drm_i915_private *dev_priv = m->private;
> - struct intel_display *display = &dev_priv->display;
> + struct intel_display *display = m->private;
>
> seq_printf(m, "Enabled: %s\n",
> str_yes_no(display->hotplug.hpd_short_storm_enabled));
> @@ -1308,8 +1307,8 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct
> file *file,
> size_t len, loff_t *offp)
> {
> struct seq_file *m = file->private_data;
> - struct drm_i915_private *dev_priv = m->private;
> - struct intel_display *display = &dev_priv->display;
> + struct intel_display *display = m->private;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_hotplug *hotplug = &display->hotplug;
> char *newline;
> char tmp[16];
> @@ -1363,12 +1362,11 @@ static const struct file_operations
> i915_hpd_short_storm_ctl_fops = { void intel_hpd_debugfs_register(struct
> intel_display *display) {
> struct drm_minor *minor = display->drm->primary;
> - struct drm_i915_private *i915 = to_i915(display->drm);
>
> debugfs_create_file("i915_hpd_storm_ctl", 0644, minor->debugfs_root,
> - i915, &i915_hpd_storm_ctl_fops);
> + display, &i915_hpd_storm_ctl_fops);
> debugfs_create_file("i915_hpd_short_storm_ctl", 0644, minor-
> >debugfs_root,
> - i915, &i915_hpd_short_storm_ctl_fops);
> + display, &i915_hpd_short_storm_ctl_fops);
> debugfs_create_bool("i915_ignore_long_hpd", 0644, minor-
> >debugfs_root,
> &display->hotplug.ignore_long_hpd);
> }
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 5/9] drm/i915/hotplug: convert hotplug irq handling to intel_de_*()
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (3 preceding siblings ...)
2025-03-11 18:00 ` [PATCH 4/9] drm/i915/hotplug: convert hotplug debugfs " Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-12 5:23 ` Shankar, Uma
2025-03-11 18:00 ` [PATCH 6/9] drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct intel_display Jani Nikula
` (13 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
All the registers handled here are display registers. Switch from
intel_uncore_*() to intel_de_*() functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_hotplug_irq.c | 205 ++++++++++--------
1 file changed, 114 insertions(+), 91 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index e6320838df59..f24c65478742 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -183,11 +183,12 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
u32 mask, u32 bits)
{
+ struct intel_display *display = &dev_priv->display;
+
lockdep_assert_held(&dev_priv->irq_lock);
drm_WARN_ON(&dev_priv->drm, bits & ~mask);
- intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN(dev_priv), mask,
- bits);
+ intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);
}
/**
@@ -415,6 +416,7 @@ static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
u32 hotplug_status = 0, hotplug_status_mask;
int i;
@@ -435,21 +437,20 @@ u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
* bits can itself generate a new hotplug interrupt :(
*/
for (i = 0; i < 10; i++) {
- u32 tmp = intel_uncore_read(&dev_priv->uncore,
- PORT_HOTPLUG_STAT(dev_priv)) & hotplug_status_mask;
+ u32 tmp = intel_de_read(display,
+ PORT_HOTPLUG_STAT(display)) & hotplug_status_mask;
if (tmp == 0)
return hotplug_status;
hotplug_status |= tmp;
- intel_uncore_write(&dev_priv->uncore,
- PORT_HOTPLUG_STAT(dev_priv),
- hotplug_status);
+ intel_de_write(display, PORT_HOTPLUG_STAT(display),
+ hotplug_status);
}
drm_WARN_ONCE(&dev_priv->drm, 1,
"PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
- intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT(dev_priv)));
+ intel_de_read(display, PORT_HOTPLUG_STAT(display)));
return hotplug_status;
}
@@ -492,7 +493,7 @@ void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
* zero. Not acking leads to "The master control interrupt lied (SDE)!"
* errors.
*/
- dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
+ dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);
if (!hotplug_trigger) {
u32 mask = PORTA_HOTPLUG_STATUS_MASK |
PORTD_HOTPLUG_STATUS_MASK |
@@ -501,7 +502,7 @@ void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
dig_hotplug_reg &= ~mask;
}
- intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
+ intel_de_write(display, PCH_PORT_HOTPLUG, dig_hotplug_reg);
if (!hotplug_trigger)
return;
@@ -567,7 +568,7 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
/* Locking due to DSI native GPIO sequences */
spin_lock(&dev_priv->irq_lock);
- dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI, 0, 0);
+ dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0);
spin_unlock(&dev_priv->irq_lock);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
@@ -579,7 +580,7 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
if (tc_hotplug_trigger) {
u32 dig_hotplug_reg;
- dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC, 0, 0);
+ dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
tc_hotplug_trigger, dig_hotplug_reg,
@@ -605,7 +606,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
if (hotplug_trigger) {
u32 dig_hotplug_reg;
- dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
+ dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
@@ -616,7 +617,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
if (hotplug2_trigger) {
u32 dig_hotplug_reg;
- dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2, 0, 0);
+ dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug2_trigger, dig_hotplug_reg,
@@ -636,7 +637,7 @@ void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
struct intel_display *display = &dev_priv->display;
u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
- dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
+ dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
@@ -651,7 +652,7 @@ void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
struct intel_display *display = &dev_priv->display;
u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
- dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
+ dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
@@ -671,7 +672,7 @@ void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
if (trigger_tc) {
u32 dig_hotplug_reg;
- dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, 0, 0);
+ dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
trigger_tc, dig_hotplug_reg,
@@ -682,7 +683,7 @@ void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
if (trigger_tbt) {
u32 dig_hotplug_reg;
- dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, 0, 0);
+ dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
trigger_tbt, dig_hotplug_reg,
@@ -741,23 +742,25 @@ static u32 ibx_hotplug_enables(struct intel_encoder *encoder)
static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
/*
* Enable digital hotplug on the PCH, and configure the DP short pulse
* duration to 2ms (which is the minimum in the Display Port spec).
* The pulse duration bits are reserved on LPT+.
*/
- intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
- intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
+ intel_de_rmw(display, PCH_PORT_HOTPLUG,
+ intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
+ intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
}
static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
- ibx_hotplug_mask(encoder->hpd_pin),
- ibx_hotplug_enables(encoder));
+ intel_de_rmw(display, PCH_PORT_HOTPLUG,
+ ibx_hotplug_mask(encoder->hpd_pin),
+ ibx_hotplug_enables(encoder));
}
static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -812,34 +815,38 @@ static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
- intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI,
- intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables));
+ struct intel_display *display = &dev_priv->display;
+
+ intel_de_rmw(display, SHOTPLUG_CTL_DDI,
+ intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
+ intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables));
}
static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_DDI,
- icp_ddi_hotplug_mask(encoder->hpd_pin),
- icp_ddi_hotplug_enables(encoder));
+ intel_de_rmw(display, SHOTPLUG_CTL_DDI,
+ icp_ddi_hotplug_mask(encoder->hpd_pin),
+ icp_ddi_hotplug_enables(encoder));
}
static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
- intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC,
- intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables));
+ struct intel_display *display = &dev_priv->display;
+
+ intel_de_rmw(display, SHOTPLUG_CTL_TC,
+ intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
+ intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables));
}
static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_TC,
- icp_tc_hotplug_mask(encoder->hpd_pin),
- icp_tc_hotplug_enables(encoder));
+ intel_de_rmw(display, SHOTPLUG_CTL_TC,
+ icp_tc_hotplug_mask(encoder->hpd_pin),
+ icp_tc_hotplug_enables(encoder));
}
static void icp_hpd_enable_detection(struct intel_encoder *encoder)
@@ -850,6 +857,7 @@ static void icp_hpd_enable_detection(struct intel_encoder *encoder)
static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
@@ -859,7 +867,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
* We reduce the value to 250us to be able to detect SHPD when an external display
* is connected. This is also expected of us as stated in DP1.4a Table 3-4.
*/
- intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
+ intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
@@ -889,11 +897,12 @@ static u32 gen11_hotplug_enables(struct intel_encoder *encoder)
static void dg1_hpd_invert(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
u32 val = (INVERT_DDIA_HPD |
INVERT_DDIB_HPD |
INVERT_DDIC_HPD |
INVERT_DDID_HPD);
- intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val);
+ intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);
}
static void dg1_hpd_enable_detection(struct intel_encoder *encoder)
@@ -912,34 +921,38 @@ static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
- intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL,
- intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
+ struct intel_display *display = &dev_priv->display;
+
+ intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
+ intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
+ intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
}
static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_uncore_rmw(&i915->uncore, GEN11_TC_HOTPLUG_CTL,
- gen11_hotplug_mask(encoder->hpd_pin),
- gen11_hotplug_enables(encoder));
+ intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
+ gen11_hotplug_mask(encoder->hpd_pin),
+ gen11_hotplug_enables(encoder));
}
static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
- intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL,
- intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
+ struct intel_display *display = &dev_priv->display;
+
+ intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
+ intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
+ intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
}
static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_uncore_rmw(&i915->uncore, GEN11_TBT_HOTPLUG_CTL,
- gen11_hotplug_mask(encoder->hpd_pin),
- gen11_hotplug_enables(encoder));
+ intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
+ gen11_hotplug_mask(encoder->hpd_pin),
+ gen11_hotplug_enables(encoder));
}
static void gen11_hpd_enable_detection(struct intel_encoder *encoder)
@@ -955,14 +968,15 @@ static void gen11_hpd_enable_detection(struct intel_encoder *encoder)
static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
- intel_uncore_rmw(&dev_priv->uncore, GEN11_DE_HPD_IMR, hotplug_irqs,
- ~enabled_irqs & hotplug_irqs);
- intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
+ intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs,
+ ~enabled_irqs & hotplug_irqs);
+ intel_de_posting_read(display, GEN11_DE_HPD_IMR);
gen11_tc_hpd_detection_setup(dev_priv);
gen11_tbt_hpd_detection_setup(dev_priv);
@@ -1141,6 +1155,7 @@ static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd);
@@ -1148,7 +1163,7 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs,
~enabled_irqs & hotplug_irqs);
- intel_uncore_posting_read(&i915->uncore, PICAINTERRUPT_IMR);
+ intel_de_posting_read(display, PICAINTERRUPT_IMR);
xelpdp_pica_hpd_detection_setup(i915);
@@ -1196,48 +1211,52 @@ static u32 spt_hotplug2_enables(struct intel_encoder *encoder)
static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
/* Display WA #1179 WaHardHangonHotPlug: cnp */
if (HAS_PCH_CNP(dev_priv)) {
- intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
- CHASSIS_CLK_REQ_DURATION(0xf));
+ intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
+ CHASSIS_CLK_REQ_DURATION(0xf));
}
/* Enable digital hotplug on the PCH */
- intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
- intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
+ intel_de_rmw(display, PCH_PORT_HOTPLUG,
+ intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
+ intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
- intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2,
- intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
- intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
+ intel_de_rmw(display, PCH_PORT_HOTPLUG2,
+ intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
+ intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
}
static void spt_hpd_enable_detection(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
/* Display WA #1179 WaHardHangonHotPlug: cnp */
if (HAS_PCH_CNP(i915)) {
- intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1,
- CHASSIS_CLK_REQ_DURATION_MASK,
- CHASSIS_CLK_REQ_DURATION(0xf));
+ intel_de_rmw(display, SOUTH_CHICKEN1,
+ CHASSIS_CLK_REQ_DURATION_MASK,
+ CHASSIS_CLK_REQ_DURATION(0xf));
}
- intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
- spt_hotplug_mask(encoder->hpd_pin),
- spt_hotplug_enables(encoder));
+ intel_de_rmw(display, PCH_PORT_HOTPLUG,
+ spt_hotplug_mask(encoder->hpd_pin),
+ spt_hotplug_enables(encoder));
- intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG2,
- spt_hotplug2_mask(encoder->hpd_pin),
- spt_hotplug2_enables(encoder));
+ intel_de_rmw(display, PCH_PORT_HOTPLUG2,
+ spt_hotplug2_mask(encoder->hpd_pin),
+ spt_hotplug2_enables(encoder));
}
static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
u32 hotplug_irqs, enabled_irqs;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
- intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+ intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
@@ -1271,23 +1290,25 @@ static u32 ilk_hotplug_enables(struct intel_encoder *encoder)
static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
/*
* Enable digital hotplug on the CPU, and configure the DP short pulse
* duration to 2ms (which is the minimum in the Display Port spec)
* The pulse duration bits are reserved on HSW+.
*/
- intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
- intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
+ intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
+ intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
+ intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
}
static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_uncore_rmw(&i915->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
- ilk_hotplug_mask(encoder->hpd_pin),
- ilk_hotplug_enables(encoder));
+ intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
+ ilk_hotplug_mask(encoder->hpd_pin),
+ ilk_hotplug_enables(encoder));
ibx_hpd_enable_detection(encoder);
}
@@ -1350,18 +1371,20 @@ static u32 bxt_hotplug_enables(struct intel_encoder *encoder)
static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
- intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
- intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
+ struct intel_display *display = &dev_priv->display;
+
+ intel_de_rmw(display, PCH_PORT_HOTPLUG,
+ intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
+ intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
}
static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
- bxt_hotplug_mask(encoder->hpd_pin),
- bxt_hotplug_enables(encoder));
+ intel_de_rmw(display, PCH_PORT_HOTPLUG,
+ bxt_hotplug_mask(encoder->hpd_pin),
+ bxt_hotplug_enables(encoder));
}
static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* RE: [PATCH 5/9] drm/i915/hotplug: convert hotplug irq handling to intel_de_*()
2025-03-11 18:00 ` [PATCH 5/9] drm/i915/hotplug: convert hotplug irq handling to intel_de_*() Jani Nikula
@ 2025-03-12 5:23 ` Shankar, Uma
0 siblings, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 5:23 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 5/9] drm/i915/hotplug: convert hotplug irq handling to
> intel_de_*()
>
> All the registers handled here are display registers. Switch from
> intel_uncore_*() to intel_de_*() functions.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 205 ++++++++++--------
> 1 file changed, 114 insertions(+), 91 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index e6320838df59..f24c65478742 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -183,11 +183,12 @@ static void intel_hpd_init_pins(struct drm_i915_private
> *dev_priv) void i915_hotplug_interrupt_update_locked(struct drm_i915_private
> *dev_priv,
> u32 mask, u32 bits)
> {
> + struct intel_display *display = &dev_priv->display;
> +
> lockdep_assert_held(&dev_priv->irq_lock);
> drm_WARN_ON(&dev_priv->drm, bits & ~mask);
>
> - intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN(dev_priv),
> mask,
> - bits);
> + intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);
> }
>
> /**
> @@ -415,6 +416,7 @@ static u32 intel_hpd_hotplug_enables(struct
> drm_i915_private *i915,
>
> u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) {
> + struct intel_display *display = &dev_priv->display;
> u32 hotplug_status = 0, hotplug_status_mask;
> int i;
>
> @@ -435,21 +437,20 @@ u32 i9xx_hpd_irq_ack(struct drm_i915_private
> *dev_priv)
> * bits can itself generate a new hotplug interrupt :(
> */
> for (i = 0; i < 10; i++) {
> - u32 tmp = intel_uncore_read(&dev_priv->uncore,
> - PORT_HOTPLUG_STAT(dev_priv)) &
> hotplug_status_mask;
> + u32 tmp = intel_de_read(display,
> + PORT_HOTPLUG_STAT(display)) &
> hotplug_status_mask;
>
> if (tmp == 0)
> return hotplug_status;
>
> hotplug_status |= tmp;
> - intel_uncore_write(&dev_priv->uncore,
> - PORT_HOTPLUG_STAT(dev_priv),
> - hotplug_status);
> + intel_de_write(display, PORT_HOTPLUG_STAT(display),
> + hotplug_status);
> }
>
> drm_WARN_ONCE(&dev_priv->drm, 1,
> "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
> - intel_uncore_read(&dev_priv->uncore,
> PORT_HOTPLUG_STAT(dev_priv)));
> + intel_de_read(display, PORT_HOTPLUG_STAT(display)));
>
> return hotplug_status;
> }
> @@ -492,7 +493,7 @@ void ibx_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 hotplug_trigger)
> * zero. Not acking leads to "The master control interrupt lied (SDE)!"
> * errors.
> */
> - dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore,
> PCH_PORT_HOTPLUG);
> + dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);
> if (!hotplug_trigger) {
> u32 mask = PORTA_HOTPLUG_STATUS_MASK |
> PORTD_HOTPLUG_STATUS_MASK |
> @@ -501,7 +502,7 @@ void ibx_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 hotplug_trigger)
> dig_hotplug_reg &= ~mask;
> }
>
> - intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG,
> dig_hotplug_reg);
> + intel_de_write(display, PCH_PORT_HOTPLUG, dig_hotplug_reg);
> if (!hotplug_trigger)
> return;
>
> @@ -567,7 +568,7 @@ void icp_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
>
> /* Locking due to DSI native GPIO sequences */
> spin_lock(&dev_priv->irq_lock);
> - dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> SHOTPLUG_CTL_DDI, 0, 0);
> + dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0,
> 0);
> spin_unlock(&dev_priv->irq_lock);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, @@ -
> 579,7 +580,7 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> pch_iir)
> if (tc_hotplug_trigger) {
> u32 dig_hotplug_reg;
>
> - dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> SHOTPLUG_CTL_TC, 0, 0);
> + dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0,
> 0);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> tc_hotplug_trigger, dig_hotplug_reg, @@ -
> 605,7 +606,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> pch_iir)
> if (hotplug_trigger) {
> u32 dig_hotplug_reg;
>
> - dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> PCH_PORT_HOTPLUG, 0, 0);
> + dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG,
> 0, 0);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg, @@ -616,7
> +617,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> if (hotplug2_trigger) {
> u32 dig_hotplug_reg;
>
> - dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> PCH_PORT_HOTPLUG2, 0, 0);
> + dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2,
> 0, 0);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug2_trigger, dig_hotplug_reg, @@ -636,7
> +637,7 @@ void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_trigger)
> struct intel_display *display = &dev_priv->display;
> u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
>
> - dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
> + dig_hotplug_reg = intel_de_rmw(display,
> DIGITAL_PORT_HOTPLUG_CNTRL, 0,
> +0);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg, @@ -651,7 +652,7
> @@ void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_trigger)
> struct intel_display *display = &dev_priv->display;
> u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
>
> - dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> PCH_PORT_HOTPLUG, 0, 0);
> + dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg, @@ -671,7 +672,7
> @@ void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> if (trigger_tc) {
> u32 dig_hotplug_reg;
>
> - dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> GEN11_TC_HOTPLUG_CTL, 0, 0);
> + dig_hotplug_reg = intel_de_rmw(display,
> GEN11_TC_HOTPLUG_CTL, 0, 0);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> trigger_tc, dig_hotplug_reg,
> @@ -682,7 +683,7 @@ void gen11_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> if (trigger_tbt) {
> u32 dig_hotplug_reg;
>
> - dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore,
> GEN11_TBT_HOTPLUG_CTL, 0, 0);
> + dig_hotplug_reg = intel_de_rmw(display,
> GEN11_TBT_HOTPLUG_CTL, 0, 0);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> trigger_tbt, dig_hotplug_reg,
> @@ -741,23 +742,25 @@ static u32 ibx_hotplug_enables(struct intel_encoder
> *encoder)
>
> static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) {
> + struct intel_display *display = &dev_priv->display;
> +
> /*
> * Enable digital hotplug on the PCH, and configure the DP short pulse
> * duration to 2ms (which is the minimum in the Display Port spec).
> * The pulse duration bits are reserved on LPT+.
> */
> - intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
> - intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> ibx_hotplug_enables));
> + intel_de_rmw(display, PCH_PORT_HOTPLUG,
> + intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
> + intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
> }
>
> static void ibx_hpd_enable_detection(struct intel_encoder *encoder) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
> - ibx_hotplug_mask(encoder->hpd_pin),
> - ibx_hotplug_enables(encoder));
> + intel_de_rmw(display, PCH_PORT_HOTPLUG,
> + ibx_hotplug_mask(encoder->hpd_pin),
> + ibx_hotplug_enables(encoder));
> }
>
> static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) @@ -812,34
> +815,38 @@ static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
>
> static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv) {
> - intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI,
> - intel_hpd_hotplug_mask(dev_priv,
> icp_ddi_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> icp_ddi_hotplug_enables));
> + struct intel_display *display = &dev_priv->display;
> +
> + intel_de_rmw(display, SHOTPLUG_CTL_DDI,
> + intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
> + intel_hpd_hotplug_enables(dev_priv,
> icp_ddi_hotplug_enables));
> }
>
> static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_DDI,
> - icp_ddi_hotplug_mask(encoder->hpd_pin),
> - icp_ddi_hotplug_enables(encoder));
> + intel_de_rmw(display, SHOTPLUG_CTL_DDI,
> + icp_ddi_hotplug_mask(encoder->hpd_pin),
> + icp_ddi_hotplug_enables(encoder));
> }
>
> static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) {
> - intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC,
> - intel_hpd_hotplug_mask(dev_priv,
> icp_tc_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> icp_tc_hotplug_enables));
> + struct intel_display *display = &dev_priv->display;
> +
> + intel_de_rmw(display, SHOTPLUG_CTL_TC,
> + intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
> + intel_hpd_hotplug_enables(dev_priv,
> icp_tc_hotplug_enables));
> }
>
> static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_TC,
> - icp_tc_hotplug_mask(encoder->hpd_pin),
> - icp_tc_hotplug_enables(encoder));
> + intel_de_rmw(display, SHOTPLUG_CTL_TC,
> + icp_tc_hotplug_mask(encoder->hpd_pin),
> + icp_tc_hotplug_enables(encoder));
> }
>
> static void icp_hpd_enable_detection(struct intel_encoder *encoder) @@ -850,6
> +857,7 @@ static void icp_hpd_enable_detection(struct intel_encoder *encoder)
>
> static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) {
> + struct intel_display *display = &dev_priv->display;
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> @@ -859,7 +867,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private
> *dev_priv)
> * We reduce the value to 250us to be able to detect SHPD when an
> external display
> * is connected. This is also expected of us as stated in DP1.4a Table 3-4.
> */
> - intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT,
> SHPD_FILTER_CNT_250);
> + intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
>
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
> @@ -889,11 +897,12 @@ static u32 gen11_hotplug_enables(struct
> intel_encoder *encoder)
>
> static void dg1_hpd_invert(struct drm_i915_private *i915) {
> + struct intel_display *display = &i915->display;
> u32 val = (INVERT_DDIA_HPD |
> INVERT_DDIB_HPD |
> INVERT_DDIC_HPD |
> INVERT_DDID_HPD);
> - intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val);
> + intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);
> }
>
> static void dg1_hpd_enable_detection(struct intel_encoder *encoder) @@ -
> 912,34 +921,38 @@ static void dg1_hpd_irq_setup(struct drm_i915_private
> *dev_priv)
>
> static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) {
> - intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL,
> - intel_hpd_hotplug_mask(dev_priv,
> gen11_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> gen11_hotplug_enables));
> + struct intel_display *display = &dev_priv->display;
> +
> + intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
> + intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
> + intel_hpd_hotplug_enables(dev_priv,
> gen11_hotplug_enables));
> }
>
> static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_uncore_rmw(&i915->uncore, GEN11_TC_HOTPLUG_CTL,
> - gen11_hotplug_mask(encoder->hpd_pin),
> - gen11_hotplug_enables(encoder));
> + intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
> + gen11_hotplug_mask(encoder->hpd_pin),
> + gen11_hotplug_enables(encoder));
> }
>
> static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> - intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL,
> - intel_hpd_hotplug_mask(dev_priv,
> gen11_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> gen11_hotplug_enables));
> + struct intel_display *display = &dev_priv->display;
> +
> + intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
> + intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
> + intel_hpd_hotplug_enables(dev_priv,
> gen11_hotplug_enables));
> }
>
> static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_uncore_rmw(&i915->uncore, GEN11_TBT_HOTPLUG_CTL,
> - gen11_hotplug_mask(encoder->hpd_pin),
> - gen11_hotplug_enables(encoder));
> + intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
> + gen11_hotplug_mask(encoder->hpd_pin),
> + gen11_hotplug_enables(encoder));
> }
>
> static void gen11_hpd_enable_detection(struct intel_encoder *encoder) @@ -
> 955,14 +968,15 @@ static void gen11_hpd_enable_detection(struct
> intel_encoder *encoder)
>
> static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) {
> + struct intel_display *display = &dev_priv->display;
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.hpd);
> hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv-
> >display.hotplug.hpd);
>
> - intel_uncore_rmw(&dev_priv->uncore, GEN11_DE_HPD_IMR,
> hotplug_irqs,
> - ~enabled_irqs & hotplug_irqs);
> - intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
> + intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs,
> + ~enabled_irqs & hotplug_irqs);
> + intel_de_posting_read(display, GEN11_DE_HPD_IMR);
>
> gen11_tc_hpd_detection_setup(dev_priv);
> gen11_tbt_hpd_detection_setup(dev_priv);
> @@ -1141,6 +1155,7 @@ static void xelpdp_hpd_enable_detection(struct
> intel_encoder *encoder)
>
> static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915) {
> + struct intel_display *display = &i915->display;
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd);
> @@ -1148,7 +1163,7 @@ static void xelpdp_hpd_irq_setup(struct
> drm_i915_private *i915)
>
> intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs,
> ~enabled_irqs & hotplug_irqs);
> - intel_uncore_posting_read(&i915->uncore, PICAINTERRUPT_IMR);
> + intel_de_posting_read(display, PICAINTERRUPT_IMR);
>
> xelpdp_pica_hpd_detection_setup(i915);
>
> @@ -1196,48 +1211,52 @@ static u32 spt_hotplug2_enables(struct
> intel_encoder *encoder)
>
> static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) {
> + struct intel_display *display = &dev_priv->display;
> +
> /* Display WA #1179 WaHardHangonHotPlug: cnp */
> if (HAS_PCH_CNP(dev_priv)) {
> - intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN1,
> CHASSIS_CLK_REQ_DURATION_MASK,
> - CHASSIS_CLK_REQ_DURATION(0xf));
> + intel_de_rmw(display, SOUTH_CHICKEN1,
> CHASSIS_CLK_REQ_DURATION_MASK,
> + CHASSIS_CLK_REQ_DURATION(0xf));
> }
>
> /* Enable digital hotplug on the PCH */
> - intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
> - intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> spt_hotplug_enables));
> + intel_de_rmw(display, PCH_PORT_HOTPLUG,
> + intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
> + intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
>
> - intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2,
> - intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> spt_hotplug2_enables));
> + intel_de_rmw(display, PCH_PORT_HOTPLUG2,
> + intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
> + intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
> }
>
> static void spt_hpd_enable_detection(struct intel_encoder *encoder) {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>
> /* Display WA #1179 WaHardHangonHotPlug: cnp */
> if (HAS_PCH_CNP(i915)) {
> - intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1,
> - CHASSIS_CLK_REQ_DURATION_MASK,
> - CHASSIS_CLK_REQ_DURATION(0xf));
> + intel_de_rmw(display, SOUTH_CHICKEN1,
> + CHASSIS_CLK_REQ_DURATION_MASK,
> + CHASSIS_CLK_REQ_DURATION(0xf));
> }
>
> - intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
> - spt_hotplug_mask(encoder->hpd_pin),
> - spt_hotplug_enables(encoder));
> + intel_de_rmw(display, PCH_PORT_HOTPLUG,
> + spt_hotplug_mask(encoder->hpd_pin),
> + spt_hotplug_enables(encoder));
>
> - intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG2,
> - spt_hotplug2_mask(encoder->hpd_pin),
> - spt_hotplug2_enables(encoder));
> + intel_de_rmw(display, PCH_PORT_HOTPLUG2,
> + spt_hotplug2_mask(encoder->hpd_pin),
> + spt_hotplug2_enables(encoder));
> }
>
> static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) {
> + struct intel_display *display = &dev_priv->display;
> u32 hotplug_irqs, enabled_irqs;
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> - intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT,
> SHPD_FILTER_CNT_500_ADJ);
> + intel_de_write(display, SHPD_FILTER_CNT,
> SHPD_FILTER_CNT_500_ADJ);
>
> enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> @@ -1271,23 +1290,25 @@ static u32 ilk_hotplug_enables(struct intel_encoder
> *encoder)
>
> static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) {
> + struct intel_display *display = &dev_priv->display;
> +
> /*
> * Enable digital hotplug on the CPU, and configure the DP short pulse
> * duration to 2ms (which is the minimum in the Display Port spec)
> * The pulse duration bits are reserved on HSW+.
> */
> - intel_uncore_rmw(&dev_priv->uncore,
> DIGITAL_PORT_HOTPLUG_CNTRL,
> - intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> ilk_hotplug_enables));
> + intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
> + intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
> + intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
> }
>
> static void ilk_hpd_enable_detection(struct intel_encoder *encoder) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_uncore_rmw(&i915->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
> - ilk_hotplug_mask(encoder->hpd_pin),
> - ilk_hotplug_enables(encoder));
> + intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
> + ilk_hotplug_mask(encoder->hpd_pin),
> + ilk_hotplug_enables(encoder));
>
> ibx_hpd_enable_detection(encoder);
> }
> @@ -1350,18 +1371,20 @@ static u32 bxt_hotplug_enables(struct intel_encoder
> *encoder)
>
> static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) {
> - intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
> - intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> bxt_hotplug_enables));
> + struct intel_display *display = &dev_priv->display;
> +
> + intel_de_rmw(display, PCH_PORT_HOTPLUG,
> + intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
> + intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
> }
>
> static void bxt_hpd_enable_detection(struct intel_encoder *encoder) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
> - bxt_hotplug_mask(encoder->hpd_pin),
> - bxt_hotplug_enables(encoder));
> + intel_de_rmw(display, PCH_PORT_HOTPLUG,
> + bxt_hotplug_mask(encoder->hpd_pin),
> + bxt_hotplug_enables(encoder));
> }
>
> static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 6/9] drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct intel_display
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (4 preceding siblings ...)
2025-03-11 18:00 ` [PATCH 5/9] drm/i915/hotplug: convert hotplug irq handling to intel_de_*() Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-12 5:33 ` Shankar, Uma
2025-03-11 18:00 ` [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces " Jani Nikula
` (12 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_hotplug_irq.[ch] to struct
intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 4 +-
.../gpu/drm/i915/display/intel_display_irq.c | 33 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +-
.../gpu/drm/i915/display/intel_hotplug_irq.c | 474 +++++++++---------
.../gpu/drm/i915/display/intel_hotplug_irq.h | 28 +-
drivers/gpu/drm/i915/i915_irq.c | 18 +-
6 files changed, 276 insertions(+), 287 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index bca91d49cb96..a7f360f89410 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -606,7 +606,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
for (i = 0; i < tries ; i++) {
/* turn on the FORCE_DETECT */
- i915_hotplug_interrupt_update(dev_priv,
+ i915_hotplug_interrupt_update(display,
CRT_HOTPLUG_FORCE_DETECT,
CRT_HOTPLUG_FORCE_DETECT);
/* wait for FORCE_DETECT to go off */
@@ -624,7 +624,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
intel_de_write(display, PORT_HOTPLUG_STAT(display),
CRT_HOTPLUG_INT_STATUS);
- i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
+ i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT, 0);
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index aa23bb817805..b37bcb8fb2e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -675,7 +675,7 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
enum pipe pipe;
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
- ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
+ ibx_hpd_irq_handler(display, hotplug_trigger);
if (pch_iir & SDE_AUDIO_POWER_MASK) {
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
@@ -812,7 +812,7 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
enum pipe pipe;
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
- ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
+ ibx_hpd_irq_handler(display, hotplug_trigger);
if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
@@ -901,7 +901,7 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
if (hotplug_trigger)
- ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
+ ilk_hpd_irq_handler(display, hotplug_trigger);
if (de_iir & DE_AUX_CHANNEL_A)
intel_dp_aux_irq_handler(display);
@@ -953,7 +953,7 @@ void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
if (hotplug_trigger)
- ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
+ ilk_hpd_irq_handler(display, hotplug_trigger);
if (de_iir & DE_ERR_INT_IVB)
ivb_err_int_handler(dev_priv);
@@ -1382,7 +1382,7 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
iir = intel_de_read(display, GEN11_DE_HPD_IIR);
if (iir) {
intel_de_write(display, GEN11_DE_HPD_IIR, iir);
- gen11_hpd_irq_handler(dev_priv, iir);
+ gen11_hpd_irq_handler(display, iir);
} else {
drm_err_ratelimited(&dev_priv->drm,
"The master control interrupt lied, (DE HPD)!\n");
@@ -1405,14 +1405,14 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
if (hotplug_trigger) {
- bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
+ bxt_hpd_irq_handler(display, hotplug_trigger);
found = true;
}
} else if (IS_BROADWELL(dev_priv)) {
u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
if (hotplug_trigger) {
- ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
+ ilk_hpd_irq_handler(display, hotplug_trigger);
found = true;
}
}
@@ -1498,12 +1498,12 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir);
if (iir) {
if (pica_iir)
- xelpdp_pica_irq_handler(dev_priv, pica_iir);
+ xelpdp_pica_irq_handler(display, pica_iir);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- icp_irq_handler(dev_priv, iir);
+ icp_irq_handler(display, iir);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- spt_irq_handler(dev_priv, iir);
+ spt_irq_handler(display, iir);
else
cpt_irq_handler(dev_priv, iir);
} else {
@@ -1904,7 +1904,7 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)
gen2_error_reset(to_intel_uncore(display->drm),
VLV_ERROR_REGS);
- i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
+ i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0);
intel_de_rmw(display, PORT_HOTPLUG_STAT(dev_priv), 0, 0);
i9xx_pipestat_irq_reset(dev_priv);
@@ -1924,7 +1924,7 @@ void i9xx_display_irq_reset(struct drm_i915_private *i915)
struct intel_display *display = &i915->display;
if (I915_HAS_HOTPLUG(i915)) {
- i915_hotplug_interrupt_update(i915, 0xffffffff, 0);
+ i915_hotplug_interrupt_update(display, 0xffffffff, 0);
intel_de_rmw(display, PORT_HOTPLUG_STAT(i915), 0, 0);
}
@@ -2348,10 +2348,11 @@ void dg1_de_irq_postinstall(struct drm_i915_private *i915)
void intel_display_irq_init(struct drm_i915_private *i915)
{
- i915->drm.vblank_disable_immediate = true;
+ struct intel_display *display = &i915->display;
+
+ display->drm->vblank_disable_immediate = true;
- intel_hotplug_irq_init(i915);
+ intel_hotplug_irq_init(display);
- INIT_WORK(&i915->display.irq.vblank_dc_work,
- intel_display_vblank_dc_work);
+ INIT_WORK(&display->irq.vblank_dc_work, intel_display_vblank_dc_work);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 7683b3ce124d..fcc3f546cb97 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -305,7 +305,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
display->hotplug.stats[pin].state = HPD_ENABLED;
}
- intel_hpd_irq_setup(dev_priv);
+ intel_hpd_irq_setup(display);
spin_unlock_irq(&dev_priv->irq_lock);
@@ -696,7 +696,7 @@ void intel_hpd_irq_handler(struct intel_display *display,
* happens later in our hotplug work.
*/
if (storm_detected)
- intel_hpd_irq_setup(dev_priv);
+ intel_hpd_irq_setup(display);
/*
* Our hotplug handler can grab modeset locks (by calling down into the
@@ -745,7 +745,7 @@ void intel_hpd_init(struct intel_display *display)
* just to make the assert_spin_locked checks happy.
*/
spin_lock_irq(&dev_priv->irq_lock);
- intel_hpd_irq_setup(dev_priv);
+ intel_hpd_irq_setup(display);
spin_unlock_irq(&dev_priv->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index f24c65478742..e44ae6acc55f 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -131,30 +131,31 @@ static const u32 hpd_mtp[HPD_NUM_PINS] = {
[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
};
-static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
+static void intel_hpd_init_pins(struct intel_display *display)
{
- struct intel_hotplug *hpd = &dev_priv->display.hotplug;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+ struct intel_hotplug *hpd = &display->hotplug;
- if (HAS_GMCH(dev_priv)) {
- if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
- IS_CHERRYVIEW(dev_priv))
+ if (HAS_GMCH(display)) {
+ if (display->platform.g4x || display->platform.valleyview ||
+ display->platform.cherryview)
hpd->hpd = hpd_status_g4x;
else
hpd->hpd = hpd_status_i915;
return;
}
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(display) >= 14)
hpd->hpd = hpd_xelpdp;
- else if (DISPLAY_VER(dev_priv) >= 11)
+ else if (DISPLAY_VER(display) >= 11)
hpd->hpd = hpd_gen11;
- else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+ else if (display->platform.geminilake || display->platform.broxton)
hpd->hpd = hpd_bxt;
- else if (DISPLAY_VER(dev_priv) == 9)
+ else if (DISPLAY_VER(display) == 9)
hpd->hpd = NULL; /* no north HPD on SKL */
- else if (DISPLAY_VER(dev_priv) >= 8)
+ else if (DISPLAY_VER(display) >= 8)
hpd->hpd = hpd_bdw;
- else if (DISPLAY_VER(dev_priv) >= 7)
+ else if (DISPLAY_VER(display) >= 7)
hpd->hpd = hpd_ivb;
else
hpd->hpd = hpd_ilk;
@@ -180,20 +181,20 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
}
/* For display hotplug interrupt */
-void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
+void i915_hotplug_interrupt_update_locked(struct intel_display *display,
u32 mask, u32 bits)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
lockdep_assert_held(&dev_priv->irq_lock);
- drm_WARN_ON(&dev_priv->drm, bits & ~mask);
+ drm_WARN_ON(display->drm, bits & ~mask);
intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);
}
/**
* i915_hotplug_interrupt_update - update hotplug interrupt enable
- * @dev_priv: driver private
+ * @display: display device
* @mask: bits to update
* @bits: bits to enable
* NOTE: the HPD enable bits are modified both inside and outside
@@ -203,12 +204,14 @@ void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
* held already, this function acquires the lock itself. A non-locking
* version is also available.
*/
-void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
+void i915_hotplug_interrupt_update(struct intel_display *display,
u32 mask,
u32 bits)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
spin_lock_irq(&dev_priv->irq_lock);
- i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
+ i915_hotplug_interrupt_update_locked(display, mask, bits);
spin_unlock_irq(&dev_priv->irq_lock);
}
@@ -340,7 +343,7 @@ static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
*
* Note that the caller is expected to zero out the masks initially.
*/
-static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
+static void intel_get_hpd_pins(struct intel_display *display,
u32 *pin_mask, u32 *long_mask,
u32 hotplug_trigger, u32 dig_hotplug_reg,
const u32 hpd[HPD_NUM_PINS],
@@ -360,37 +363,37 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
*long_mask |= BIT(pin);
}
- drm_dbg(&dev_priv->drm,
- "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
- hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
+ drm_dbg_kms(display->drm,
+ "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
+ hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
}
-static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
+static u32 intel_hpd_enabled_irqs(struct intel_display *display,
const u32 hpd[HPD_NUM_PINS])
{
struct intel_encoder *encoder;
u32 enabled_irqs = 0;
- for_each_intel_encoder(&dev_priv->drm, encoder)
- if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
+ for_each_intel_encoder(display->drm, encoder)
+ if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
enabled_irqs |= hpd[encoder->hpd_pin];
return enabled_irqs;
}
-static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
+static u32 intel_hpd_hotplug_irqs(struct intel_display *display,
const u32 hpd[HPD_NUM_PINS])
{
struct intel_encoder *encoder;
u32 hotplug_irqs = 0;
- for_each_intel_encoder(&dev_priv->drm, encoder)
+ for_each_intel_encoder(display->drm, encoder)
hotplug_irqs |= hpd[encoder->hpd_pin];
return hotplug_irqs;
}
-static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915,
+static u32 intel_hpd_hotplug_mask(struct intel_display *display,
hotplug_mask_func hotplug_mask)
{
enum hpd_pin pin;
@@ -402,26 +405,25 @@ static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915,
return hotplug;
}
-static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
+static u32 intel_hpd_hotplug_enables(struct intel_display *display,
hotplug_enables_func hotplug_enables)
{
struct intel_encoder *encoder;
u32 hotplug = 0;
- for_each_intel_encoder(&i915->drm, encoder)
+ for_each_intel_encoder(display->drm, encoder)
hotplug |= hotplug_enables(encoder);
return hotplug;
}
-u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
+u32 i9xx_hpd_irq_ack(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
u32 hotplug_status = 0, hotplug_status_mask;
int i;
- if (IS_G4X(dev_priv) ||
- IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ if (display->platform.g4x ||
+ display->platform.valleyview || display->platform.cherryview)
hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
else
@@ -448,43 +450,41 @@ u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
hotplug_status);
}
- drm_WARN_ONCE(&dev_priv->drm, 1,
+ drm_WARN_ONCE(display->drm, 1,
"PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
intel_de_read(display, PORT_HOTPLUG_STAT(display)));
return hotplug_status;
}
-void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status)
+void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status)
{
- struct intel_display *display = &dev_priv->display;
u32 pin_mask = 0, long_mask = 0;
u32 hotplug_trigger;
- if (IS_G4X(dev_priv) ||
- IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ if (display->platform.g4x ||
+ display->platform.valleyview || display->platform.cherryview)
hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
else
hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
if (hotplug_trigger) {
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
hotplug_trigger, hotplug_trigger,
- dev_priv->display.hotplug.hpd,
+ display->hotplug.hpd,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(display, pin_mask, long_mask);
}
- if ((IS_G4X(dev_priv) ||
- IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+ if ((display->platform.g4x ||
+ display->platform.valleyview || display->platform.cherryview) &&
hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
intel_dp_aux_irq_handler(display);
}
-void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
+void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
{
- struct intel_display *display = &dev_priv->display;
u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
/*
@@ -506,44 +506,43 @@ void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
if (!hotplug_trigger)
return;
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->display.hotplug.pch_hpd,
+ display->hotplug.pch_hpd,
pch_port_hotplug_long_detect);
intel_hpd_irq_handler(display, pin_mask, long_mask);
}
-void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
+void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir)
{
- struct intel_display *display = &i915->display;
enum hpd_pin pin;
u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK);
u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
u32 pin_mask = 0, long_mask = 0;
- if (DISPLAY_VER(i915) >= 20)
+ if (DISPLAY_VER(display) >= 20)
trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
u32 val;
- if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger))
+ if (!(display->hotplug.hpd[pin] & hotplug_trigger))
continue;
pin_mask |= BIT(pin);
- val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin));
- intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val);
+ val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));
+ intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val);
if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT))
long_mask |= BIT(pin);
}
if (pin_mask) {
- drm_dbg(&i915->drm,
- "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
- hotplug_trigger, pin_mask, long_mask);
+ drm_dbg_kms(display->drm,
+ "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
+ hotplug_trigger, pin_mask, long_mask);
intel_hpd_irq_handler(display, pin_mask, long_mask);
}
@@ -552,13 +551,13 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
intel_dp_aux_irq_handler(display);
if (!pin_mask && !trigger_aux)
- drm_err(&i915->drm,
+ drm_err(display->drm,
"Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
}
-void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+void icp_irq_handler(struct intel_display *display, u32 pch_iir)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
u32 pin_mask = 0, long_mask = 0;
@@ -571,9 +570,9 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0);
spin_unlock(&dev_priv->irq_lock);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
ddi_hotplug_trigger, dig_hotplug_reg,
- dev_priv->display.hotplug.pch_hpd,
+ display->hotplug.pch_hpd,
icp_ddi_port_hotplug_long_detect);
}
@@ -582,9 +581,9 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
tc_hotplug_trigger, dig_hotplug_reg,
- dev_priv->display.hotplug.pch_hpd,
+ display->hotplug.pch_hpd,
icp_tc_port_hotplug_long_detect);
}
@@ -595,9 +594,8 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_gmbus_irq_handler(display);
}
-void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+void spt_irq_handler(struct intel_display *display, u32 pch_iir)
{
- struct intel_display *display = &dev_priv->display;
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
~SDE_PORTE_HOTPLUG_SPT;
u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
@@ -608,9 +606,9 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->display.hotplug.pch_hpd,
+ display->hotplug.pch_hpd,
spt_port_hotplug_long_detect);
}
@@ -619,9 +617,9 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
hotplug2_trigger, dig_hotplug_reg,
- dev_priv->display.hotplug.pch_hpd,
+ display->hotplug.pch_hpd,
spt_port_hotplug2_long_detect);
}
@@ -632,39 +630,36 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_gmbus_irq_handler(display);
}
-void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
+void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
{
- struct intel_display *display = &dev_priv->display;
u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->display.hotplug.hpd,
+ display->hotplug.hpd,
ilk_port_hotplug_long_detect);
intel_hpd_irq_handler(display, pin_mask, long_mask);
}
-void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
+void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
{
- struct intel_display *display = &dev_priv->display;
u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->display.hotplug.hpd,
+ display->hotplug.hpd,
bxt_port_hotplug_long_detect);
intel_hpd_irq_handler(display, pin_mask, long_mask);
}
-void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
+void gen11_hpd_irq_handler(struct intel_display *display, u32 iir)
{
- struct intel_display *display = &dev_priv->display;
u32 pin_mask = 0, long_mask = 0;
u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
@@ -674,9 +669,9 @@ void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
trigger_tc, dig_hotplug_reg,
- dev_priv->display.hotplug.hpd,
+ display->hotplug.hpd,
gen11_port_hotplug_long_detect);
}
@@ -685,16 +680,16 @@ void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ intel_get_hpd_pins(display, &pin_mask, &long_mask,
trigger_tbt, dig_hotplug_reg,
- dev_priv->display.hotplug.hpd,
+ display->hotplug.hpd,
gen11_port_hotplug_long_detect);
}
if (pin_mask)
intel_hpd_irq_handler(display, pin_mask, long_mask);
else
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Unexpected DE HPD interrupt 0x%08x\n", iir);
}
@@ -740,18 +735,16 @@ static u32 ibx_hotplug_enables(struct intel_encoder *encoder)
}
}
-static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void ibx_hpd_detection_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
/*
* Enable digital hotplug on the PCH, and configure the DP short pulse
* duration to 2ms (which is the minimum in the Display Port spec).
* The pulse duration bits are reserved on LPT+.
*/
intel_de_rmw(display, PCH_PORT_HOTPLUG,
- intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
+ intel_hpd_hotplug_mask(display, ibx_hotplug_mask),
+ intel_hpd_hotplug_enables(display, ibx_hotplug_enables));
}
static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
@@ -763,16 +756,17 @@ static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
ibx_hotplug_enables(encoder));
}
-static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void ibx_hpd_irq_setup(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
- ibx_hpd_detection_setup(dev_priv);
+ ibx_hpd_detection_setup(display);
}
static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
@@ -813,13 +807,11 @@ static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
return icp_tc_hotplug_mask(encoder->hpd_pin);
}
-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void icp_ddi_hpd_detection_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
intel_de_rmw(display, SHOTPLUG_CTL_DDI,
- intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables));
+ intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask),
+ intel_hpd_hotplug_enables(display, icp_ddi_hotplug_enables));
}
static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
@@ -831,13 +823,11 @@ static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
icp_ddi_hotplug_enables(encoder));
}
-static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void icp_tc_hpd_detection_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
intel_de_rmw(display, SHOTPLUG_CTL_TC,
- intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables));
+ intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask),
+ intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables));
}
static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
@@ -855,13 +845,13 @@ static void icp_hpd_enable_detection(struct intel_encoder *encoder)
icp_tc_hpd_enable_detection(encoder);
}
-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void icp_hpd_irq_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
/*
* We reduce the value to 250us to be able to detect SHPD when an external display
@@ -871,8 +861,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
- icp_ddi_hpd_detection_setup(dev_priv);
- icp_tc_hpd_detection_setup(dev_priv);
+ icp_ddi_hpd_detection_setup(display);
+ icp_tc_hpd_detection_setup(display);
}
static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)
@@ -895,9 +885,8 @@ static u32 gen11_hotplug_enables(struct intel_encoder *encoder)
return gen11_hotplug_mask(encoder->hpd_pin);
}
-static void dg1_hpd_invert(struct drm_i915_private *i915)
+static void dg1_hpd_invert(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
u32 val = (INVERT_DDIA_HPD |
INVERT_DDIB_HPD |
INVERT_DDIC_HPD |
@@ -907,25 +896,23 @@ static void dg1_hpd_invert(struct drm_i915_private *i915)
static void dg1_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- dg1_hpd_invert(i915);
+ dg1_hpd_invert(display);
icp_hpd_enable_detection(encoder);
}
-static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void dg1_hpd_irq_setup(struct intel_display *display)
{
- dg1_hpd_invert(dev_priv);
- icp_hpd_irq_setup(dev_priv);
+ dg1_hpd_invert(display);
+ icp_hpd_irq_setup(display);
}
-static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void gen11_tc_hpd_detection_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
- intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
+ intel_hpd_hotplug_mask(display, gen11_hotplug_mask),
+ intel_hpd_hotplug_enables(display, gen11_hotplug_enables));
}
static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
@@ -937,13 +924,11 @@ static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
gen11_hotplug_enables(encoder));
}
-static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void gen11_tbt_hpd_detection_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
- intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
+ intel_hpd_hotplug_mask(display, gen11_hotplug_mask),
+ intel_hpd_hotplug_enables(display, gen11_hotplug_enables));
}
static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder)
@@ -966,23 +951,23 @@ static void gen11_hpd_enable_detection(struct intel_encoder *encoder)
icp_hpd_enable_detection(encoder);
}
-static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void gen11_hpd_irq_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs,
~enabled_irqs & hotplug_irqs);
intel_de_posting_read(display, GEN11_DE_HPD_IMR);
- gen11_tc_hpd_detection_setup(dev_priv);
- gen11_tbt_hpd_detection_setup(dev_priv);
+ gen11_tc_hpd_detection_setup(display);
+ gen11_tbt_hpd_detection_setup(display);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- icp_hpd_irq_setup(dev_priv);
+ icp_hpd_irq_setup(display);
}
static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
@@ -1019,39 +1004,39 @@ static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder)
return mtp_tc_hotplug_mask(encoder->hpd_pin);
}
-static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *i915)
+static void mtp_ddi_hpd_detection_setup(struct intel_display *display)
{
- intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
- intel_hpd_hotplug_mask(i915, mtp_ddi_hotplug_mask),
- intel_hpd_hotplug_enables(i915, mtp_ddi_hotplug_enables));
+ intel_de_rmw(display, SHOTPLUG_CTL_DDI,
+ intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask),
+ intel_hpd_hotplug_enables(display, mtp_ddi_hotplug_enables));
}
static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
+ intel_de_rmw(display, SHOTPLUG_CTL_DDI,
mtp_ddi_hotplug_mask(encoder->hpd_pin),
mtp_ddi_hotplug_enables(encoder));
}
-static void mtp_tc_hpd_detection_setup(struct drm_i915_private *i915)
+static void mtp_tc_hpd_detection_setup(struct intel_display *display)
{
- intel_de_rmw(i915, SHOTPLUG_CTL_TC,
- intel_hpd_hotplug_mask(i915, mtp_tc_hotplug_mask),
- intel_hpd_hotplug_enables(i915, mtp_tc_hotplug_enables));
+ intel_de_rmw(display, SHOTPLUG_CTL_TC,
+ intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask),
+ intel_hpd_hotplug_enables(display, mtp_tc_hotplug_enables));
}
static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
+ intel_de_rmw(display, SHOTPLUG_CTL_DDI,
mtp_tc_hotplug_mask(encoder->hpd_pin),
mtp_tc_hotplug_enables(encoder));
}
-static void mtp_hpd_invert(struct drm_i915_private *i915)
+static void mtp_hpd_invert(struct intel_display *display)
{
u32 val = (INVERT_DDIA_HPD |
INVERT_DDIB_HPD |
@@ -1062,49 +1047,51 @@ static void mtp_hpd_invert(struct drm_i915_private *i915)
INVERT_TC4_HPD |
INVERT_DDID_HPD_MTP |
INVERT_DDIE_HPD);
- intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val);
+ intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);
}
static void mtp_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- mtp_hpd_invert(i915);
+ mtp_hpd_invert(display);
mtp_ddi_hpd_enable_detection(encoder);
mtp_tc_hpd_enable_detection(encoder);
}
-static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
+static void mtp_hpd_irq_setup(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
/*
* Use 250us here to align with the DP1.4a(Table 3-4) spec as to what the
* SHPD_FILTER_CNT value should be.
*/
- intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
+ intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
- mtp_hpd_invert(i915);
+ mtp_hpd_invert(display);
ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
- mtp_ddi_hpd_detection_setup(i915);
- mtp_tc_hpd_detection_setup(i915);
+ mtp_ddi_hpd_detection_setup(display);
+ mtp_tc_hpd_detection_setup(display);
}
-static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
+static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
- mtp_ddi_hpd_detection_setup(i915);
- mtp_tc_hpd_detection_setup(i915);
+ mtp_ddi_hpd_detection_setup(display);
+ mtp_tc_hpd_detection_setup(display);
}
static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
@@ -1112,7 +1099,7 @@ static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
}
-static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915,
+static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display,
enum hpd_pin hpd_pin, bool enable)
{
u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |
@@ -1121,18 +1108,18 @@ static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915,
if (!is_xelpdp_pica_hpd_pin(hpd_pin))
return;
- intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
+ intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
mask, enable ? mask : 0);
}
static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- _xelpdp_pica_hpd_detection_setup(i915, encoder->hpd_pin, true);
+ _xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true);
}
-static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915)
+static void xelpdp_pica_hpd_detection_setup(struct intel_display *display)
{
struct intel_encoder *encoder;
u32 available_pins = 0;
@@ -1140,11 +1127,11 @@ static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915)
BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS);
- for_each_intel_encoder(&i915->drm, encoder)
+ for_each_intel_encoder(display->drm, encoder)
available_pins |= BIT(encoder->hpd_pin);
for_each_hpd_pin(pin)
- _xelpdp_pica_hpd_detection_setup(i915, pin, available_pins & BIT(pin));
+ _xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin));
}
static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
@@ -1153,24 +1140,24 @@ static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
mtp_hpd_enable_detection(encoder);
}
-static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
+static void xelpdp_hpd_irq_setup(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
- intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs,
+ intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs,
~enabled_irqs & hotplug_irqs);
intel_de_posting_read(display, PICAINTERRUPT_IMR);
- xelpdp_pica_hpd_detection_setup(i915);
+ xelpdp_pica_hpd_detection_setup(display);
if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
- xe2lpd_sde_hpd_irq_setup(i915);
+ xe2lpd_sde_hpd_irq_setup(display);
else if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
- mtp_hpd_irq_setup(i915);
+ mtp_hpd_irq_setup(display);
}
static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)
@@ -1209,9 +1196,9 @@ static u32 spt_hotplug2_enables(struct intel_encoder *encoder)
return spt_hotplug2_mask(encoder->hpd_pin);
}
-static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void spt_hpd_detection_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
/* Display WA #1179 WaHardHangonHotPlug: cnp */
if (HAS_PCH_CNP(dev_priv)) {
@@ -1221,12 +1208,12 @@ static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
/* Enable digital hotplug on the PCH */
intel_de_rmw(display, PCH_PORT_HOTPLUG,
- intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
+ intel_hpd_hotplug_mask(display, spt_hotplug_mask),
+ intel_hpd_hotplug_enables(display, spt_hotplug_enables));
intel_de_rmw(display, PCH_PORT_HOTPLUG2,
- intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
- intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
+ intel_hpd_hotplug_mask(display, spt_hotplug2_mask),
+ intel_hpd_hotplug_enables(display, spt_hotplug2_enables));
}
static void spt_hpd_enable_detection(struct intel_encoder *encoder)
@@ -1250,20 +1237,20 @@ static void spt_hpd_enable_detection(struct intel_encoder *encoder)
spt_hotplug2_enables(encoder));
}
-static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void spt_hpd_irq_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
- spt_hpd_detection_setup(dev_priv);
+ spt_hpd_detection_setup(display);
}
static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)
@@ -1288,18 +1275,16 @@ static u32 ilk_hotplug_enables(struct intel_encoder *encoder)
}
}
-static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void ilk_hpd_detection_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
/*
* Enable digital hotplug on the CPU, and configure the DP short pulse
* duration to 2ms (which is the minimum in the Display Port spec)
* The pulse duration bits are reserved on HSW+.
*/
intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
- intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
+ intel_hpd_hotplug_mask(display, ilk_hotplug_mask),
+ intel_hpd_hotplug_enables(display, ilk_hotplug_enables));
}
static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
@@ -1313,21 +1298,22 @@ static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
ibx_hpd_enable_detection(encoder);
}
-static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void ilk_hpd_irq_setup(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
- if (DISPLAY_VER(dev_priv) >= 8)
+ if (DISPLAY_VER(display) >= 8)
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
else
ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
- ilk_hpd_detection_setup(dev_priv);
+ ilk_hpd_detection_setup(display);
- ibx_hpd_irq_setup(dev_priv);
+ ibx_hpd_irq_setup(display);
}
static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)
@@ -1369,13 +1355,11 @@ static u32 bxt_hotplug_enables(struct intel_encoder *encoder)
}
}
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void bxt_hpd_detection_setup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
intel_de_rmw(display, PCH_PORT_HOTPLUG,
- intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
- intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
+ intel_hpd_hotplug_mask(display, bxt_hotplug_mask),
+ intel_hpd_hotplug_enables(display, bxt_hotplug_enables));
}
static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
@@ -1387,42 +1371,44 @@ static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
bxt_hotplug_enables(encoder));
}
-static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void bxt_hpd_irq_setup(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
- bxt_hpd_detection_setup(dev_priv);
+ bxt_hpd_detection_setup(display);
}
-static void g45_hpd_peg_band_gap_wa(struct drm_i915_private *i915)
+static void g45_hpd_peg_band_gap_wa(struct intel_display *display)
{
/*
* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
* 0xd. Failure to do so will result in spurious interrupts being
* generated on the port when a cable is not attached.
*/
- intel_de_rmw(i915, PEG_BAND_GAP_DATA, 0xf, 0xd);
+ intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd);
}
static void i915_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];
- if (IS_G45(i915))
- g45_hpd_peg_band_gap_wa(i915);
+ if (display->platform.g45)
+ g45_hpd_peg_band_gap_wa(display);
/* HPD sense and interrupt enable are one and the same */
- i915_hotplug_interrupt_update(i915, hotplug_en, hotplug_en);
+ i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en);
}
-static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void i915_hpd_irq_setup(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_en;
lockdep_assert_held(&dev_priv->irq_lock);
@@ -1431,20 +1417,20 @@ static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
* Note HDMI and DP share hotplug bits. Enable bits are the same for all
* generations.
*/
- hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
+ hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915);
/*
* Programming the CRT detection parameters tends to generate a spurious
* hotplug event about three seconds later. So just do it once.
*/
- if (IS_G4X(dev_priv))
+ if (display->platform.g4x)
hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
- if (IS_G45(dev_priv))
- g45_hpd_peg_band_gap_wa(dev_priv);
+ if (display->platform.g45)
+ g45_hpd_peg_band_gap_wa(display);
/* Ignore TV since it's buggy */
- i915_hotplug_interrupt_update_locked(dev_priv,
+ i915_hotplug_interrupt_update_locked(display,
HOTPLUG_INT_EN_MASK |
CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
CRT_HOTPLUG_ACTIVATION_PERIOD_64,
@@ -1453,7 +1439,7 @@ static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
struct intel_hotplug_funcs {
/* Enable HPD sense and interrupts for all present encoders */
- void (*hpd_irq_setup)(struct drm_i915_private *i915);
+ void (*hpd_irq_setup)(struct intel_display *display);
/* Enable HPD sense for a single encoder */
void (*hpd_enable_detection)(struct intel_encoder *encoder);
};
@@ -1476,49 +1462,49 @@ HPD_FUNCS(ilk);
void intel_hpd_enable_detection(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- if (i915->display.funcs.hotplug)
- i915->display.funcs.hotplug->hpd_enable_detection(encoder);
+ if (display->funcs.hotplug)
+ display->funcs.hotplug->hpd_enable_detection(encoder);
}
-void intel_hpd_irq_setup(struct drm_i915_private *i915)
+void intel_hpd_irq_setup(struct intel_display *display)
{
- if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) &&
- !i915->display.irq.vlv_display_irqs_enabled)
+ if ((display->platform.valleyview || display->platform.cherryview) &&
+ !display->irq.vlv_display_irqs_enabled)
return;
- if (i915->display.funcs.hotplug)
- i915->display.funcs.hotplug->hpd_irq_setup(i915);
+ if (display->funcs.hotplug)
+ display->funcs.hotplug->hpd_irq_setup(display);
}
-void intel_hotplug_irq_init(struct drm_i915_private *i915)
+void intel_hotplug_irq_init(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
- intel_hpd_init_pins(i915);
+ intel_hpd_init_pins(display);
intel_hpd_init_early(display);
- if (HAS_GMCH(i915)) {
- if (I915_HAS_HOTPLUG(i915))
- i915->display.funcs.hotplug = &i915_hpd_funcs;
+ if (HAS_GMCH(display)) {
+ if (I915_HAS_HOTPLUG(display))
+ display->funcs.hotplug = &i915_hpd_funcs;
} else {
if (HAS_PCH_DG2(i915))
- i915->display.funcs.hotplug = &icp_hpd_funcs;
+ display->funcs.hotplug = &icp_hpd_funcs;
else if (HAS_PCH_DG1(i915))
- i915->display.funcs.hotplug = &dg1_hpd_funcs;
- else if (DISPLAY_VER(i915) >= 14)
- i915->display.funcs.hotplug = &xelpdp_hpd_funcs;
- else if (DISPLAY_VER(i915) >= 11)
- i915->display.funcs.hotplug = &gen11_hpd_funcs;
- else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- i915->display.funcs.hotplug = &bxt_hpd_funcs;
+ display->funcs.hotplug = &dg1_hpd_funcs;
+ else if (DISPLAY_VER(display) >= 14)
+ display->funcs.hotplug = &xelpdp_hpd_funcs;
+ else if (DISPLAY_VER(display) >= 11)
+ display->funcs.hotplug = &gen11_hpd_funcs;
+ else if (display->platform.geminilake || display->platform.broxton)
+ display->funcs.hotplug = &bxt_hpd_funcs;
else if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
- i915->display.funcs.hotplug = &icp_hpd_funcs;
+ display->funcs.hotplug = &icp_hpd_funcs;
else if (INTEL_PCH_TYPE(i915) >= PCH_SPT)
- i915->display.funcs.hotplug = &spt_hpd_funcs;
+ display->funcs.hotplug = &spt_hpd_funcs;
else
- i915->display.funcs.hotplug = &ilk_hpd_funcs;
+ display->funcs.hotplug = &ilk_hpd_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.h b/drivers/gpu/drm/i915/display/intel_hotplug_irq.h
index e4db752df096..9063bb02a2e9 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.h
@@ -8,28 +8,28 @@
#include <linux/types.h>
-struct drm_i915_private;
+struct intel_display;
struct intel_encoder;
-u32 i9xx_hpd_irq_ack(struct drm_i915_private *i915);
+u32 i9xx_hpd_irq_ack(struct intel_display *display);
-void i9xx_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_status);
-void ibx_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger);
-void ilk_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger);
-void gen11_hpd_irq_handler(struct drm_i915_private *i915, u32 iir);
-void bxt_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger);
-void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir);
-void icp_irq_handler(struct drm_i915_private *i915, u32 pch_iir);
-void spt_irq_handler(struct drm_i915_private *i915, u32 pch_iir);
+void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status);
+void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
+void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
+void gen11_hpd_irq_handler(struct intel_display *display, u32 iir);
+void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
+void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir);
+void icp_irq_handler(struct intel_display *display, u32 pch_iir);
+void spt_irq_handler(struct intel_display *display, u32 pch_iir);
-void i915_hotplug_interrupt_update_locked(struct drm_i915_private *i915,
+void i915_hotplug_interrupt_update_locked(struct intel_display *display,
u32 mask, u32 bits);
-void i915_hotplug_interrupt_update(struct drm_i915_private *i915,
+void i915_hotplug_interrupt_update(struct intel_display *display,
u32 mask, u32 bits);
void intel_hpd_enable_detection(struct intel_encoder *encoder);
-void intel_hpd_irq_setup(struct drm_i915_private *i915);
+void intel_hpd_irq_setup(struct intel_display *display);
-void intel_hotplug_irq_init(struct drm_i915_private *i915);
+void intel_hotplug_irq_init(struct intel_display *display);
#endif /* __INTEL_HOTPLUG_IRQ_H__ */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index de53615571be..3b05eb3f9cbc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -277,7 +277,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
if (iir & I915_DISPLAY_PORT_INTERRUPT)
- hotplug_status = i9xx_hpd_irq_ack(dev_priv);
+ hotplug_status = i9xx_hpd_irq_ack(display);
if (iir & I915_MASTER_ERROR_INTERRUPT)
vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
@@ -306,7 +306,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
if (hotplug_status)
- i9xx_hpd_irq_handler(dev_priv, hotplug_status);
+ i9xx_hpd_irq_handler(display, hotplug_status);
if (iir & I915_MASTER_ERROR_INTERRUPT)
vlv_display_error_irq_handler(display, eir, dpinvgtt);
@@ -367,7 +367,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
if (iir & I915_DISPLAY_PORT_INTERRUPT)
- hotplug_status = i9xx_hpd_irq_ack(dev_priv);
+ hotplug_status = i9xx_hpd_irq_ack(display);
if (iir & I915_MASTER_ERROR_INTERRUPT)
vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
@@ -392,7 +392,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
if (hotplug_status)
- i9xx_hpd_irq_handler(dev_priv, hotplug_status);
+ i9xx_hpd_irq_handler(display, hotplug_status);
if (iir & I915_MASTER_ERROR_INTERRUPT)
vlv_display_error_irq_handler(display, eir, dpinvgtt);
@@ -952,6 +952,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
static irqreturn_t i915_irq_handler(int irq, void *arg)
{
struct drm_i915_private *dev_priv = arg;
+ struct intel_display *display = &dev_priv->display;
irqreturn_t ret = IRQ_NONE;
if (!intel_irqs_enabled(dev_priv))
@@ -974,7 +975,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
if (I915_HAS_HOTPLUG(dev_priv) &&
iir & I915_DISPLAY_PORT_INTERRUPT)
- hotplug_status = i9xx_hpd_irq_ack(dev_priv);
+ hotplug_status = i9xx_hpd_irq_ack(display);
/* Call regardless, as some status bits might not be
* signalled in IIR */
@@ -992,7 +993,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
if (hotplug_status)
- i9xx_hpd_irq_handler(dev_priv, hotplug_status);
+ i9xx_hpd_irq_handler(display, hotplug_status);
i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
} while (0);
@@ -1075,6 +1076,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
static irqreturn_t i965_irq_handler(int irq, void *arg)
{
struct drm_i915_private *dev_priv = arg;
+ struct intel_display *display = &dev_priv->display;
irqreturn_t ret = IRQ_NONE;
if (!intel_irqs_enabled(dev_priv))
@@ -1096,7 +1098,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
ret = IRQ_HANDLED;
if (iir & I915_DISPLAY_PORT_INTERRUPT)
- hotplug_status = i9xx_hpd_irq_ack(dev_priv);
+ hotplug_status = i9xx_hpd_irq_ack(display);
/* Call regardless, as some status bits might not be
* signalled in IIR */
@@ -1119,7 +1121,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
if (hotplug_status)
- i9xx_hpd_irq_handler(dev_priv, hotplug_status);
+ i9xx_hpd_irq_handler(display, hotplug_status);
i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
} while (0);
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* RE: [PATCH 6/9] drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct intel_display
2025-03-11 18:00 ` [PATCH 6/9] drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct intel_display Jani Nikula
@ 2025-03-12 5:33 ` Shankar, Uma
0 siblings, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 5:33 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 6/9] drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct
> intel_display
>
> Going forward, struct intel_display is the main display device data
> pointer. Convert as much as possible of intel_hotplug_irq.[ch] to struct
> intel_display.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 4 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 33 +-
> drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +-
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 474 +++++++++---------
> .../gpu/drm/i915/display/intel_hotplug_irq.h | 28 +-
> drivers/gpu/drm/i915/i915_irq.c | 18 +-
> 6 files changed, 276 insertions(+), 287 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index bca91d49cb96..a7f360f89410 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -606,7 +606,7 @@ static bool intel_crt_detect_hotplug(struct
> drm_connector *connector)
>
> for (i = 0; i < tries ; i++) {
> /* turn on the FORCE_DETECT */
> - i915_hotplug_interrupt_update(dev_priv,
> + i915_hotplug_interrupt_update(display,
> CRT_HOTPLUG_FORCE_DETECT,
> CRT_HOTPLUG_FORCE_DETECT);
> /* wait for FORCE_DETECT to go off */
> @@ -624,7 +624,7 @@ static bool intel_crt_detect_hotplug(struct
> drm_connector *connector)
> intel_de_write(display, PORT_HOTPLUG_STAT(display),
> CRT_HOTPLUG_INT_STATUS);
>
> - i915_hotplug_interrupt_update(dev_priv,
> CRT_HOTPLUG_FORCE_DETECT, 0);
> + i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT,
> 0);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index aa23bb817805..b37bcb8fb2e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -675,7 +675,7 @@ static void ibx_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> enum pipe pipe;
> u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
>
> - ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
> + ibx_hpd_irq_handler(display, hotplug_trigger);
>
> if (pch_iir & SDE_AUDIO_POWER_MASK) {
> int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
> @@ -812,7 +812,7 @@ static void cpt_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> enum pipe pipe;
> u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
>
> - ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
> + ibx_hpd_irq_handler(display, hotplug_trigger);
>
> if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
> int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
> @@ -901,7 +901,7 @@ void ilk_display_irq_handler(struct drm_i915_private
> *dev_priv, u32 de_iir)
> u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
>
> if (hotplug_trigger)
> - ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
> + ilk_hpd_irq_handler(display, hotplug_trigger);
>
> if (de_iir & DE_AUX_CHANNEL_A)
> intel_dp_aux_irq_handler(display);
> @@ -953,7 +953,7 @@ void ivb_display_irq_handler(struct drm_i915_private
> *dev_priv, u32 de_iir)
> u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
>
> if (hotplug_trigger)
> - ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
> + ilk_hpd_irq_handler(display, hotplug_trigger);
>
> if (de_iir & DE_ERR_INT_IVB)
> ivb_err_int_handler(dev_priv);
> @@ -1382,7 +1382,7 @@ void gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
> iir = intel_de_read(display, GEN11_DE_HPD_IIR);
> if (iir) {
> intel_de_write(display, GEN11_DE_HPD_IIR, iir);
> - gen11_hpd_irq_handler(dev_priv, iir);
> + gen11_hpd_irq_handler(display, iir);
> } else {
> drm_err_ratelimited(&dev_priv->drm,
> "The master control interrupt lied,
> (DE HPD)!\n");
> @@ -1405,14 +1405,14 @@ void gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
> u32 hotplug_trigger = iir &
> BXT_DE_PORT_HOTPLUG_MASK;
>
> if (hotplug_trigger) {
> - bxt_hpd_irq_handler(dev_priv,
> hotplug_trigger);
> + bxt_hpd_irq_handler(display,
> hotplug_trigger);
> found = true;
> }
> } else if (IS_BROADWELL(dev_priv)) {
> u32 hotplug_trigger = iir &
> BDW_DE_PORT_HOTPLUG_MASK;
>
> if (hotplug_trigger) {
> - ilk_hpd_irq_handler(dev_priv,
> hotplug_trigger);
> + ilk_hpd_irq_handler(display,
> hotplug_trigger);
> found = true;
> }
> }
> @@ -1498,12 +1498,12 @@ void gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
> gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir);
> if (iir) {
> if (pica_iir)
> - xelpdp_pica_irq_handler(dev_priv, pica_iir);
> + xelpdp_pica_irq_handler(display, pica_iir);
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> - icp_irq_handler(dev_priv, iir);
> + icp_irq_handler(display, iir);
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> - spt_irq_handler(dev_priv, iir);
> + spt_irq_handler(display, iir);
> else
> cpt_irq_handler(dev_priv, iir);
> } else {
> @@ -1904,7 +1904,7 @@ static void _vlv_display_irq_reset(struct
> drm_i915_private *dev_priv)
> gen2_error_reset(to_intel_uncore(display->drm),
> VLV_ERROR_REGS);
>
> - i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
> + i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0);
> intel_de_rmw(display, PORT_HOTPLUG_STAT(dev_priv), 0, 0);
>
> i9xx_pipestat_irq_reset(dev_priv);
> @@ -1924,7 +1924,7 @@ void i9xx_display_irq_reset(struct drm_i915_private
> *i915)
> struct intel_display *display = &i915->display;
>
> if (I915_HAS_HOTPLUG(i915)) {
> - i915_hotplug_interrupt_update(i915, 0xffffffff, 0);
> + i915_hotplug_interrupt_update(display, 0xffffffff, 0);
> intel_de_rmw(display, PORT_HOTPLUG_STAT(i915), 0, 0);
> }
>
> @@ -2348,10 +2348,11 @@ void dg1_de_irq_postinstall(struct drm_i915_private
> *i915)
>
> void intel_display_irq_init(struct drm_i915_private *i915)
> {
> - i915->drm.vblank_disable_immediate = true;
> + struct intel_display *display = &i915->display;
> +
> + display->drm->vblank_disable_immediate = true;
>
> - intel_hotplug_irq_init(i915);
> + intel_hotplug_irq_init(display);
>
> - INIT_WORK(&i915->display.irq.vblank_dc_work,
> - intel_display_vblank_dc_work);
> + INIT_WORK(&display->irq.vblank_dc_work,
> intel_display_vblank_dc_work);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 7683b3ce124d..fcc3f546cb97 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -305,7 +305,7 @@ static void intel_hpd_irq_storm_reenable_work(struct
> work_struct *work)
> display->hotplug.stats[pin].state = HPD_ENABLED;
> }
>
> - intel_hpd_irq_setup(dev_priv);
> + intel_hpd_irq_setup(display);
>
> spin_unlock_irq(&dev_priv->irq_lock);
>
> @@ -696,7 +696,7 @@ void intel_hpd_irq_handler(struct intel_display *display,
> * happens later in our hotplug work.
> */
> if (storm_detected)
> - intel_hpd_irq_setup(dev_priv);
> + intel_hpd_irq_setup(display);
>
> /*
> * Our hotplug handler can grab modeset locks (by calling down into the
> @@ -745,7 +745,7 @@ void intel_hpd_init(struct intel_display *display)
> * just to make the assert_spin_locked checks happy.
> */
> spin_lock_irq(&dev_priv->irq_lock);
> - intel_hpd_irq_setup(dev_priv);
> + intel_hpd_irq_setup(display);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index f24c65478742..e44ae6acc55f 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -131,30 +131,31 @@ static const u32 hpd_mtp[HPD_NUM_PINS] = {
> [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
> };
>
> -static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> +static void intel_hpd_init_pins(struct intel_display *display)
> {
> - struct intel_hotplug *hpd = &dev_priv->display.hotplug;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> + struct intel_hotplug *hpd = &display->hotplug;
>
> - if (HAS_GMCH(dev_priv)) {
> - if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> - IS_CHERRYVIEW(dev_priv))
> + if (HAS_GMCH(display)) {
> + if (display->platform.g4x || display->platform.valleyview ||
> + display->platform.cherryview)
> hpd->hpd = hpd_status_g4x;
> else
> hpd->hpd = hpd_status_i915;
> return;
> }
>
> - if (DISPLAY_VER(dev_priv) >= 14)
> + if (DISPLAY_VER(display) >= 14)
> hpd->hpd = hpd_xelpdp;
> - else if (DISPLAY_VER(dev_priv) >= 11)
> + else if (DISPLAY_VER(display) >= 11)
> hpd->hpd = hpd_gen11;
> - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> + else if (display->platform.geminilake || display->platform.broxton)
> hpd->hpd = hpd_bxt;
> - else if (DISPLAY_VER(dev_priv) == 9)
> + else if (DISPLAY_VER(display) == 9)
> hpd->hpd = NULL; /* no north HPD on SKL */
> - else if (DISPLAY_VER(dev_priv) >= 8)
> + else if (DISPLAY_VER(display) >= 8)
> hpd->hpd = hpd_bdw;
> - else if (DISPLAY_VER(dev_priv) >= 7)
> + else if (DISPLAY_VER(display) >= 7)
> hpd->hpd = hpd_ivb;
> else
> hpd->hpd = hpd_ilk;
> @@ -180,20 +181,20 @@ static void intel_hpd_init_pins(struct drm_i915_private
> *dev_priv)
> }
>
> /* For display hotplug interrupt */
> -void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
> +void i915_hotplug_interrupt_update_locked(struct intel_display *display,
> u32 mask, u32 bits)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> lockdep_assert_held(&dev_priv->irq_lock);
> - drm_WARN_ON(&dev_priv->drm, bits & ~mask);
> + drm_WARN_ON(display->drm, bits & ~mask);
>
> intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);
> }
>
> /**
> * i915_hotplug_interrupt_update - update hotplug interrupt enable
> - * @dev_priv: driver private
> + * @display: display device
> * @mask: bits to update
> * @bits: bits to enable
> * NOTE: the HPD enable bits are modified both inside and outside
> @@ -203,12 +204,14 @@ void i915_hotplug_interrupt_update_locked(struct
> drm_i915_private *dev_priv,
> * held already, this function acquires the lock itself. A non-locking
> * version is also available.
> */
> -void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
> +void i915_hotplug_interrupt_update(struct intel_display *display,
> u32 mask,
> u32 bits)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> spin_lock_irq(&dev_priv->irq_lock);
> - i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
> + i915_hotplug_interrupt_update_locked(display, mask, bits);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> @@ -340,7 +343,7 @@ static bool i9xx_port_hotplug_long_detect(enum hpd_pin
> pin, u32 val)
> *
> * Note that the caller is expected to zero out the masks initially.
> */
> -static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
> +static void intel_get_hpd_pins(struct intel_display *display,
> u32 *pin_mask, u32 *long_mask,
> u32 hotplug_trigger, u32 dig_hotplug_reg,
> const u32 hpd[HPD_NUM_PINS],
> @@ -360,37 +363,37 @@ static void intel_get_hpd_pins(struct drm_i915_private
> *dev_priv,
> *long_mask |= BIT(pin);
> }
>
> - drm_dbg(&dev_priv->drm,
> - "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x,
> long 0x%08x\n",
> - hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
> + drm_dbg_kms(display->drm,
> + "hotplug event received, stat 0x%08x, dig 0x%08x, pins
> 0x%08x, long 0x%08x\n",
> + hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
> }
>
> -static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
> +static u32 intel_hpd_enabled_irqs(struct intel_display *display,
> const u32 hpd[HPD_NUM_PINS])
> {
> struct intel_encoder *encoder;
> u32 enabled_irqs = 0;
>
> - for_each_intel_encoder(&dev_priv->drm, encoder)
> - if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state ==
> HPD_ENABLED)
> + for_each_intel_encoder(display->drm, encoder)
> + if (display->hotplug.stats[encoder->hpd_pin].state ==
> HPD_ENABLED)
> enabled_irqs |= hpd[encoder->hpd_pin];
>
> return enabled_irqs;
> }
>
> -static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
> +static u32 intel_hpd_hotplug_irqs(struct intel_display *display,
> const u32 hpd[HPD_NUM_PINS])
> {
> struct intel_encoder *encoder;
> u32 hotplug_irqs = 0;
>
> - for_each_intel_encoder(&dev_priv->drm, encoder)
> + for_each_intel_encoder(display->drm, encoder)
> hotplug_irqs |= hpd[encoder->hpd_pin];
>
> return hotplug_irqs;
> }
>
> -static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915,
> +static u32 intel_hpd_hotplug_mask(struct intel_display *display,
> hotplug_mask_func hotplug_mask)
> {
> enum hpd_pin pin;
> @@ -402,26 +405,25 @@ static u32 intel_hpd_hotplug_mask(struct
> drm_i915_private *i915,
> return hotplug;
> }
>
> -static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
> +static u32 intel_hpd_hotplug_enables(struct intel_display *display,
> hotplug_enables_func hotplug_enables)
> {
> struct intel_encoder *encoder;
> u32 hotplug = 0;
>
> - for_each_intel_encoder(&i915->drm, encoder)
> + for_each_intel_encoder(display->drm, encoder)
> hotplug |= hotplug_enables(encoder);
>
> return hotplug;
> }
>
> -u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
> +u32 i9xx_hpd_irq_ack(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 hotplug_status = 0, hotplug_status_mask;
> int i;
>
> - if (IS_G4X(dev_priv) ||
> - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + if (display->platform.g4x ||
> + display->platform.valleyview || display->platform.cherryview)
> hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
> DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
> else
> @@ -448,43 +450,41 @@ u32 i9xx_hpd_irq_ack(struct drm_i915_private
> *dev_priv)
> hotplug_status);
> }
>
> - drm_WARN_ONCE(&dev_priv->drm, 1,
> + drm_WARN_ONCE(display->drm, 1,
> "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
> intel_de_read(display, PORT_HOTPLUG_STAT(display)));
>
> return hotplug_status;
> }
>
> -void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_status)
> +void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 pin_mask = 0, long_mask = 0;
> u32 hotplug_trigger;
>
> - if (IS_G4X(dev_priv) ||
> - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + if (display->platform.g4x ||
> + display->platform.valleyview || display->platform.cherryview)
> hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
> else
> hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
>
> if (hotplug_trigger) {
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> hotplug_trigger, hotplug_trigger,
> - dev_priv->display.hotplug.hpd,
> + display->hotplug.hpd,
> i9xx_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> - if ((IS_G4X(dev_priv) ||
> - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> + if ((display->platform.g4x ||
> + display->platform.valleyview || display->platform.cherryview) &&
> hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
> intel_dp_aux_irq_handler(display);
> }
>
> -void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_trigger)
> +void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
>
> /*
> @@ -506,44 +506,43 @@ void ibx_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 hotplug_trigger)
> if (!hotplug_trigger)
> return;
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg,
> - dev_priv->display.hotplug.pch_hpd,
> + display->hotplug.pch_hpd,
> pch_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> -void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
> +void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir)
> {
> - struct intel_display *display = &i915->display;
> enum hpd_pin pin;
> u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK |
> XELPDP_TBT_HOTPLUG_MASK);
> u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
> u32 pin_mask = 0, long_mask = 0;
>
> - if (DISPLAY_VER(i915) >= 20)
> + if (DISPLAY_VER(display) >= 20)
> trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
>
> for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
> u32 val;
>
> - if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger))
> + if (!(display->hotplug.hpd[pin] & hotplug_trigger))
> continue;
>
> pin_mask |= BIT(pin);
>
> - val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin));
> - intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val);
> + val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));
> + intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val);
>
> if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT |
> XELPDP_TBT_HPD_LONG_DETECT))
> long_mask |= BIT(pin);
> }
>
> if (pin_mask) {
> - drm_dbg(&i915->drm,
> - "pica hotplug event received, stat 0x%08x, pins 0x%08x,
> long 0x%08x\n",
> - hotplug_trigger, pin_mask, long_mask);
> + drm_dbg_kms(display->drm,
> + "pica hotplug event received, stat 0x%08x, pins
> 0x%08x, long 0x%08x\n",
> + hotplug_trigger, pin_mask, long_mask);
>
> intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
> @@ -552,13 +551,13 @@ void xelpdp_pica_irq_handler(struct drm_i915_private
> *i915, u32 iir)
> intel_dp_aux_irq_handler(display);
>
> if (!pin_mask && !trigger_aux)
> - drm_err(&i915->drm,
> + drm_err(display->drm,
> "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
> }
>
> -void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> +void icp_irq_handler(struct intel_display *display, u32 pch_iir)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
> u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
> u32 pin_mask = 0, long_mask = 0;
> @@ -571,9 +570,9 @@ void icp_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
> dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0,
> 0);
> spin_unlock(&dev_priv->irq_lock);
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> ddi_hotplug_trigger, dig_hotplug_reg,
> - dev_priv->display.hotplug.pch_hpd,
> + display->hotplug.pch_hpd,
> icp_ddi_port_hotplug_long_detect);
> }
>
> @@ -582,9 +581,9 @@ void icp_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
>
> dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0,
> 0);
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> tc_hotplug_trigger, dig_hotplug_reg,
> - dev_priv->display.hotplug.pch_hpd,
> + display->hotplug.pch_hpd,
> icp_tc_port_hotplug_long_detect);
> }
>
> @@ -595,9 +594,8 @@ void icp_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
> intel_gmbus_irq_handler(display);
> }
>
> -void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> +void spt_irq_handler(struct intel_display *display, u32 pch_iir)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> ~SDE_PORTE_HOTPLUG_SPT;
> u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
> @@ -608,9 +606,9 @@ void spt_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
>
> dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG,
> 0, 0);
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg,
> - dev_priv->display.hotplug.pch_hpd,
> + display->hotplug.pch_hpd,
> spt_port_hotplug_long_detect);
> }
>
> @@ -619,9 +617,9 @@ void spt_irq_handler(struct drm_i915_private *dev_priv,
> u32 pch_iir)
>
> dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2,
> 0, 0);
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> hotplug2_trigger, dig_hotplug_reg,
> - dev_priv->display.hotplug.pch_hpd,
> + display->hotplug.pch_hpd,
> spt_port_hotplug2_long_detect);
> }
>
> @@ -632,39 +630,36 @@ void spt_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> intel_gmbus_irq_handler(display);
> }
>
> -void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_trigger)
> +void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
>
> dig_hotplug_reg = intel_de_rmw(display,
> DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg,
> - dev_priv->display.hotplug.hpd,
> + display->hotplug.hpd,
> ilk_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> -void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32
> hotplug_trigger)
> +void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
>
> dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg,
> - dev_priv->display.hotplug.hpd,
> + display->hotplug.hpd,
> bxt_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(display, pin_mask, long_mask);
> }
>
> -void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> +void gen11_hpd_irq_handler(struct intel_display *display, u32 iir)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 pin_mask = 0, long_mask = 0;
> u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
> u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
> @@ -674,9 +669,9 @@ void gen11_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
>
> dig_hotplug_reg = intel_de_rmw(display,
> GEN11_TC_HOTPLUG_CTL, 0, 0);
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> trigger_tc, dig_hotplug_reg,
> - dev_priv->display.hotplug.hpd,
> + display->hotplug.hpd,
> gen11_port_hotplug_long_detect);
> }
>
> @@ -685,16 +680,16 @@ void gen11_hpd_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
>
> dig_hotplug_reg = intel_de_rmw(display,
> GEN11_TBT_HOTPLUG_CTL, 0, 0);
>
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + intel_get_hpd_pins(display, &pin_mask, &long_mask,
> trigger_tbt, dig_hotplug_reg,
> - dev_priv->display.hotplug.hpd,
> + display->hotplug.hpd,
> gen11_port_hotplug_long_detect);
> }
>
> if (pin_mask)
> intel_hpd_irq_handler(display, pin_mask, long_mask);
> else
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Unexpected DE HPD interrupt 0x%08x\n", iir);
> }
>
> @@ -740,18 +735,16 @@ static u32 ibx_hotplug_enables(struct intel_encoder
> *encoder)
> }
> }
>
> -static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +static void ibx_hpd_detection_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> /*
> * Enable digital hotplug on the PCH, and configure the DP short pulse
> * duration to 2ms (which is the minimum in the Display Port spec).
> * The pulse duration bits are reserved on LPT+.
> */
> intel_de_rmw(display, PCH_PORT_HOTPLUG,
> - intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
> + intel_hpd_hotplug_mask(display, ibx_hotplug_mask),
> + intel_hpd_hotplug_enables(display, ibx_hotplug_enables));
> }
>
> static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -763,16 +756,17 @@ static void ibx_hpd_enable_detection(struct
> intel_encoder *encoder)
> ibx_hotplug_enables(encoder));
> }
>
> -static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void ibx_hpd_irq_setup(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
>
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
> - ibx_hpd_detection_setup(dev_priv);
> + ibx_hpd_detection_setup(display);
> }
>
> static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
> @@ -813,13 +807,11 @@ static u32 icp_tc_hotplug_enables(struct
> intel_encoder *encoder)
> return icp_tc_hotplug_mask(encoder->hpd_pin);
> }
>
> -static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +static void icp_ddi_hpd_detection_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> intel_de_rmw(display, SHOTPLUG_CTL_DDI,
> - intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> icp_ddi_hotplug_enables));
> + intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask),
> + intel_hpd_hotplug_enables(display,
> icp_ddi_hotplug_enables));
> }
>
> static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -831,13 +823,11 @@ static void icp_ddi_hpd_enable_detection(struct
> intel_encoder *encoder)
> icp_ddi_hotplug_enables(encoder));
> }
>
> -static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +static void icp_tc_hpd_detection_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> intel_de_rmw(display, SHOTPLUG_CTL_TC,
> - intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> icp_tc_hotplug_enables));
> + intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask),
> + intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables));
> }
>
> static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -855,13 +845,13 @@ static void icp_hpd_enable_detection(struct
> intel_encoder *encoder)
> icp_tc_hpd_enable_detection(encoder);
> }
>
> -static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void icp_hpd_irq_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
>
> /*
> * We reduce the value to 250us to be able to detect SHPD when an
> external display
> @@ -871,8 +861,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private
> *dev_priv)
>
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
> - icp_ddi_hpd_detection_setup(dev_priv);
> - icp_tc_hpd_detection_setup(dev_priv);
> + icp_ddi_hpd_detection_setup(display);
> + icp_tc_hpd_detection_setup(display);
> }
>
> static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)
> @@ -895,9 +885,8 @@ static u32 gen11_hotplug_enables(struct intel_encoder
> *encoder)
> return gen11_hotplug_mask(encoder->hpd_pin);
> }
>
> -static void dg1_hpd_invert(struct drm_i915_private *i915)
> +static void dg1_hpd_invert(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> u32 val = (INVERT_DDIA_HPD |
> INVERT_DDIB_HPD |
> INVERT_DDIC_HPD |
> @@ -907,25 +896,23 @@ static void dg1_hpd_invert(struct drm_i915_private
> *i915)
>
> static void dg1_hpd_enable_detection(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - dg1_hpd_invert(i915);
> + dg1_hpd_invert(display);
> icp_hpd_enable_detection(encoder);
> }
>
> -static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void dg1_hpd_irq_setup(struct intel_display *display)
> {
> - dg1_hpd_invert(dev_priv);
> - icp_hpd_irq_setup(dev_priv);
> + dg1_hpd_invert(display);
> + icp_hpd_irq_setup(display);
> }
>
> -static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +static void gen11_tc_hpd_detection_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
> - intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> gen11_hotplug_enables));
> + intel_hpd_hotplug_mask(display, gen11_hotplug_mask),
> + intel_hpd_hotplug_enables(display, gen11_hotplug_enables));
> }
>
> static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -937,13 +924,11 @@ static void gen11_tc_hpd_enable_detection(struct
> intel_encoder *encoder)
> gen11_hotplug_enables(encoder));
> }
>
> -static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +static void gen11_tbt_hpd_detection_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
> - intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv,
> gen11_hotplug_enables));
> + intel_hpd_hotplug_mask(display, gen11_hotplug_mask),
> + intel_hpd_hotplug_enables(display, gen11_hotplug_enables));
> }
>
> static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -966,23 +951,23 @@ static void gen11_hpd_enable_detection(struct
> intel_encoder *encoder)
> icp_hpd_enable_detection(encoder);
> }
>
> -static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void gen11_hpd_irq_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv-
> >display.hotplug.hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
>
> intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs,
> ~enabled_irqs & hotplug_irqs);
> intel_de_posting_read(display, GEN11_DE_HPD_IMR);
>
> - gen11_tc_hpd_detection_setup(dev_priv);
> - gen11_tbt_hpd_detection_setup(dev_priv);
> + gen11_tc_hpd_detection_setup(display);
> + gen11_tbt_hpd_detection_setup(display);
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> - icp_hpd_irq_setup(dev_priv);
> + icp_hpd_irq_setup(display);
> }
>
> static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
> @@ -1019,39 +1004,39 @@ static u32 mtp_tc_hotplug_enables(struct
> intel_encoder *encoder)
> return mtp_tc_hotplug_mask(encoder->hpd_pin);
> }
>
> -static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *i915)
> +static void mtp_ddi_hpd_detection_setup(struct intel_display *display)
> {
> - intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
> - intel_hpd_hotplug_mask(i915, mtp_ddi_hotplug_mask),
> - intel_hpd_hotplug_enables(i915, mtp_ddi_hotplug_enables));
> + intel_de_rmw(display, SHOTPLUG_CTL_DDI,
> + intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask),
> + intel_hpd_hotplug_enables(display,
> mtp_ddi_hotplug_enables));
> }
>
> static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
> + intel_de_rmw(display, SHOTPLUG_CTL_DDI,
> mtp_ddi_hotplug_mask(encoder->hpd_pin),
> mtp_ddi_hotplug_enables(encoder));
> }
>
> -static void mtp_tc_hpd_detection_setup(struct drm_i915_private *i915)
> +static void mtp_tc_hpd_detection_setup(struct intel_display *display)
> {
> - intel_de_rmw(i915, SHOTPLUG_CTL_TC,
> - intel_hpd_hotplug_mask(i915, mtp_tc_hotplug_mask),
> - intel_hpd_hotplug_enables(i915, mtp_tc_hotplug_enables));
> + intel_de_rmw(display, SHOTPLUG_CTL_TC,
> + intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask),
> + intel_hpd_hotplug_enables(display,
> mtp_tc_hotplug_enables));
> }
>
> static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
> + intel_de_rmw(display, SHOTPLUG_CTL_DDI,
> mtp_tc_hotplug_mask(encoder->hpd_pin),
> mtp_tc_hotplug_enables(encoder));
> }
>
> -static void mtp_hpd_invert(struct drm_i915_private *i915)
> +static void mtp_hpd_invert(struct intel_display *display)
> {
> u32 val = (INVERT_DDIA_HPD |
> INVERT_DDIB_HPD |
> @@ -1062,49 +1047,51 @@ static void mtp_hpd_invert(struct drm_i915_private
> *i915)
> INVERT_TC4_HPD |
> INVERT_DDID_HPD_MTP |
> INVERT_DDIE_HPD);
> - intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val);
> + intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);
> }
>
> static void mtp_hpd_enable_detection(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - mtp_hpd_invert(i915);
> + mtp_hpd_invert(display);
> mtp_ddi_hpd_enable_detection(encoder);
> mtp_tc_hpd_enable_detection(encoder);
> }
>
> -static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
> +static void mtp_hpd_irq_setup(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> - enabled_irqs = intel_hpd_enabled_irqs(i915, i915-
> >display.hotplug.pch_hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915-
> >display.hotplug.pch_hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
>
> /*
> * Use 250us here to align with the DP1.4a(Table 3-4) spec as to what the
> * SHPD_FILTER_CNT value should be.
> */
> - intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
> + intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
>
> - mtp_hpd_invert(i915);
> + mtp_hpd_invert(display);
> ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
>
> - mtp_ddi_hpd_detection_setup(i915);
> - mtp_tc_hpd_detection_setup(i915);
> + mtp_ddi_hpd_detection_setup(display);
> + mtp_tc_hpd_detection_setup(display);
> }
>
> -static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
> +static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> - enabled_irqs = intel_hpd_enabled_irqs(i915, i915-
> >display.hotplug.pch_hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915-
> >display.hotplug.pch_hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
>
> ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
>
> - mtp_ddi_hpd_detection_setup(i915);
> - mtp_tc_hpd_detection_setup(i915);
> + mtp_ddi_hpd_detection_setup(display);
> + mtp_tc_hpd_detection_setup(display);
> }
>
> static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
> @@ -1112,7 +1099,7 @@ static bool is_xelpdp_pica_hpd_pin(enum hpd_pin
> hpd_pin)
> return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
> }
>
> -static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915,
> +static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display,
> enum hpd_pin hpd_pin, bool enable)
> {
> u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |
> @@ -1121,18 +1108,18 @@ static void
> _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915,
> if (!is_xelpdp_pica_hpd_pin(hpd_pin))
> return;
>
> - intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
> + intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
> mask, enable ? mask : 0);
> }
>
> static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - _xelpdp_pica_hpd_detection_setup(i915, encoder->hpd_pin, true);
> + _xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true);
> }
>
> -static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915)
> +static void xelpdp_pica_hpd_detection_setup(struct intel_display *display)
> {
> struct intel_encoder *encoder;
> u32 available_pins = 0;
> @@ -1140,11 +1127,11 @@ static void xelpdp_pica_hpd_detection_setup(struct
> drm_i915_private *i915)
>
> BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS);
>
> - for_each_intel_encoder(&i915->drm, encoder)
> + for_each_intel_encoder(display->drm, encoder)
> available_pins |= BIT(encoder->hpd_pin);
>
> for_each_hpd_pin(pin)
> - _xelpdp_pica_hpd_detection_setup(i915, pin, available_pins &
> BIT(pin));
> + _xelpdp_pica_hpd_detection_setup(display, pin, available_pins &
> BIT(pin));
> }
>
> static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -1153,24 +1140,24 @@ static void xelpdp_hpd_enable_detection(struct
> intel_encoder *encoder)
> mtp_hpd_enable_detection(encoder);
> }
>
> -static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
> +static void xelpdp_hpd_irq_setup(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> - enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
>
> - intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs,
> + intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs,
> ~enabled_irqs & hotplug_irqs);
> intel_de_posting_read(display, PICAINTERRUPT_IMR);
>
> - xelpdp_pica_hpd_detection_setup(i915);
> + xelpdp_pica_hpd_detection_setup(display);
>
> if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
> - xe2lpd_sde_hpd_irq_setup(i915);
> + xe2lpd_sde_hpd_irq_setup(display);
> else if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
> - mtp_hpd_irq_setup(i915);
> + mtp_hpd_irq_setup(display);
> }
>
> static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)
> @@ -1209,9 +1196,9 @@ static u32 spt_hotplug2_enables(struct intel_encoder
> *encoder)
> return spt_hotplug2_mask(encoder->hpd_pin);
> }
>
> -static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +static void spt_hpd_detection_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> /* Display WA #1179 WaHardHangonHotPlug: cnp */
> if (HAS_PCH_CNP(dev_priv)) {
> @@ -1221,12 +1208,12 @@ static void spt_hpd_detection_setup(struct
> drm_i915_private *dev_priv)
>
> /* Enable digital hotplug on the PCH */
> intel_de_rmw(display, PCH_PORT_HOTPLUG,
> - intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
> + intel_hpd_hotplug_mask(display, spt_hotplug_mask),
> + intel_hpd_hotplug_enables(display, spt_hotplug_enables));
>
> intel_de_rmw(display, PCH_PORT_HOTPLUG2,
> - intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
> - intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
> + intel_hpd_hotplug_mask(display, spt_hotplug2_mask),
> + intel_hpd_hotplug_enables(display, spt_hotplug2_enables));
> }
>
> static void spt_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -1250,20 +1237,20 @@ static void spt_hpd_enable_detection(struct
> intel_encoder *encoder)
> spt_hotplug2_enables(encoder));
> }
>
> -static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void spt_hpd_irq_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> intel_de_write(display, SHPD_FILTER_CNT,
> SHPD_FILTER_CNT_500_ADJ);
>
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv-
> >display.hotplug.pch_hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
>
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
> - spt_hpd_detection_setup(dev_priv);
> + spt_hpd_detection_setup(display);
> }
>
> static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)
> @@ -1288,18 +1275,16 @@ static u32 ilk_hotplug_enables(struct intel_encoder
> *encoder)
> }
> }
>
> -static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +static void ilk_hpd_detection_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> /*
> * Enable digital hotplug on the CPU, and configure the DP short pulse
> * duration to 2ms (which is the minimum in the Display Port spec)
> * The pulse duration bits are reserved on HSW+.
> */
> intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
> - intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
> + intel_hpd_hotplug_mask(display, ilk_hotplug_mask),
> + intel_hpd_hotplug_enables(display, ilk_hotplug_enables));
> }
>
> static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -1313,21 +1298,22 @@ static void ilk_hpd_enable_detection(struct
> intel_encoder *encoder)
> ibx_hpd_enable_detection(encoder);
> }
>
> -static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void ilk_hpd_irq_setup(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv-
> >display.hotplug.hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
>
> - if (DISPLAY_VER(dev_priv) >= 8)
> + if (DISPLAY_VER(display) >= 8)
> bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
> else
> ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
>
> - ilk_hpd_detection_setup(dev_priv);
> + ilk_hpd_detection_setup(display);
>
> - ibx_hpd_irq_setup(dev_priv);
> + ibx_hpd_irq_setup(display);
> }
>
> static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)
> @@ -1369,13 +1355,11 @@ static u32 bxt_hotplug_enables(struct intel_encoder
> *encoder)
> }
> }
>
> -static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> +static void bxt_hpd_detection_setup(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> intel_de_rmw(display, PCH_PORT_HOTPLUG,
> - intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
> - intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
> + intel_hpd_hotplug_mask(display, bxt_hotplug_mask),
> + intel_hpd_hotplug_enables(display, bxt_hotplug_enables));
> }
>
> static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
> @@ -1387,42 +1371,44 @@ static void bxt_hpd_enable_detection(struct
> intel_encoder *encoder)
> bxt_hotplug_enables(encoder));
> }
>
> -static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void bxt_hpd_irq_setup(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv-
> >display.hotplug.hpd);
> - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv-
> >display.hotplug.hpd);
> + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
>
> bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
>
> - bxt_hpd_detection_setup(dev_priv);
> + bxt_hpd_detection_setup(display);
> }
>
> -static void g45_hpd_peg_band_gap_wa(struct drm_i915_private *i915)
> +static void g45_hpd_peg_band_gap_wa(struct intel_display *display)
> {
> /*
> * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
> * 0xd. Failure to do so will result in spurious interrupts being
> * generated on the port when a cable is not attached.
> */
> - intel_de_rmw(i915, PEG_BAND_GAP_DATA, 0xf, 0xd);
> + intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd);
> }
>
> static void i915_hpd_enable_detection(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];
>
> - if (IS_G45(i915))
> - g45_hpd_peg_band_gap_wa(i915);
> + if (display->platform.g45)
> + g45_hpd_peg_band_gap_wa(display);
>
> /* HPD sense and interrupt enable are one and the same */
> - i915_hotplug_interrupt_update(i915, hotplug_en, hotplug_en);
> + i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en);
> }
>
> -static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void i915_hpd_irq_setup(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_en;
>
> lockdep_assert_held(&dev_priv->irq_lock);
> @@ -1431,20 +1417,20 @@ static void i915_hpd_irq_setup(struct
> drm_i915_private *dev_priv)
> * Note HDMI and DP share hotplug bits. Enable bits are the same for all
> * generations.
> */
> - hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
> + hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915);
> /*
> * Programming the CRT detection parameters tends to generate a
> spurious
> * hotplug event about three seconds later. So just do it once.
> */
> - if (IS_G4X(dev_priv))
> + if (display->platform.g4x)
> hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
> hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
>
> - if (IS_G45(dev_priv))
> - g45_hpd_peg_band_gap_wa(dev_priv);
> + if (display->platform.g45)
> + g45_hpd_peg_band_gap_wa(display);
>
> /* Ignore TV since it's buggy */
> - i915_hotplug_interrupt_update_locked(dev_priv,
> + i915_hotplug_interrupt_update_locked(display,
> HOTPLUG_INT_EN_MASK |
>
> CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
>
> CRT_HOTPLUG_ACTIVATION_PERIOD_64,
> @@ -1453,7 +1439,7 @@ static void i915_hpd_irq_setup(struct
> drm_i915_private *dev_priv)
>
> struct intel_hotplug_funcs {
> /* Enable HPD sense and interrupts for all present encoders */
> - void (*hpd_irq_setup)(struct drm_i915_private *i915);
> + void (*hpd_irq_setup)(struct intel_display *display);
> /* Enable HPD sense for a single encoder */
> void (*hpd_enable_detection)(struct intel_encoder *encoder);
> };
> @@ -1476,49 +1462,49 @@ HPD_FUNCS(ilk);
>
> void intel_hpd_enable_detection(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - if (i915->display.funcs.hotplug)
> - i915->display.funcs.hotplug->hpd_enable_detection(encoder);
> + if (display->funcs.hotplug)
> + display->funcs.hotplug->hpd_enable_detection(encoder);
> }
>
> -void intel_hpd_irq_setup(struct drm_i915_private *i915)
> +void intel_hpd_irq_setup(struct intel_display *display)
> {
> - if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) &&
> - !i915->display.irq.vlv_display_irqs_enabled)
> + if ((display->platform.valleyview || display->platform.cherryview) &&
> + !display->irq.vlv_display_irqs_enabled)
> return;
>
> - if (i915->display.funcs.hotplug)
> - i915->display.funcs.hotplug->hpd_irq_setup(i915);
> + if (display->funcs.hotplug)
> + display->funcs.hotplug->hpd_irq_setup(display);
> }
>
> -void intel_hotplug_irq_init(struct drm_i915_private *i915)
> +void intel_hotplug_irq_init(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
>
> - intel_hpd_init_pins(i915);
> + intel_hpd_init_pins(display);
>
> intel_hpd_init_early(display);
>
> - if (HAS_GMCH(i915)) {
> - if (I915_HAS_HOTPLUG(i915))
> - i915->display.funcs.hotplug = &i915_hpd_funcs;
> + if (HAS_GMCH(display)) {
> + if (I915_HAS_HOTPLUG(display))
> + display->funcs.hotplug = &i915_hpd_funcs;
> } else {
> if (HAS_PCH_DG2(i915))
> - i915->display.funcs.hotplug = &icp_hpd_funcs;
> + display->funcs.hotplug = &icp_hpd_funcs;
> else if (HAS_PCH_DG1(i915))
> - i915->display.funcs.hotplug = &dg1_hpd_funcs;
> - else if (DISPLAY_VER(i915) >= 14)
> - i915->display.funcs.hotplug = &xelpdp_hpd_funcs;
> - else if (DISPLAY_VER(i915) >= 11)
> - i915->display.funcs.hotplug = &gen11_hpd_funcs;
> - else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> - i915->display.funcs.hotplug = &bxt_hpd_funcs;
> + display->funcs.hotplug = &dg1_hpd_funcs;
> + else if (DISPLAY_VER(display) >= 14)
> + display->funcs.hotplug = &xelpdp_hpd_funcs;
> + else if (DISPLAY_VER(display) >= 11)
> + display->funcs.hotplug = &gen11_hpd_funcs;
> + else if (display->platform.geminilake || display-
> >platform.broxton)
> + display->funcs.hotplug = &bxt_hpd_funcs;
> else if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
> - i915->display.funcs.hotplug = &icp_hpd_funcs;
> + display->funcs.hotplug = &icp_hpd_funcs;
> else if (INTEL_PCH_TYPE(i915) >= PCH_SPT)
> - i915->display.funcs.hotplug = &spt_hpd_funcs;
> + display->funcs.hotplug = &spt_hpd_funcs;
> else
> - i915->display.funcs.hotplug = &ilk_hpd_funcs;
> + display->funcs.hotplug = &ilk_hpd_funcs;
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.h
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.h
> index e4db752df096..9063bb02a2e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.h
> @@ -8,28 +8,28 @@
>
> #include <linux/types.h>
>
> -struct drm_i915_private;
> +struct intel_display;
> struct intel_encoder;
>
> -u32 i9xx_hpd_irq_ack(struct drm_i915_private *i915);
> +u32 i9xx_hpd_irq_ack(struct intel_display *display);
>
> -void i9xx_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_status);
> -void ibx_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger);
> -void ilk_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger);
> -void gen11_hpd_irq_handler(struct drm_i915_private *i915, u32 iir);
> -void bxt_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger);
> -void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir);
> -void icp_irq_handler(struct drm_i915_private *i915, u32 pch_iir);
> -void spt_irq_handler(struct drm_i915_private *i915, u32 pch_iir);
> +void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status);
> +void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
> +void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
> +void gen11_hpd_irq_handler(struct intel_display *display, u32 iir);
> +void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
> +void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir);
> +void icp_irq_handler(struct intel_display *display, u32 pch_iir);
> +void spt_irq_handler(struct intel_display *display, u32 pch_iir);
>
> -void i915_hotplug_interrupt_update_locked(struct drm_i915_private *i915,
> +void i915_hotplug_interrupt_update_locked(struct intel_display *display,
> u32 mask, u32 bits);
> -void i915_hotplug_interrupt_update(struct drm_i915_private *i915,
> +void i915_hotplug_interrupt_update(struct intel_display *display,
> u32 mask, u32 bits);
>
> void intel_hpd_enable_detection(struct intel_encoder *encoder);
> -void intel_hpd_irq_setup(struct drm_i915_private *i915);
> +void intel_hpd_irq_setup(struct intel_display *display);
>
> -void intel_hotplug_irq_init(struct drm_i915_private *i915);
> +void intel_hotplug_irq_init(struct intel_display *display);
>
> #endif /* __INTEL_HOTPLUG_IRQ_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index de53615571be..3b05eb3f9cbc 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -277,7 +277,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void
> *arg)
> intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR,
> pm_iir);
>
> if (iir & I915_DISPLAY_PORT_INTERRUPT)
> - hotplug_status = i9xx_hpd_irq_ack(dev_priv);
> + hotplug_status = i9xx_hpd_irq_ack(display);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
> @@ -306,7 +306,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void
> *arg)
> gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
>
> if (hotplug_status)
> - i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> + i9xx_hpd_irq_handler(display, hotplug_status);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> vlv_display_error_irq_handler(display, eir, dpinvgtt);
> @@ -367,7 +367,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void
> *arg)
> gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
>
> if (iir & I915_DISPLAY_PORT_INTERRUPT)
> - hotplug_status = i9xx_hpd_irq_ack(dev_priv);
> + hotplug_status = i9xx_hpd_irq_ack(display);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
> @@ -392,7 +392,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void
> *arg)
> intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ,
> GEN8_MASTER_IRQ_CONTROL);
>
> if (hotplug_status)
> - i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> + i9xx_hpd_irq_handler(display, hotplug_status);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> vlv_display_error_irq_handler(display, eir, dpinvgtt);
> @@ -952,6 +952,7 @@ static void i915_irq_postinstall(struct drm_i915_private
> *dev_priv)
> static irqreturn_t i915_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private *dev_priv = arg;
> + struct intel_display *display = &dev_priv->display;
> irqreturn_t ret = IRQ_NONE;
>
> if (!intel_irqs_enabled(dev_priv))
> @@ -974,7 +975,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>
> if (I915_HAS_HOTPLUG(dev_priv) &&
> iir & I915_DISPLAY_PORT_INTERRUPT)
> - hotplug_status = i9xx_hpd_irq_ack(dev_priv);
> + hotplug_status = i9xx_hpd_irq_ack(display);
>
> /* Call regardless, as some status bits might not be
> * signalled in IIR */
> @@ -992,7 +993,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
> i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>
> if (hotplug_status)
> - i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> + i9xx_hpd_irq_handler(display, hotplug_status);
>
> i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
> } while (0);
> @@ -1075,6 +1076,7 @@ static void i965_irq_postinstall(struct
> drm_i915_private *dev_priv)
> static irqreturn_t i965_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private *dev_priv = arg;
> + struct intel_display *display = &dev_priv->display;
> irqreturn_t ret = IRQ_NONE;
>
> if (!intel_irqs_enabled(dev_priv))
> @@ -1096,7 +1098,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
> ret = IRQ_HANDLED;
>
> if (iir & I915_DISPLAY_PORT_INTERRUPT)
> - hotplug_status = i9xx_hpd_irq_ack(dev_priv);
> + hotplug_status = i9xx_hpd_irq_ack(display);
>
> /* Call regardless, as some status bits might not be
> * signalled in IIR */
> @@ -1119,7 +1121,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
> i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>
> if (hotplug_status)
> - i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> + i9xx_hpd_irq_handler(display, hotplug_status);
>
> i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
> } while (0);
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces to struct intel_display
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (5 preceding siblings ...)
2025-03-11 18:00 ` [PATCH 6/9] drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct intel_display Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-11 19:15 ` Ville Syrjälä
2025-03-12 5:47 ` Shankar, Uma
2025-03-11 18:00 ` [PATCH 8/9] drm/i915/irq: convert rest of intel_display_irq.[ch] " Jani Nikula
` (11 subsequent siblings)
18 siblings, 2 replies; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert the external interfaces of intel_display_irq.[ch] to
struct intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 24 ++-
.../drm/i915/display/intel_display_driver.c | 2 +-
.../gpu/drm/i915/display/intel_display_irq.c | 204 +++++++++---------
.../gpu/drm/i915/display/intel_display_irq.h | 75 ++++---
.../i915/display/intel_display_power_well.c | 12 +-
.../drm/i915/display/intel_fifo_underrun.c | 27 +--
.../gpu/drm/i915/display/intel_hotplug_irq.c | 22 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 3 +-
drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
.../drm/i915/display/skl_universal_plane.c | 6 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
drivers/gpu/drm/i915/i915_irq.c | 98 +++++----
drivers/gpu/drm/xe/display/xe_display.c | 12 +-
13 files changed, 263 insertions(+), 232 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 013295f66d56..5e8344fdfc28 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -630,84 +630,92 @@ vlv_primary_async_flip(struct intel_dsb *dsb,
static void
bdw_primary_enable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
spin_lock_irq(&i915->irq_lock);
- bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
+ bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
spin_unlock_irq(&i915->irq_lock);
}
static void
bdw_primary_disable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
spin_lock_irq(&i915->irq_lock);
- bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
+ bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
spin_unlock_irq(&i915->irq_lock);
}
static void
ivb_primary_enable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
spin_lock_irq(&i915->irq_lock);
- ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
+ ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
spin_unlock_irq(&i915->irq_lock);
}
static void
ivb_primary_disable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
spin_lock_irq(&i915->irq_lock);
- ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
+ ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
spin_unlock_irq(&i915->irq_lock);
}
static void
ilk_primary_enable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
spin_lock_irq(&i915->irq_lock);
- ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
+ ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
spin_unlock_irq(&i915->irq_lock);
}
static void
ilk_primary_disable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
spin_lock_irq(&i915->irq_lock);
- ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
+ ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
spin_unlock_irq(&i915->irq_lock);
}
static void
vlv_primary_enable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
spin_lock_irq(&i915->irq_lock);
- i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
+ i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
spin_unlock_irq(&i915->irq_lock);
}
static void
vlv_primary_disable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
spin_lock_irq(&i915->irq_lock);
- i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
+ i915_disable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
spin_unlock_irq(&i915->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index ae60ccb21520..f76a3a9d66b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -193,7 +193,7 @@ void intel_display_driver_early_probe(struct intel_display *display)
mutex_init(&display->pps.mutex);
mutex_init(&display->hdcp.hdcp_mutex);
- intel_display_irq_init(i915);
+ intel_display_irq_init(display);
intel_dkl_phy_init(display);
intel_color_init_hooks(display);
intel_init_cdclk_hooks(display);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b37bcb8fb2e8..68f903c35978 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -125,14 +125,14 @@ intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
/**
* ilk_update_display_irq - update DEIMR
- * @dev_priv: driver private
+ * @display: display device
* @interrupt_mask: mask of interrupt bits to update
* @enabled_irq_mask: mask of interrupt bits to enable
*/
-void ilk_update_display_irq(struct drm_i915_private *dev_priv,
+void ilk_update_display_irq(struct intel_display *display,
u32 interrupt_mask, u32 enabled_irq_mask)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 new_val;
lockdep_assert_held(&dev_priv->irq_lock);
@@ -150,26 +150,26 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv,
}
}
-void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits)
+void ilk_enable_display_irq(struct intel_display *display, u32 bits)
{
- ilk_update_display_irq(i915, bits, bits);
+ ilk_update_display_irq(display, bits, bits);
}
-void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits)
+void ilk_disable_display_irq(struct intel_display *display, u32 bits)
{
- ilk_update_display_irq(i915, bits, 0);
+ ilk_update_display_irq(display, bits, 0);
}
/**
* bdw_update_port_irq - update DE port interrupt
- * @dev_priv: driver private
+ * @display: display device
* @interrupt_mask: mask of interrupt bits to update
* @enabled_irq_mask: mask of interrupt bits to enable
*/
-void bdw_update_port_irq(struct drm_i915_private *dev_priv,
+void bdw_update_port_irq(struct intel_display *display,
u32 interrupt_mask, u32 enabled_irq_mask)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 new_val;
u32 old_val;
@@ -194,16 +194,16 @@ void bdw_update_port_irq(struct drm_i915_private *dev_priv,
/**
* bdw_update_pipe_irq - update DE pipe interrupt
- * @dev_priv: driver private
+ * @display: display device
* @pipe: pipe whose interrupt to update
* @interrupt_mask: mask of interrupt bits to update
* @enabled_irq_mask: mask of interrupt bits to enable
*/
-static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
+static void bdw_update_pipe_irq(struct intel_display *display,
enum pipe pipe, u32 interrupt_mask,
u32 enabled_irq_mask)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 new_val;
lockdep_assert_held(&dev_priv->irq_lock);
@@ -224,29 +224,29 @@ static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
}
}
-void bdw_enable_pipe_irq(struct drm_i915_private *i915,
+void bdw_enable_pipe_irq(struct intel_display *display,
enum pipe pipe, u32 bits)
{
- bdw_update_pipe_irq(i915, pipe, bits, bits);
+ bdw_update_pipe_irq(display, pipe, bits, bits);
}
-void bdw_disable_pipe_irq(struct drm_i915_private *i915,
+void bdw_disable_pipe_irq(struct intel_display *display,
enum pipe pipe, u32 bits)
{
- bdw_update_pipe_irq(i915, pipe, bits, 0);
+ bdw_update_pipe_irq(display, pipe, bits, 0);
}
/**
* ibx_display_interrupt_update - update SDEIMR
- * @dev_priv: driver private
+ * @display: display device
* @interrupt_mask: mask of interrupt bits to update
* @enabled_irq_mask: mask of interrupt bits to enable
*/
-void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
+void ibx_display_interrupt_update(struct intel_display *display,
u32 interrupt_mask,
u32 enabled_irq_mask)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 sdeimr = intel_de_read(display, SDEIMR);
sdeimr &= ~interrupt_mask;
@@ -263,14 +263,14 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
intel_de_posting_read(display, SDEIMR);
}
-void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits)
+void ibx_enable_display_interrupt(struct intel_display *display, u32 bits)
{
- ibx_display_interrupt_update(i915, bits, bits);
+ ibx_display_interrupt_update(display, bits, bits);
}
-void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits)
+void ibx_disable_display_interrupt(struct intel_display *display, u32 bits)
{
- ibx_display_interrupt_update(i915, bits, 0);
+ ibx_display_interrupt_update(display, bits, 0);
}
u32 i915_pipestat_enable_mask(struct intel_display *display,
@@ -318,10 +318,10 @@ u32 i915_pipestat_enable_mask(struct intel_display *display,
return enable_mask;
}
-void i915_enable_pipestat(struct drm_i915_private *dev_priv,
+void i915_enable_pipestat(struct intel_display *display,
enum pipe pipe, u32 status_mask)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
i915_reg_t reg = PIPESTAT(dev_priv, pipe);
u32 enable_mask;
@@ -342,10 +342,10 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
intel_de_posting_read(display, reg);
}
-void i915_disable_pipestat(struct drm_i915_private *dev_priv,
+void i915_disable_pipestat(struct intel_display *display,
enum pipe pipe, u32 status_mask)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
i915_reg_t reg = PIPESTAT(dev_priv, pipe);
u32 enable_mask;
@@ -381,11 +381,11 @@ static bool i915_has_legacy_blc_interrupt(struct intel_display *display)
/**
* i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
- * @dev_priv: i915 device private
+ * @display: display device
*/
-void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
+void i915_enable_asle_pipestat(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
if (!intel_opregion_asle_present(display))
return;
@@ -395,9 +395,9 @@ void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
spin_lock_irq(&dev_priv->irq_lock);
- i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
+ i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
if (DISPLAY_VER(dev_priv) >= 4)
- i915_enable_pipestat(dev_priv, PIPE_A,
+ i915_enable_pipestat(display, PIPE_A,
PIPE_LEGACY_BLC_EVENT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock);
@@ -524,10 +524,10 @@ static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
}
}
-void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
+void i9xx_pipestat_irq_ack(struct intel_display *display,
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
spin_lock(&dev_priv->irq_lock);
@@ -592,10 +592,10 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
spin_unlock(&dev_priv->irq_lock);
}
-void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+void i915_pipestat_irq_handler(struct intel_display *display,
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
bool blc_event = false;
enum pipe pipe;
@@ -617,10 +617,10 @@ void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
intel_opregion_asle_intr(display);
}
-void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+void i965_pipestat_irq_handler(struct intel_display *display,
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
bool blc_event = false;
enum pipe pipe;
@@ -645,10 +645,10 @@ void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
intel_gmbus_irq_handler(display);
}
-void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+void valleyview_pipestat_irq_handler(struct intel_display *display,
u32 pipe_stats[I915_MAX_PIPES])
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
for_each_pipe(dev_priv, pipe) {
@@ -894,9 +894,9 @@ static void ilk_gtt_fault_irq_handler(struct intel_display *display)
}
}
-void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
+void ilk_display_irq_handler(struct intel_display *display, u32 de_iir)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
@@ -946,9 +946,9 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
gen5_rps_irq_handler(&to_gt(dev_priv)->rps);
}
-void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
+void ivb_display_irq_handler(struct intel_display *display, u32 de_iir)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
@@ -1359,9 +1359,9 @@ static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_i
intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
}
-void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
+void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 iir;
enum pipe pipe;
@@ -1517,9 +1517,8 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
}
}
-u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)
+u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
{
- struct intel_display *display = &i915->display;
u32 iir;
if (!(master_ctl & GEN11_GU_MISC_IRQ))
@@ -1532,17 +1531,15 @@ u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)
return iir;
}
-void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
+void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
{
- struct intel_display *display = &i915->display;
-
if (iir & GEN11_GU_MISC_GSE)
intel_opregion_asle_intr(display);
}
-void gen11_display_irq_handler(struct drm_i915_private *i915)
+void gen11_display_irq_handler(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 disp_ctl;
disable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -1553,7 +1550,7 @@ void gen11_display_irq_handler(struct drm_i915_private *i915)
disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL);
intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
- gen8_de_irq_handler(i915, disp_ctl);
+ gen8_de_irq_handler(display, disp_ctl);
intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -1585,8 +1582,10 @@ static void i915gm_irq_cstate_wa_disable(struct drm_i915_private *i915)
_MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
}
-void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable)
+void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
spin_lock_irq(&i915->drm.vblank_time_lock);
if (enable)
@@ -1599,12 +1598,13 @@ void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable)
int i8xx_enable_vblank(struct drm_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(crtc->dev);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
+ i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
return 0;
@@ -1612,12 +1612,13 @@ int i8xx_enable_vblank(struct drm_crtc *crtc)
void i8xx_disable_vblank(struct drm_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(crtc->dev);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
+ i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
@@ -1641,12 +1642,13 @@ void i915gm_disable_vblank(struct drm_crtc *crtc)
int i965_enable_vblank(struct drm_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(crtc->dev);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- i915_enable_pipestat(dev_priv, pipe,
+ i915_enable_pipestat(display, pipe,
PIPE_START_VBLANK_INTERRUPT_STATUS);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -1655,18 +1657,20 @@ int i965_enable_vblank(struct drm_crtc *crtc)
void i965_disable_vblank(struct drm_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(crtc->dev);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- i915_disable_pipestat(dev_priv, pipe,
+ i915_disable_pipestat(display, pipe,
PIPE_START_VBLANK_INTERRUPT_STATUS);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
int ilk_enable_vblank(struct drm_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(crtc->dev);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
@@ -1674,7 +1678,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- ilk_enable_display_irq(dev_priv, bit);
+ ilk_enable_display_irq(display, bit);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
/* Even though there is no DMC, frame counter can get stuck when
@@ -1688,6 +1692,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
void ilk_disable_vblank(struct drm_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(crtc->dev);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
@@ -1695,7 +1700,7 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- ilk_disable_display_irq(dev_priv, bit);
+ ilk_disable_display_irq(display, bit);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
@@ -1753,7 +1758,7 @@ int bdw_enable_vblank(struct drm_crtc *_crtc)
schedule_work(&display->irq.vblank_dc_work);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+ bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
/* Even if there is no DMC, frame counter can get stuck when
@@ -1777,7 +1782,7 @@ void bdw_disable_vblank(struct drm_crtc *_crtc)
return;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+ bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
if (crtc->block_dc_for_vblank && --display->irq.vblank_wa_num_pipes == 0)
@@ -1913,15 +1918,17 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)
dev_priv->irq_mask = ~0u;
}
-void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
+void vlv_display_irq_reset(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
if (dev_priv->display.irq.vlv_display_irqs_enabled)
_vlv_display_irq_reset(dev_priv);
}
-void i9xx_display_irq_reset(struct drm_i915_private *i915)
+void i9xx_display_irq_reset(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
if (I915_HAS_HOTPLUG(i915)) {
i915_hotplug_interrupt_update(display, 0xffffffff, 0);
@@ -1937,9 +1944,9 @@ static u32 vlv_error_mask(void)
return VLV_ERROR_PAGE_TABLE;
}
-void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
+void vlv_display_irq_postinstall(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 pipestat_mask;
u32 enable_mask;
enum pipe pipe;
@@ -1961,9 +1968,9 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
- i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
+ i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
for_each_pipe(dev_priv, pipe)
- i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
+ i915_enable_pipestat(display, pipe, pipestat_mask);
enable_mask = I915_DISPLAY_PORT_INTERRUPT |
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
@@ -1983,9 +1990,9 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
intel_display_irq_regs_init(display, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask);
}
-void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
+void gen8_display_irq_reset(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
if (!HAS_DISPLAY(dev_priv))
@@ -2003,9 +2010,9 @@ void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);
}
-void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
+void gen11_display_irq_reset(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
@@ -2054,10 +2061,10 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
intel_display_irq_regs_reset(display, SDE_IRQ_REGS);
}
-void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
+void gen8_irq_power_well_post_enable(struct intel_display *display,
u8 pipe_mask)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
gen8_de_pipe_flip_done_mask(dev_priv);
enum pipe pipe;
@@ -2077,10 +2084,10 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
spin_unlock_irq(&dev_priv->irq_lock);
}
-void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
+void gen8_irq_power_well_pre_disable(struct intel_display *display,
u8 pipe_mask)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
spin_lock_irq(&dev_priv->irq_lock);
@@ -2128,8 +2135,10 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
}
-void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
+void valleyview_enable_display_irqs(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
lockdep_assert_held(&dev_priv->irq_lock);
if (dev_priv->display.irq.vlv_display_irqs_enabled)
@@ -2139,12 +2148,14 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
if (intel_irqs_enabled(dev_priv)) {
_vlv_display_irq_reset(dev_priv);
- vlv_display_irq_postinstall(dev_priv);
+ vlv_display_irq_postinstall(display);
}
}
-void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
+void valleyview_disable_display_irqs(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
lockdep_assert_held(&dev_priv->irq_lock);
if (!dev_priv->display.irq.vlv_display_irqs_enabled)
@@ -2156,9 +2167,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
_vlv_display_irq_reset(dev_priv);
}
-void ilk_de_irq_postinstall(struct drm_i915_private *i915)
+void ilk_de_irq_postinstall(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
u32 display_mask, extra_mask;
if (DISPLAY_VER(i915) >= 7) {
@@ -2201,9 +2213,9 @@ void ilk_de_irq_postinstall(struct drm_i915_private *i915)
static void mtp_irq_postinstall(struct drm_i915_private *i915);
static void icp_irq_postinstall(struct drm_i915_private *i915);
-void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
+void gen8_de_irq_postinstall(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
GEN8_PIPE_CDCLK_CRC_DONE;
@@ -2323,33 +2335,27 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
}
-void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
+void gen11_de_irq_postinstall(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
- gen8_de_irq_postinstall(dev_priv);
+ gen8_de_irq_postinstall(display);
intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
}
-void dg1_de_irq_postinstall(struct drm_i915_private *i915)
+void dg1_de_irq_postinstall(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
-
- if (!HAS_DISPLAY(i915))
+ if (!HAS_DISPLAY(display))
return;
- gen8_de_irq_postinstall(i915);
+ gen8_de_irq_postinstall(display);
intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
}
-void intel_display_irq_init(struct drm_i915_private *i915)
+void intel_display_irq_init(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
-
display->drm->vblank_disable_immediate = true;
intel_hotplug_irq_init(display);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index d9867cd0a220..f72727768351 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -12,28 +12,27 @@
enum pipe;
struct drm_crtc;
-struct drm_i915_private;
struct intel_display;
-void valleyview_enable_display_irqs(struct drm_i915_private *i915);
-void valleyview_disable_display_irqs(struct drm_i915_private *i915);
+void valleyview_enable_display_irqs(struct intel_display *display);
+void valleyview_disable_display_irqs(struct intel_display *display);
-void ilk_update_display_irq(struct drm_i915_private *i915,
+void ilk_update_display_irq(struct intel_display *display,
u32 interrupt_mask, u32 enabled_irq_mask);
-void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits);
-void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits);
+void ilk_enable_display_irq(struct intel_display *display, u32 bits);
+void ilk_disable_display_irq(struct intel_display *display, u32 bits);
-void bdw_update_port_irq(struct drm_i915_private *i915, u32 interrupt_mask, u32 enabled_irq_mask);
-void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
-void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
+void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask);
+void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);
+void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);
-void ibx_display_interrupt_update(struct drm_i915_private *i915,
+void ibx_display_interrupt_update(struct intel_display *display,
u32 interrupt_mask, u32 enabled_irq_mask);
-void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits);
-void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits);
+void ibx_enable_display_interrupt(struct intel_display *display, u32 bits);
+void ibx_disable_display_interrupt(struct intel_display *display, u32 bits);
-void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8 pipe_mask);
-void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8 pipe_mask);
+void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask);
+void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask);
int i8xx_enable_vblank(struct drm_crtc *crtc);
int i915gm_enable_vblank(struct drm_crtc *crtc);
@@ -46,41 +45,41 @@ void i965_disable_vblank(struct drm_crtc *crtc);
void ilk_disable_vblank(struct drm_crtc *crtc);
void bdw_disable_vblank(struct drm_crtc *crtc);
-void ivb_display_irq_handler(struct drm_i915_private *i915, u32 de_iir);
-void ilk_display_irq_handler(struct drm_i915_private *i915, u32 de_iir);
-void gen8_de_irq_handler(struct drm_i915_private *i915, u32 master_ctl);
-void gen11_display_irq_handler(struct drm_i915_private *i915);
+void ivb_display_irq_handler(struct intel_display *display, u32 de_iir);
+void ilk_display_irq_handler(struct intel_display *display, u32 de_iir);
+void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
+void gen11_display_irq_handler(struct intel_display *display);
-u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl);
-void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir);
+u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
+void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
-void i9xx_display_irq_reset(struct drm_i915_private *i915);
-void vlv_display_irq_reset(struct drm_i915_private *i915);
-void gen8_display_irq_reset(struct drm_i915_private *i915);
-void gen11_display_irq_reset(struct drm_i915_private *i915);
+void i9xx_display_irq_reset(struct intel_display *display);
+void vlv_display_irq_reset(struct intel_display *display);
+void gen8_display_irq_reset(struct intel_display *display);
+void gen11_display_irq_reset(struct intel_display *display);
-void vlv_display_irq_postinstall(struct drm_i915_private *i915);
-void ilk_de_irq_postinstall(struct drm_i915_private *i915);
-void gen8_de_irq_postinstall(struct drm_i915_private *i915);
-void gen11_de_irq_postinstall(struct drm_i915_private *i915);
-void dg1_de_irq_postinstall(struct drm_i915_private *i915);
+void vlv_display_irq_postinstall(struct intel_display *display);
+void ilk_de_irq_postinstall(struct intel_display *display);
+void gen8_de_irq_postinstall(struct intel_display *display);
+void gen11_de_irq_postinstall(struct intel_display *display);
+void dg1_de_irq_postinstall(struct intel_display *display);
u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
-void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
-void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
-void i915_enable_asle_pipestat(struct drm_i915_private *i915);
+void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
+void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
+void i915_enable_asle_pipestat(struct intel_display *display);
-void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
+void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]);
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
+void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);
void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
-void intel_display_irq_init(struct drm_i915_private *i915);
+void intel_display_irq_init(struct intel_display *display);
-void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable);
+void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
#endif /* __INTEL_DISPLAY_IRQ_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index daf2a0cbb157..b03a95ef64da 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -186,22 +186,18 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
static void hsw_power_well_post_enable(struct intel_display *display,
u8 irq_pipe_mask, bool has_vga)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
if (has_vga)
intel_vga_reset_io_mem(display);
if (irq_pipe_mask)
- gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
+ gen8_irq_power_well_post_enable(display, irq_pipe_mask);
}
static void hsw_power_well_pre_disable(struct intel_display *display,
u8 irq_pipe_mask)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
if (irq_pipe_mask)
- gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
+ gen8_irq_power_well_pre_disable(display, irq_pipe_mask);
}
#define ICL_AUX_PW_TO_PHY(pw_idx) \
@@ -1226,7 +1222,7 @@ static void vlv_display_power_well_init(struct intel_display *display)
vlv_init_display_clock_gating(display);
spin_lock_irq(&dev_priv->irq_lock);
- valleyview_enable_display_irqs(dev_priv);
+ valleyview_enable_display_irqs(display);
spin_unlock_irq(&dev_priv->irq_lock);
/*
@@ -1255,7 +1251,7 @@ static void vlv_display_power_well_deinit(struct intel_display *display)
struct drm_i915_private *dev_priv = to_i915(display->drm);
spin_lock_irq(&dev_priv->irq_lock);
- valleyview_disable_display_irqs(dev_priv);
+ valleyview_disable_display_irqs(display);
spin_unlock_irq(&dev_priv->irq_lock);
/* make sure we're done processing display irqs */
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 7a8fbff39be0..3f47a3beb2e6 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -136,14 +136,13 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
static void ilk_set_fifo_underrun_reporting(struct intel_display *display,
enum pipe pipe, bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 bit = (pipe == PIPE_A) ?
DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
if (enable)
- ilk_enable_display_irq(dev_priv, bit);
+ ilk_enable_display_irq(display, bit);
else
- ilk_disable_display_irq(dev_priv, bit);
+ ilk_disable_display_irq(display, bit);
}
static void ivb_check_fifo_underruns(struct intel_crtc *crtc)
@@ -169,7 +168,6 @@ static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
enum pipe pipe, bool enable,
bool old)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
if (enable) {
intel_de_write(display, GEN7_ERR_INT,
ERR_INT_FIFO_UNDERRUN(pipe));
@@ -177,9 +175,9 @@ static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
if (!ivb_can_enable_err_int(display))
return;
- ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
+ ilk_enable_display_irq(display, DE_ERR_INT_IVB);
} else {
- ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
+ ilk_disable_display_irq(display, DE_ERR_INT_IVB);
if (old &&
intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
@@ -193,26 +191,23 @@ static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
static void bdw_set_fifo_underrun_reporting(struct intel_display *display,
enum pipe pipe, bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
if (enable)
- bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
+ bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);
else
- bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
+ bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);
}
static void ibx_set_fifo_underrun_reporting(struct intel_display *display,
enum pipe pch_transcoder,
bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 bit = (pch_transcoder == PIPE_A) ?
SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
if (enable)
- ibx_enable_display_interrupt(dev_priv, bit);
+ ibx_enable_display_interrupt(display, bit);
else
- ibx_disable_display_interrupt(dev_priv, bit);
+ ibx_disable_display_interrupt(display, bit);
}
static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
@@ -240,8 +235,6 @@ static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
enum pipe pch_transcoder,
bool enable, bool old)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
if (enable) {
intel_de_write(display, SERR_INT,
SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
@@ -249,9 +242,9 @@ static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
if (!cpt_can_enable_serr_int(display))
return;
- ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
+ ibx_enable_display_interrupt(display, SDE_ERROR_CPT);
} else {
- ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
+ ibx_disable_display_interrupt(display, SDE_ERROR_CPT);
if (old && intel_de_read(display, SERR_INT) &
SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index e44ae6acc55f..1bcff3a47745 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -758,13 +758,12 @@ static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
static void ibx_hpd_irq_setup(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+ ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
ibx_hpd_detection_setup(display);
}
@@ -847,7 +846,6 @@ static void icp_hpd_enable_detection(struct intel_encoder *encoder)
static void icp_hpd_irq_setup(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
@@ -859,7 +857,7 @@ static void icp_hpd_irq_setup(struct intel_display *display)
*/
intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+ ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
icp_ddi_hpd_detection_setup(display);
icp_tc_hpd_detection_setup(display);
@@ -1061,7 +1059,6 @@ static void mtp_hpd_enable_detection(struct intel_encoder *encoder)
static void mtp_hpd_irq_setup(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
@@ -1074,7 +1071,7 @@ static void mtp_hpd_irq_setup(struct intel_display *display)
intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
mtp_hpd_invert(display);
- ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
+ ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
mtp_ddi_hpd_detection_setup(display);
mtp_tc_hpd_detection_setup(display);
@@ -1082,13 +1079,12 @@ static void mtp_hpd_irq_setup(struct intel_display *display)
static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
- ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
+ ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
mtp_ddi_hpd_detection_setup(display);
mtp_tc_hpd_detection_setup(display);
@@ -1248,7 +1244,7 @@ static void spt_hpd_irq_setup(struct intel_display *display)
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+ ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
spt_hpd_detection_setup(display);
}
@@ -1300,16 +1296,15 @@ static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
static void ilk_hpd_irq_setup(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
if (DISPLAY_VER(display) >= 8)
- bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
+ bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);
else
- ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
+ ilk_update_display_irq(display, hotplug_irqs, enabled_irqs);
ilk_hpd_detection_setup(display);
@@ -1373,13 +1368,12 @@ static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
static void bxt_hpd_irq_setup(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 hotplug_irqs, enabled_irqs;
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
- bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
+ bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);
bxt_hpd_detection_setup(display);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 10e26c3db946..65f60615f387 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -281,6 +281,7 @@ static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
static void
intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
{
+ struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *pipe_config;
struct drm_atomic_state *state;
@@ -288,7 +289,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
int ret;
if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
- i915gm_irq_cstate_wa(dev_priv, enable);
+ i915gm_irq_cstate_wa(display, enable);
drm_modeset_acquire_init(&ctx, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index 5dbe857ea85b..2e3f3f0207e8 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1594,7 +1594,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
/* Disable TV interrupts around load detect or we'll recurse */
if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
spin_lock_irq(&dev_priv->irq_lock);
- i915_disable_pipestat(dev_priv, 0,
+ i915_disable_pipestat(display, 0,
PIPE_HOTPLUG_INTERRUPT_STATUS |
PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock);
@@ -1669,7 +1669,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
/* Restore interrupt config */
if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
spin_lock_irq(&dev_priv->irq_lock);
- i915_enable_pipestat(dev_priv, 0,
+ i915_enable_pipestat(display, 0,
PIPE_HOTPLUG_INTERRUPT_STATUS |
PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 70e550539bb2..8739195aba69 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2689,22 +2689,24 @@ static const struct drm_plane_funcs tgl_plane_funcs = {
static void
skl_plane_enable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
spin_lock_irq(&i915->irq_lock);
- bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
+ bdw_enable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
spin_unlock_irq(&i915->irq_lock);
}
static void
skl_plane_disable_flip_done(struct intel_plane *plane)
{
+ struct intel_display *display = to_intel_display(plane);
struct drm_i915_private *i915 = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
spin_lock_irq(&i915->irq_lock);
- bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
+ bdw_disable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
spin_unlock_irq(&i915->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 2cfaedb04876..4b46c59588b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -550,6 +550,7 @@ static unsigned int init_emon(struct intel_uncore *uncore)
static bool gen5_rps_enable(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+ struct intel_display *display = &i915->display;
struct intel_uncore *uncore = rps_to_uncore(rps);
u8 fstart, vstart;
u32 rgvmodectl;
@@ -608,7 +609,7 @@ static bool gen5_rps_enable(struct intel_rps *rps)
rps->ips.last_time2 = ktime_get_raw_ns();
spin_lock(&i915->irq_lock);
- ilk_enable_display_irq(i915, DE_PCU_EVENT);
+ ilk_enable_display_irq(display, DE_PCU_EVENT);
spin_unlock(&i915->irq_lock);
spin_unlock_irq(&mchdev_lock);
@@ -621,13 +622,14 @@ static bool gen5_rps_enable(struct intel_rps *rps)
static void gen5_rps_disable(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+ struct intel_display *display = &i915->display;
struct intel_uncore *uncore = rps_to_uncore(rps);
u16 rgvswctl;
spin_lock_irq(&mchdev_lock);
spin_lock(&i915->irq_lock);
- ilk_disable_display_irq(i915, DE_PCU_EVENT);
+ ilk_disable_display_irq(display, DE_PCU_EVENT);
spin_unlock(&i915->irq_lock);
rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3b05eb3f9cbc..ba3afc7e38ac 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -284,7 +284,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
/* Call regardless, as some status bits might not be
* signalled in IIR */
- i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+ i9xx_pipestat_irq_ack(display, iir, pipe_stats);
if (iir & (I915_LPE_PIPE_A_INTERRUPT |
I915_LPE_PIPE_B_INTERRUPT))
@@ -311,7 +311,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
if (iir & I915_MASTER_ERROR_INTERRUPT)
vlv_display_error_irq_handler(display, eir, dpinvgtt);
- valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
+ valleyview_pipestat_irq_handler(display, pipe_stats);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -374,7 +374,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
/* Call regardless, as some status bits might not be
* signalled in IIR */
- i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+ i9xx_pipestat_irq_ack(display, iir, pipe_stats);
if (iir & (I915_LPE_PIPE_A_INTERRUPT |
I915_LPE_PIPE_B_INTERRUPT |
@@ -397,7 +397,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
if (iir & I915_MASTER_ERROR_INTERRUPT)
vlv_display_error_irq_handler(display, eir, dpinvgtt);
- valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
+ valleyview_pipestat_irq_handler(display, pipe_stats);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -418,6 +418,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
static irqreturn_t ilk_irq_handler(int irq, void *arg)
{
struct drm_i915_private *i915 = arg;
+ struct intel_display *display = &i915->display;
void __iomem * const regs = intel_uncore_regs(&i915->uncore);
u32 de_iir, gt_iir, de_ier, sde_ier = 0;
irqreturn_t ret = IRQ_NONE;
@@ -458,9 +459,9 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
if (de_iir) {
raw_reg_write(regs, DEIIR, de_iir);
if (DISPLAY_VER(i915) >= 7)
- ivb_display_irq_handler(i915, de_iir);
+ ivb_display_irq_handler(display, de_iir);
else
- ilk_display_irq_handler(i915, de_iir);
+ ilk_display_irq_handler(display, de_iir);
ret = IRQ_HANDLED;
}
@@ -506,6 +507,7 @@ static inline void gen8_master_intr_enable(void __iomem * const regs)
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
struct drm_i915_private *dev_priv = arg;
+ struct intel_display *display = &dev_priv->display;
void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore);
u32 master_ctl;
@@ -524,7 +526,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & ~GEN8_GT_IRQS) {
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
- gen8_de_irq_handler(dev_priv, master_ctl);
+ gen8_de_irq_handler(display, master_ctl);
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
}
@@ -556,6 +558,7 @@ static inline void gen11_master_intr_enable(void __iomem * const regs)
static irqreturn_t gen11_irq_handler(int irq, void *arg)
{
struct drm_i915_private *i915 = arg;
+ struct intel_display *display = &i915->display;
void __iomem * const regs = intel_uncore_regs(&i915->uncore);
struct intel_gt *gt = to_gt(i915);
u32 master_ctl;
@@ -575,13 +578,13 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & GEN11_DISPLAY_IRQ)
- gen11_display_irq_handler(i915);
+ gen11_display_irq_handler(display);
- gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
+ gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
gen11_master_intr_enable(regs);
- gen11_gu_misc_irq_handler(i915, gu_misc_iir);
+ gen11_gu_misc_irq_handler(display, gu_misc_iir);
pmu_irq_stats(i915, IRQ_HANDLED);
@@ -613,6 +616,7 @@ static inline void dg1_master_intr_enable(void __iomem * const regs)
static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = arg;
+ struct intel_display *display = &i915->display;
struct intel_gt *gt = to_gt(i915);
void __iomem * const regs = intel_uncore_regs(gt->uncore);
u32 master_tile_ctl, master_ctl;
@@ -641,13 +645,13 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
gen11_gt_irq_handler(gt, master_ctl);
if (master_ctl & GEN11_DISPLAY_IRQ)
- gen11_display_irq_handler(i915);
+ gen11_display_irq_handler(display);
- gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
+ gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
dg1_master_intr_enable(regs);
- gen11_gu_misc_irq_handler(i915, gu_misc_iir);
+ gen11_gu_misc_irq_handler(display, gu_misc_iir);
pmu_irq_stats(i915, IRQ_HANDLED);
@@ -691,24 +695,27 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
gen5_gt_irq_reset(to_gt(dev_priv));
spin_lock_irq(&dev_priv->irq_lock);
- vlv_display_irq_reset(dev_priv);
+ vlv_display_irq_reset(display);
spin_unlock_irq(&dev_priv->irq_lock);
}
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
gen8_master_intr_disable(intel_uncore_regs(uncore));
gen8_gt_irq_reset(to_gt(dev_priv));
- gen8_display_irq_reset(dev_priv);
+ gen8_display_irq_reset(display);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
if (HAS_PCH_SPLIT(dev_priv))
@@ -718,13 +725,14 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_gt *gt = to_gt(dev_priv);
struct intel_uncore *uncore = gt->uncore;
gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
+ gen11_display_irq_reset(display);
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -732,6 +740,7 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
struct intel_gt *gt;
unsigned int i;
@@ -741,7 +750,7 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
for_each_gt(gt, dev_priv, i)
gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
+ gen11_display_irq_reset(display);
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -751,6 +760,7 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0);
@@ -761,23 +771,27 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
spin_lock_irq(&dev_priv->irq_lock);
- vlv_display_irq_reset(dev_priv);
+ vlv_display_irq_reset(display);
spin_unlock_irq(&dev_priv->irq_lock);
}
static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
gen5_gt_irq_postinstall(to_gt(dev_priv));
- ilk_de_irq_postinstall(dev_priv);
+ ilk_de_irq_postinstall(display);
}
static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
gen5_gt_irq_postinstall(to_gt(dev_priv));
spin_lock_irq(&dev_priv->irq_lock);
- vlv_display_irq_postinstall(dev_priv);
+ vlv_display_irq_postinstall(display);
spin_unlock_irq(&dev_priv->irq_lock);
intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
@@ -786,20 +800,23 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
gen8_gt_irq_postinstall(to_gt(dev_priv));
- gen8_de_irq_postinstall(dev_priv);
+ gen8_de_irq_postinstall(display);
gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_gt *gt = to_gt(dev_priv);
struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
gen11_gt_irq_postinstall(gt);
- gen11_de_irq_postinstall(dev_priv);
+ gen11_de_irq_postinstall(display);
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
@@ -809,6 +826,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
struct intel_gt *gt;
@@ -819,7 +837,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
- dg1_de_irq_postinstall(dev_priv);
+ dg1_de_irq_postinstall(display);
dg1_master_intr_enable(intel_uncore_regs(uncore));
intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
@@ -827,10 +845,12 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
gen8_gt_irq_postinstall(to_gt(dev_priv));
spin_lock_irq(&dev_priv->irq_lock);
- vlv_display_irq_postinstall(dev_priv);
+ vlv_display_irq_postinstall(display);
spin_unlock_irq(&dev_priv->irq_lock);
intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
@@ -900,9 +920,10 @@ static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
static void i915_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
- i9xx_display_irq_reset(dev_priv);
+ i9xx_display_irq_reset(display);
gen2_error_reset(uncore, GEN2_ERROR_REGS);
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
@@ -911,6 +932,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
u32 enable_mask;
@@ -942,11 +964,11 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
spin_lock_irq(&dev_priv->irq_lock);
- i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
- i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
+ i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
+ i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock);
- i915_enable_asle_pipestat(dev_priv);
+ i915_enable_asle_pipestat(display);
}
static irqreturn_t i915_irq_handler(int irq, void *arg)
@@ -979,7 +1001,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
/* Call regardless, as some status bits might not be
* signalled in IIR */
- i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+ i9xx_pipestat_irq_ack(display, iir, pipe_stats);
if (iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
@@ -995,7 +1017,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
if (hotplug_status)
i9xx_hpd_irq_handler(display, hotplug_status);
- i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+ i915_pipestat_irq_handler(display, iir, pipe_stats);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -1007,9 +1029,10 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
static void i965_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
- i9xx_display_irq_reset(dev_priv);
+ i9xx_display_irq_reset(display);
gen2_error_reset(uncore, GEN2_ERROR_REGS);
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
@@ -1037,6 +1060,7 @@ static u32 i965_error_mask(struct drm_i915_private *i915)
static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
u32 enable_mask;
@@ -1065,12 +1089,12 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
spin_lock_irq(&dev_priv->irq_lock);
- i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
- i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
- i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
+ i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
+ i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
+ i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock);
- i915_enable_asle_pipestat(dev_priv);
+ i915_enable_asle_pipestat(display);
}
static irqreturn_t i965_irq_handler(int irq, void *arg)
@@ -1102,7 +1126,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
/* Call regardless, as some status bits might not be
* signalled in IIR */
- i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+ i9xx_pipestat_irq_ack(display, iir, pipe_stats);
if (iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
@@ -1123,7 +1147,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
if (hotplug_status)
i9xx_hpd_irq_handler(display, hotplug_status);
- i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+ i965_pipestat_irq_handler(display, iir, pipe_stats);
} while (0);
pmu_irq_stats(dev_priv, IRQ_HANDLED);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 263459323bf7..8e61cfa06647 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -220,11 +220,13 @@ void xe_display_unregister(struct xe_device *xe)
void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
if (master_ctl & DISPLAY_IRQ)
- gen11_display_irq_handler(xe);
+ gen11_display_irq_handler(display);
}
void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
@@ -240,19 +242,23 @@ void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
void xe_display_irq_reset(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
- gen11_display_irq_reset(xe);
+ gen11_display_irq_reset(display);
}
void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
if (gt->info.id == XE_GT0)
- gen11_de_irq_postinstall(xe);
+ gen11_de_irq_postinstall(display);
}
static bool suspend_to_idle(void)
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces to struct intel_display
2025-03-11 18:00 ` [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces " Jani Nikula
@ 2025-03-11 19:15 ` Ville Syrjälä
2025-03-12 9:52 ` Jani Nikula
2025-03-12 5:47 ` Shankar, Uma
1 sibling, 1 reply; 34+ messages in thread
From: Ville Syrjälä @ 2025-03-11 19:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Mar 11, 2025 at 08:00:41PM +0200, Jani Nikula wrote:
> Going forward, struct intel_display is the main display device data
> pointer. Convert the external interfaces of intel_display_irq.[ch] to
> struct intel_display.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 24 ++-
> .../drm/i915/display/intel_display_driver.c | 2 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 204 +++++++++---------
> .../gpu/drm/i915/display/intel_display_irq.h | 75 ++++---
> .../i915/display/intel_display_power_well.c | 12 +-
> .../drm/i915/display/intel_fifo_underrun.c | 27 +--
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 22 +-
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 3 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
> .../drm/i915/display/skl_universal_plane.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
> drivers/gpu/drm/i915/i915_irq.c | 98 +++++----
> drivers/gpu/drm/xe/display/xe_display.c | 12 +-
> 13 files changed, 263 insertions(+), 232 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 013295f66d56..5e8344fdfc28 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -630,84 +630,92 @@ vlv_primary_async_flip(struct intel_dsb *dsb,
> static void
> bdw_primary_enable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> spin_lock_irq(&i915->irq_lock);
> - bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> + bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> bdw_primary_disable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> spin_lock_irq(&i915->irq_lock);
> - bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> + bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> ivb_primary_enable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
>
> spin_lock_irq(&i915->irq_lock);
> - ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
> + ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
> spin_unlock_irq(&i915->irq_lock);
I was pondering if we could just suck the lock into these
guys. But at least the fifo underrun reporting code is using
some of these things and there there the lock is taken
further out. So sadly not as trivial as I was hoping.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces to struct intel_display
2025-03-11 19:15 ` Ville Syrjälä
@ 2025-03-12 9:52 ` Jani Nikula
2025-03-12 10:06 ` Ville Syrjälä
0 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-12 9:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On Tue, 11 Mar 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Mar 11, 2025 at 08:00:41PM +0200, Jani Nikula wrote:
>> static void
>> ivb_primary_enable_flip_done(struct intel_plane *plane)
>> {
>> + struct intel_display *display = to_intel_display(plane);
>> struct drm_i915_private *i915 = to_i915(plane->base.dev);
>>
>> spin_lock_irq(&i915->irq_lock);
>> - ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
>> + ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
>> spin_unlock_irq(&i915->irq_lock);
>
> I was pondering if we could just suck the lock into these
> guys. But at least the fifo underrun reporting code is using
> some of these things and there there the lock is taken
> further out. So sadly not as trivial as I was hoping.
The whole i915->irq_lock (*) is a looming problem for display separation
from i915/xe core.
How do you abstract a spin lock? Is it okay to pass a spinlock_t * from
i915 core code to display, which would then store this pointer and use
it locally?
Wrapping it in a pair of function calls certainly sucks in a lot of
ways.
BR,
Jani.
*) xe->irq.lock on xe, with an ugly #define irq_lock irq.lock
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces to struct intel_display
2025-03-12 9:52 ` Jani Nikula
@ 2025-03-12 10:06 ` Ville Syrjälä
0 siblings, 0 replies; 34+ messages in thread
From: Ville Syrjälä @ 2025-03-12 10:06 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Wed, Mar 12, 2025 at 11:52:33AM +0200, Jani Nikula wrote:
> On Tue, 11 Mar 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Tue, Mar 11, 2025 at 08:00:41PM +0200, Jani Nikula wrote:
> >> static void
> >> ivb_primary_enable_flip_done(struct intel_plane *plane)
> >> {
> >> + struct intel_display *display = to_intel_display(plane);
> >> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> >>
> >> spin_lock_irq(&i915->irq_lock);
> >> - ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
> >> + ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
> >> spin_unlock_irq(&i915->irq_lock);
> >
> > I was pondering if we could just suck the lock into these
> > guys. But at least the fifo underrun reporting code is using
> > some of these things and there there the lock is taken
> > further out. So sadly not as trivial as I was hoping.
>
> The whole i915->irq_lock (*) is a looming problem for display separation
> from i915/xe core.
>
> How do you abstract a spin lock? Is it okay to pass a spinlock_t * from
> i915 core code to display, which would then store this pointer and use
> it locally?
I think we should be able to just switch to our own display->irq_lock.
I don't think we're really protecting anything shared between gt and
display with this.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 34+ messages in thread
* RE: [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces to struct intel_display
2025-03-11 18:00 ` [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces " Jani Nikula
2025-03-11 19:15 ` Ville Syrjälä
@ 2025-03-12 5:47 ` Shankar, Uma
1 sibling, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 5:47 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces to
> struct intel_display
>
> Going forward, struct intel_display is the main display device data
> pointer. Convert the external interfaces of intel_display_irq.[ch] to
> struct intel_display.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 24 ++-
> .../drm/i915/display/intel_display_driver.c | 2 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 204 +++++++++---------
> .../gpu/drm/i915/display/intel_display_irq.h | 75 ++++---
> .../i915/display/intel_display_power_well.c | 12 +-
> .../drm/i915/display/intel_fifo_underrun.c | 27 +--
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 22 +-
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 3 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
> .../drm/i915/display/skl_universal_plane.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
> drivers/gpu/drm/i915/i915_irq.c | 98 +++++----
> drivers/gpu/drm/xe/display/xe_display.c | 12 +-
> 13 files changed, 263 insertions(+), 232 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 013295f66d56..5e8344fdfc28 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -630,84 +630,92 @@ vlv_primary_async_flip(struct intel_dsb *dsb,
> static void
> bdw_primary_enable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> spin_lock_irq(&i915->irq_lock);
> - bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> + bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> bdw_primary_disable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> spin_lock_irq(&i915->irq_lock);
> - bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> + bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> ivb_primary_enable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
>
> spin_lock_irq(&i915->irq_lock);
> - ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane-
> >i9xx_plane));
> + ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane-
> >i9xx_plane));
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> ivb_primary_disable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
>
> spin_lock_irq(&i915->irq_lock);
> - ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane-
> >i9xx_plane));
> + ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane-
> >i9xx_plane));
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> ilk_primary_enable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
>
> spin_lock_irq(&i915->irq_lock);
> - ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
> + ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane-
> >i9xx_plane));
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> ilk_primary_disable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
>
> spin_lock_irq(&i915->irq_lock);
> - ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
> + ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane-
> >i9xx_plane));
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> vlv_primary_enable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> spin_lock_irq(&i915->irq_lock);
> - i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
> + i915_enable_pipestat(display, pipe,
> PLANE_FLIP_DONE_INT_STATUS_VLV);
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> vlv_primary_disable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> spin_lock_irq(&i915->irq_lock);
> - i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
> + i915_disable_pipestat(display, pipe,
> PLANE_FLIP_DONE_INT_STATUS_VLV);
> spin_unlock_irq(&i915->irq_lock);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index ae60ccb21520..f76a3a9d66b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -193,7 +193,7 @@ void intel_display_driver_early_probe(struct intel_display
> *display)
> mutex_init(&display->pps.mutex);
> mutex_init(&display->hdcp.hdcp_mutex);
>
> - intel_display_irq_init(i915);
> + intel_display_irq_init(display);
> intel_dkl_phy_init(display);
> intel_color_init_hooks(display);
> intel_init_cdclk_hooks(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index b37bcb8fb2e8..68f903c35978 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -125,14 +125,14 @@ intel_handle_vblank(struct drm_i915_private
> *dev_priv, enum pipe pipe)
>
> /**
> * ilk_update_display_irq - update DEIMR
> - * @dev_priv: driver private
> + * @display: display device
> * @interrupt_mask: mask of interrupt bits to update
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> -void ilk_update_display_irq(struct drm_i915_private *dev_priv,
> +void ilk_update_display_irq(struct intel_display *display,
> u32 interrupt_mask, u32 enabled_irq_mask)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 new_val;
>
> lockdep_assert_held(&dev_priv->irq_lock);
> @@ -150,26 +150,26 @@ void ilk_update_display_irq(struct drm_i915_private
> *dev_priv,
> }
> }
>
> -void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits)
> +void ilk_enable_display_irq(struct intel_display *display, u32 bits)
> {
> - ilk_update_display_irq(i915, bits, bits);
> + ilk_update_display_irq(display, bits, bits);
> }
>
> -void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits)
> +void ilk_disable_display_irq(struct intel_display *display, u32 bits)
> {
> - ilk_update_display_irq(i915, bits, 0);
> + ilk_update_display_irq(display, bits, 0);
> }
>
> /**
> * bdw_update_port_irq - update DE port interrupt
> - * @dev_priv: driver private
> + * @display: display device
> * @interrupt_mask: mask of interrupt bits to update
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> -void bdw_update_port_irq(struct drm_i915_private *dev_priv,
> +void bdw_update_port_irq(struct intel_display *display,
> u32 interrupt_mask, u32 enabled_irq_mask)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 new_val;
> u32 old_val;
>
> @@ -194,16 +194,16 @@ void bdw_update_port_irq(struct drm_i915_private
> *dev_priv,
>
> /**
> * bdw_update_pipe_irq - update DE pipe interrupt
> - * @dev_priv: driver private
> + * @display: display device
> * @pipe: pipe whose interrupt to update
> * @interrupt_mask: mask of interrupt bits to update
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> -static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
> +static void bdw_update_pipe_irq(struct intel_display *display,
> enum pipe pipe, u32 interrupt_mask,
> u32 enabled_irq_mask)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 new_val;
>
> lockdep_assert_held(&dev_priv->irq_lock);
> @@ -224,29 +224,29 @@ static void bdw_update_pipe_irq(struct
> drm_i915_private *dev_priv,
> }
> }
>
> -void bdw_enable_pipe_irq(struct drm_i915_private *i915,
> +void bdw_enable_pipe_irq(struct intel_display *display,
> enum pipe pipe, u32 bits)
> {
> - bdw_update_pipe_irq(i915, pipe, bits, bits);
> + bdw_update_pipe_irq(display, pipe, bits, bits);
> }
>
> -void bdw_disable_pipe_irq(struct drm_i915_private *i915,
> +void bdw_disable_pipe_irq(struct intel_display *display,
> enum pipe pipe, u32 bits)
> {
> - bdw_update_pipe_irq(i915, pipe, bits, 0);
> + bdw_update_pipe_irq(display, pipe, bits, 0);
> }
>
> /**
> * ibx_display_interrupt_update - update SDEIMR
> - * @dev_priv: driver private
> + * @display: display device
> * @interrupt_mask: mask of interrupt bits to update
> * @enabled_irq_mask: mask of interrupt bits to enable
> */
> -void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
> +void ibx_display_interrupt_update(struct intel_display *display,
> u32 interrupt_mask,
> u32 enabled_irq_mask)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 sdeimr = intel_de_read(display, SDEIMR);
>
> sdeimr &= ~interrupt_mask;
> @@ -263,14 +263,14 @@ void ibx_display_interrupt_update(struct
> drm_i915_private *dev_priv,
> intel_de_posting_read(display, SDEIMR);
> }
>
> -void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits)
> +void ibx_enable_display_interrupt(struct intel_display *display, u32 bits)
> {
> - ibx_display_interrupt_update(i915, bits, bits);
> + ibx_display_interrupt_update(display, bits, bits);
> }
>
> -void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits)
> +void ibx_disable_display_interrupt(struct intel_display *display, u32 bits)
> {
> - ibx_display_interrupt_update(i915, bits, 0);
> + ibx_display_interrupt_update(display, bits, 0);
> }
>
> u32 i915_pipestat_enable_mask(struct intel_display *display,
> @@ -318,10 +318,10 @@ u32 i915_pipestat_enable_mask(struct intel_display
> *display,
> return enable_mask;
> }
>
> -void i915_enable_pipestat(struct drm_i915_private *dev_priv,
> +void i915_enable_pipestat(struct intel_display *display,
> enum pipe pipe, u32 status_mask)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> i915_reg_t reg = PIPESTAT(dev_priv, pipe);
> u32 enable_mask;
>
> @@ -342,10 +342,10 @@ void i915_enable_pipestat(struct drm_i915_private
> *dev_priv,
> intel_de_posting_read(display, reg);
> }
>
> -void i915_disable_pipestat(struct drm_i915_private *dev_priv,
> +void i915_disable_pipestat(struct intel_display *display,
> enum pipe pipe, u32 status_mask)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> i915_reg_t reg = PIPESTAT(dev_priv, pipe);
> u32 enable_mask;
>
> @@ -381,11 +381,11 @@ static bool i915_has_legacy_blc_interrupt(struct
> intel_display *display)
>
> /**
> * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
> - * @dev_priv: i915 device private
> + * @display: display device
> */
> -void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
> +void i915_enable_asle_pipestat(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> if (!intel_opregion_asle_present(display))
> return;
> @@ -395,9 +395,9 @@ void i915_enable_asle_pipestat(struct drm_i915_private
> *dev_priv)
>
> spin_lock_irq(&dev_priv->irq_lock);
>
> - i915_enable_pipestat(dev_priv, PIPE_B,
> PIPE_LEGACY_BLC_EVENT_STATUS);
> + i915_enable_pipestat(display, PIPE_B,
> PIPE_LEGACY_BLC_EVENT_STATUS);
> if (DISPLAY_VER(dev_priv) >= 4)
> - i915_enable_pipestat(dev_priv, PIPE_A,
> + i915_enable_pipestat(display, PIPE_A,
> PIPE_LEGACY_BLC_EVENT_STATUS);
>
> spin_unlock_irq(&dev_priv->irq_lock);
> @@ -524,10 +524,10 @@ static void i9xx_pipestat_irq_reset(struct
> drm_i915_private *dev_priv)
> }
> }
>
> -void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
> +void i9xx_pipestat_irq_ack(struct intel_display *display,
> u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
>
> spin_lock(&dev_priv->irq_lock);
> @@ -592,10 +592,10 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private
> *dev_priv,
> spin_unlock(&dev_priv->irq_lock);
> }
>
> -void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
> +void i915_pipestat_irq_handler(struct intel_display *display,
> u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> bool blc_event = false;
> enum pipe pipe;
>
> @@ -617,10 +617,10 @@ void i915_pipestat_irq_handler(struct
> drm_i915_private *dev_priv,
> intel_opregion_asle_intr(display);
> }
>
> -void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
> +void i965_pipestat_irq_handler(struct intel_display *display,
> u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> bool blc_event = false;
> enum pipe pipe;
>
> @@ -645,10 +645,10 @@ void i965_pipestat_irq_handler(struct
> drm_i915_private *dev_priv,
> intel_gmbus_irq_handler(display);
> }
>
> -void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
> +void valleyview_pipestat_irq_handler(struct intel_display *display,
> u32 pipe_stats[I915_MAX_PIPES])
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
>
> for_each_pipe(dev_priv, pipe) {
> @@ -894,9 +894,9 @@ static void ilk_gtt_fault_irq_handler(struct intel_display
> *display)
> }
> }
>
> -void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
> +void ilk_display_irq_handler(struct intel_display *display, u32 de_iir)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
> u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
>
> @@ -946,9 +946,9 @@ void ilk_display_irq_handler(struct drm_i915_private
> *dev_priv, u32 de_iir)
> gen5_rps_irq_handler(&to_gt(dev_priv)->rps);
> }
>
> -void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
> +void ivb_display_irq_handler(struct intel_display *display, u32 de_iir)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
> u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
>
> @@ -1359,9 +1359,9 @@ static void gen8_read_and_ack_pch_irqs(struct
> drm_i915_private *i915, u32 *pch_i
> intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
> }
>
> -void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> +void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 iir;
> enum pipe pipe;
>
> @@ -1517,9 +1517,8 @@ void gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
> }
> }
>
> -u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32
> master_ctl)
> +u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
> {
> - struct intel_display *display = &i915->display;
> u32 iir;
>
> if (!(master_ctl & GEN11_GU_MISC_IRQ))
> @@ -1532,17 +1531,15 @@ u32 gen11_gu_misc_irq_ack(struct
> drm_i915_private *i915, const u32 master_ctl)
> return iir;
> }
>
> -void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
> +void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
> {
> - struct intel_display *display = &i915->display;
> -
> if (iir & GEN11_GU_MISC_GSE)
> intel_opregion_asle_intr(display);
> }
>
> -void gen11_display_irq_handler(struct drm_i915_private *i915)
> +void gen11_display_irq_handler(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> u32 disp_ctl;
>
> disable_rpm_wakeref_asserts(&i915->runtime_pm);
> @@ -1553,7 +1550,7 @@ void gen11_display_irq_handler(struct
> drm_i915_private *i915)
> disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL);
>
> intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
> - gen8_de_irq_handler(i915, disp_ctl);
> + gen8_de_irq_handler(display, disp_ctl);
> intel_de_write(display, GEN11_DISPLAY_INT_CTL,
> GEN11_DISPLAY_IRQ_ENABLE);
>
> enable_rpm_wakeref_asserts(&i915->runtime_pm);
> @@ -1585,8 +1582,10 @@ static void i915gm_irq_cstate_wa_disable(struct
> drm_i915_private *i915)
>
> _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
> }
>
> -void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable)
> +void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> spin_lock_irq(&i915->drm.vblank_time_lock);
>
> if (enable)
> @@ -1599,12 +1598,13 @@ void i915gm_irq_cstate_wa(struct
> drm_i915_private *i915, bool enable)
>
> int i8xx_enable_vblank(struct drm_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(crtc->dev);
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> unsigned long irqflags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - i915_enable_pipestat(dev_priv, pipe,
> PIPE_VBLANK_INTERRUPT_STATUS);
> + i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> return 0;
> @@ -1612,12 +1612,13 @@ int i8xx_enable_vblank(struct drm_crtc *crtc)
>
> void i8xx_disable_vblank(struct drm_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(crtc->dev);
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> unsigned long irqflags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - i915_disable_pipestat(dev_priv, pipe,
> PIPE_VBLANK_INTERRUPT_STATUS);
> + i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
>
> @@ -1641,12 +1642,13 @@ void i915gm_disable_vblank(struct drm_crtc *crtc)
>
> int i965_enable_vblank(struct drm_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(crtc->dev);
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> unsigned long irqflags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - i915_enable_pipestat(dev_priv, pipe,
> + i915_enable_pipestat(display, pipe,
> PIPE_START_VBLANK_INTERRUPT_STATUS);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> @@ -1655,18 +1657,20 @@ int i965_enable_vblank(struct drm_crtc *crtc)
>
> void i965_disable_vblank(struct drm_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(crtc->dev);
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> unsigned long irqflags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - i915_disable_pipestat(dev_priv, pipe,
> + i915_disable_pipestat(display, pipe,
> PIPE_START_VBLANK_INTERRUPT_STATUS);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
>
> int ilk_enable_vblank(struct drm_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(crtc->dev);
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> unsigned long irqflags;
> @@ -1674,7 +1678,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
> DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - ilk_enable_display_irq(dev_priv, bit);
> + ilk_enable_display_irq(display, bit);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> /* Even though there is no DMC, frame counter can get stuck when
> @@ -1688,6 +1692,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
>
> void ilk_disable_vblank(struct drm_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(crtc->dev);
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> unsigned long irqflags;
> @@ -1695,7 +1700,7 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
> DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - ilk_disable_display_irq(dev_priv, bit);
> + ilk_disable_display_irq(display, bit);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
>
> @@ -1753,7 +1758,7 @@ int bdw_enable_vblank(struct drm_crtc *_crtc)
> schedule_work(&display->irq.vblank_dc_work);
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
> + bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> /* Even if there is no DMC, frame counter can get stuck when
> @@ -1777,7 +1782,7 @@ void bdw_disable_vblank(struct drm_crtc *_crtc)
> return;
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> - bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
> + bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> if (crtc->block_dc_for_vblank && --display->irq.vblank_wa_num_pipes
> == 0)
> @@ -1913,15 +1918,17 @@ static void _vlv_display_irq_reset(struct
> drm_i915_private *dev_priv)
> dev_priv->irq_mask = ~0u;
> }
>
> -void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> +void vlv_display_irq_reset(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> if (dev_priv->display.irq.vlv_display_irqs_enabled)
> _vlv_display_irq_reset(dev_priv);
> }
>
> -void i9xx_display_irq_reset(struct drm_i915_private *i915)
> +void i9xx_display_irq_reset(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
>
> if (I915_HAS_HOTPLUG(i915)) {
> i915_hotplug_interrupt_update(display, 0xffffffff, 0);
> @@ -1937,9 +1944,9 @@ static u32 vlv_error_mask(void)
> return VLV_ERROR_PAGE_TABLE;
> }
>
> -void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
> +void vlv_display_irq_postinstall(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 pipestat_mask;
> u32 enable_mask;
> enum pipe pipe;
> @@ -1961,9 +1968,9 @@ void vlv_display_irq_postinstall(struct
> drm_i915_private *dev_priv)
>
> pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
>
> - i915_enable_pipestat(dev_priv, PIPE_A,
> PIPE_GMBUS_INTERRUPT_STATUS);
> + i915_enable_pipestat(display, PIPE_A,
> PIPE_GMBUS_INTERRUPT_STATUS);
> for_each_pipe(dev_priv, pipe)
> - i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
> + i915_enable_pipestat(display, pipe, pipestat_mask);
>
> enable_mask = I915_DISPLAY_PORT_INTERRUPT |
> I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> @@ -1983,9 +1990,9 @@ void vlv_display_irq_postinstall(struct
> drm_i915_private *dev_priv)
> intel_display_irq_regs_init(display, VLV_IRQ_REGS, dev_priv->irq_mask,
> enable_mask);
> }
>
> -void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
> +void gen8_display_irq_reset(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
>
> if (!HAS_DISPLAY(dev_priv))
> @@ -2003,9 +2010,9 @@ void gen8_display_irq_reset(struct drm_i915_private
> *dev_priv)
> intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);
> }
>
> -void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> +void gen11_display_irq_reset(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
> u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
> @@ -2054,10 +2061,10 @@ void gen11_display_irq_reset(struct
> drm_i915_private *dev_priv)
> intel_display_irq_regs_reset(display, SDE_IRQ_REGS);
> }
>
> -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> +void gen8_irq_power_well_post_enable(struct intel_display *display,
> u8 pipe_mask)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
> gen8_de_pipe_flip_done_mask(dev_priv);
> enum pipe pipe;
> @@ -2077,10 +2084,10 @@ void gen8_irq_power_well_post_enable(struct
> drm_i915_private *dev_priv,
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> -void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
> +void gen8_irq_power_well_pre_disable(struct intel_display *display,
> u8 pipe_mask)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
>
> spin_lock_irq(&dev_priv->irq_lock);
> @@ -2128,8 +2135,10 @@ static void ibx_irq_postinstall(struct
> drm_i915_private *dev_priv)
> intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
> }
>
> -void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
> +void valleyview_enable_display_irqs(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> lockdep_assert_held(&dev_priv->irq_lock);
>
> if (dev_priv->display.irq.vlv_display_irqs_enabled)
> @@ -2139,12 +2148,14 @@ void valleyview_enable_display_irqs(struct
> drm_i915_private *dev_priv)
>
> if (intel_irqs_enabled(dev_priv)) {
> _vlv_display_irq_reset(dev_priv);
> - vlv_display_irq_postinstall(dev_priv);
> + vlv_display_irq_postinstall(display);
> }
> }
>
> -void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
> +void valleyview_disable_display_irqs(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> lockdep_assert_held(&dev_priv->irq_lock);
>
> if (!dev_priv->display.irq.vlv_display_irqs_enabled)
> @@ -2156,9 +2167,10 @@ void valleyview_disable_display_irqs(struct
> drm_i915_private *dev_priv)
> _vlv_display_irq_reset(dev_priv);
> }
>
> -void ilk_de_irq_postinstall(struct drm_i915_private *i915)
> +void ilk_de_irq_postinstall(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> u32 display_mask, extra_mask;
>
> if (DISPLAY_VER(i915) >= 7) {
> @@ -2201,9 +2213,9 @@ void ilk_de_irq_postinstall(struct drm_i915_private
> *i915)
> static void mtp_irq_postinstall(struct drm_i915_private *i915);
> static void icp_irq_postinstall(struct drm_i915_private *i915);
>
> -void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> +void gen8_de_irq_postinstall(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
> GEN8_PIPE_CDCLK_CRC_DONE;
> @@ -2323,33 +2335,27 @@ static void icp_irq_postinstall(struct
> drm_i915_private *dev_priv)
> intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
> }
>
> -void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
> +void gen11_de_irq_postinstall(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(display))
> return;
>
> - gen8_de_irq_postinstall(dev_priv);
> + gen8_de_irq_postinstall(display);
>
> intel_de_write(display, GEN11_DISPLAY_INT_CTL,
> GEN11_DISPLAY_IRQ_ENABLE);
> }
>
> -void dg1_de_irq_postinstall(struct drm_i915_private *i915)
> +void dg1_de_irq_postinstall(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> -
> - if (!HAS_DISPLAY(i915))
> + if (!HAS_DISPLAY(display))
> return;
>
> - gen8_de_irq_postinstall(i915);
> + gen8_de_irq_postinstall(display);
> intel_de_write(display, GEN11_DISPLAY_INT_CTL,
> GEN11_DISPLAY_IRQ_ENABLE);
> }
>
> -void intel_display_irq_init(struct drm_i915_private *i915)
> +void intel_display_irq_init(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> -
> display->drm->vblank_disable_immediate = true;
>
> intel_hotplug_irq_init(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h
> b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index d9867cd0a220..f72727768351 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -12,28 +12,27 @@
>
> enum pipe;
> struct drm_crtc;
> -struct drm_i915_private;
> struct intel_display;
>
> -void valleyview_enable_display_irqs(struct drm_i915_private *i915);
> -void valleyview_disable_display_irqs(struct drm_i915_private *i915);
> +void valleyview_enable_display_irqs(struct intel_display *display);
> +void valleyview_disable_display_irqs(struct intel_display *display);
>
> -void ilk_update_display_irq(struct drm_i915_private *i915,
> +void ilk_update_display_irq(struct intel_display *display,
> u32 interrupt_mask, u32 enabled_irq_mask);
> -void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits);
> -void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits);
> +void ilk_enable_display_irq(struct intel_display *display, u32 bits);
> +void ilk_disable_display_irq(struct intel_display *display, u32 bits);
>
> -void bdw_update_port_irq(struct drm_i915_private *i915, u32 interrupt_mask,
> u32 enabled_irq_mask);
> -void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32
> bits);
> -void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32
> bits);
> +void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32
> enabled_irq_mask);
> +void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32
> bits);
> +void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32
> bits);
>
> -void ibx_display_interrupt_update(struct drm_i915_private *i915,
> +void ibx_display_interrupt_update(struct intel_display *display,
> u32 interrupt_mask, u32 enabled_irq_mask);
> -void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits);
> -void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits);
> +void ibx_enable_display_interrupt(struct intel_display *display, u32 bits);
> +void ibx_disable_display_interrupt(struct intel_display *display, u32 bits);
>
> -void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8
> pipe_mask);
> -void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8
> pipe_mask);
> +void gen8_irq_power_well_post_enable(struct intel_display *display, u8
> pipe_mask);
> +void gen8_irq_power_well_pre_disable(struct intel_display *display, u8
> pipe_mask);
>
> int i8xx_enable_vblank(struct drm_crtc *crtc);
> int i915gm_enable_vblank(struct drm_crtc *crtc);
> @@ -46,41 +45,41 @@ void i965_disable_vblank(struct drm_crtc *crtc);
> void ilk_disable_vblank(struct drm_crtc *crtc);
> void bdw_disable_vblank(struct drm_crtc *crtc);
>
> -void ivb_display_irq_handler(struct drm_i915_private *i915, u32 de_iir);
> -void ilk_display_irq_handler(struct drm_i915_private *i915, u32 de_iir);
> -void gen8_de_irq_handler(struct drm_i915_private *i915, u32 master_ctl);
> -void gen11_display_irq_handler(struct drm_i915_private *i915);
> +void ivb_display_irq_handler(struct intel_display *display, u32 de_iir);
> +void ilk_display_irq_handler(struct intel_display *display, u32 de_iir);
> +void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
> +void gen11_display_irq_handler(struct intel_display *display);
>
> -u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32
> master_ctl);
> -void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir);
> +u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
> +void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>
> -void i9xx_display_irq_reset(struct drm_i915_private *i915);
> -void vlv_display_irq_reset(struct drm_i915_private *i915);
> -void gen8_display_irq_reset(struct drm_i915_private *i915);
> -void gen11_display_irq_reset(struct drm_i915_private *i915);
> +void i9xx_display_irq_reset(struct intel_display *display);
> +void vlv_display_irq_reset(struct intel_display *display);
> +void gen8_display_irq_reset(struct intel_display *display);
> +void gen11_display_irq_reset(struct intel_display *display);
>
> -void vlv_display_irq_postinstall(struct drm_i915_private *i915);
> -void ilk_de_irq_postinstall(struct drm_i915_private *i915);
> -void gen8_de_irq_postinstall(struct drm_i915_private *i915);
> -void gen11_de_irq_postinstall(struct drm_i915_private *i915);
> -void dg1_de_irq_postinstall(struct drm_i915_private *i915);
> +void vlv_display_irq_postinstall(struct intel_display *display);
> +void ilk_de_irq_postinstall(struct intel_display *display);
> +void gen8_de_irq_postinstall(struct intel_display *display);
> +void gen11_de_irq_postinstall(struct intel_display *display);
> +void dg1_de_irq_postinstall(struct intel_display *display);
>
> u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
> -void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32
> status_mask);
> -void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32
> status_mask);
> -void i915_enable_asle_pipestat(struct drm_i915_private *i915);
> +void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32
> status_mask);
> +void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32
> status_mask);
> +void i915_enable_asle_pipestat(struct intel_display *display);
>
> -void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32
> pipe_stats[I915_MAX_PIPES]);
> +void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32
> pipe_stats[I915_MAX_PIPES]);
>
> -void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32
> pipe_stats[I915_MAX_PIPES]);
> -void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32
> pipe_stats[I915_MAX_PIPES]);
> -void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32
> pipe_stats[I915_MAX_PIPES]);
> +void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32
> pipe_stats[I915_MAX_PIPES]);
> +void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32
> pipe_stats[I915_MAX_PIPES]);
> +void valleyview_pipestat_irq_handler(struct intel_display *display, u32
> pipe_stats[I915_MAX_PIPES]);
>
> void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32
> *dpinvgtt);
> void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32
> dpinvgtt);
>
> -void intel_display_irq_init(struct drm_i915_private *i915);
> +void intel_display_irq_init(struct intel_display *display);
>
> -void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable);
> +void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
>
> #endif /* __INTEL_DISPLAY_IRQ_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index daf2a0cbb157..b03a95ef64da 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -186,22 +186,18 @@ int intel_power_well_refcount(struct i915_power_well
> *power_well)
> static void hsw_power_well_post_enable(struct intel_display *display,
> u8 irq_pipe_mask, bool has_vga)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> -
> if (has_vga)
> intel_vga_reset_io_mem(display);
>
> if (irq_pipe_mask)
> - gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
> + gen8_irq_power_well_post_enable(display, irq_pipe_mask);
> }
>
> static void hsw_power_well_pre_disable(struct intel_display *display,
> u8 irq_pipe_mask)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> -
> if (irq_pipe_mask)
> - gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
> + gen8_irq_power_well_pre_disable(display, irq_pipe_mask);
> }
>
> #define ICL_AUX_PW_TO_PHY(pw_idx) \
> @@ -1226,7 +1222,7 @@ static void vlv_display_power_well_init(struct
> intel_display *display)
> vlv_init_display_clock_gating(display);
>
> spin_lock_irq(&dev_priv->irq_lock);
> - valleyview_enable_display_irqs(dev_priv);
> + valleyview_enable_display_irqs(display);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> /*
> @@ -1255,7 +1251,7 @@ static void vlv_display_power_well_deinit(struct
> intel_display *display)
> struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> spin_lock_irq(&dev_priv->irq_lock);
> - valleyview_disable_display_irqs(dev_priv);
> + valleyview_disable_display_irqs(display);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> /* make sure we're done processing display irqs */
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 7a8fbff39be0..3f47a3beb2e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -136,14 +136,13 @@ static void i9xx_set_fifo_underrun_reporting(struct
> intel_display *display,
> static void ilk_set_fifo_underrun_reporting(struct intel_display *display,
> enum pipe pipe, bool enable)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 bit = (pipe == PIPE_A) ?
> DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
>
> if (enable)
> - ilk_enable_display_irq(dev_priv, bit);
> + ilk_enable_display_irq(display, bit);
> else
> - ilk_disable_display_irq(dev_priv, bit);
> + ilk_disable_display_irq(display, bit);
> }
>
> static void ivb_check_fifo_underruns(struct intel_crtc *crtc)
> @@ -169,7 +168,6 @@ static void ivb_set_fifo_underrun_reporting(struct
> intel_display *display,
> enum pipe pipe, bool enable,
> bool old)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> if (enable) {
> intel_de_write(display, GEN7_ERR_INT,
> ERR_INT_FIFO_UNDERRUN(pipe));
> @@ -177,9 +175,9 @@ static void ivb_set_fifo_underrun_reporting(struct
> intel_display *display,
> if (!ivb_can_enable_err_int(display))
> return;
>
> - ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
> + ilk_enable_display_irq(display, DE_ERR_INT_IVB);
> } else {
> - ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
> + ilk_disable_display_irq(display, DE_ERR_INT_IVB);
>
> if (old &&
> intel_de_read(display, GEN7_ERR_INT) &
> ERR_INT_FIFO_UNDERRUN(pipe)) {
> @@ -193,26 +191,23 @@ static void ivb_set_fifo_underrun_reporting(struct
> intel_display *display,
> static void bdw_set_fifo_underrun_reporting(struct intel_display *display,
> enum pipe pipe, bool enable)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> -
> if (enable)
> - bdw_enable_pipe_irq(dev_priv, pipe,
> GEN8_PIPE_FIFO_UNDERRUN);
> + bdw_enable_pipe_irq(display, pipe,
> GEN8_PIPE_FIFO_UNDERRUN);
> else
> - bdw_disable_pipe_irq(dev_priv, pipe,
> GEN8_PIPE_FIFO_UNDERRUN);
> + bdw_disable_pipe_irq(display, pipe,
> GEN8_PIPE_FIFO_UNDERRUN);
> }
>
> static void ibx_set_fifo_underrun_reporting(struct intel_display *display,
> enum pipe pch_transcoder,
> bool enable)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 bit = (pch_transcoder == PIPE_A) ?
> SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
>
> if (enable)
> - ibx_enable_display_interrupt(dev_priv, bit);
> + ibx_enable_display_interrupt(display, bit);
> else
> - ibx_disable_display_interrupt(dev_priv, bit);
> + ibx_disable_display_interrupt(display, bit);
> }
>
> static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
> @@ -240,8 +235,6 @@ static void cpt_set_fifo_underrun_reporting(struct
> intel_display *display,
> enum pipe pch_transcoder,
> bool enable, bool old)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> -
> if (enable) {
> intel_de_write(display, SERR_INT,
>
> SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
> @@ -249,9 +242,9 @@ static void cpt_set_fifo_underrun_reporting(struct
> intel_display *display,
> if (!cpt_can_enable_serr_int(display))
> return;
>
> - ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
> + ibx_enable_display_interrupt(display, SDE_ERROR_CPT);
> } else {
> - ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
> + ibx_disable_display_interrupt(display, SDE_ERROR_CPT);
>
> if (old && intel_de_read(display, SERR_INT) &
> SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index e44ae6acc55f..1bcff3a47745 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -758,13 +758,12 @@ static void ibx_hpd_enable_detection(struct
> intel_encoder *encoder)
>
> static void ibx_hpd_irq_setup(struct intel_display *display)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
>
> - ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> + ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
>
> ibx_hpd_detection_setup(display);
> }
> @@ -847,7 +846,6 @@ static void icp_hpd_enable_detection(struct
> intel_encoder *encoder)
>
> static void icp_hpd_irq_setup(struct intel_display *display)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> @@ -859,7 +857,7 @@ static void icp_hpd_irq_setup(struct intel_display
> *display)
> */
> intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
>
> - ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> + ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
>
> icp_ddi_hpd_detection_setup(display);
> icp_tc_hpd_detection_setup(display);
> @@ -1061,7 +1059,6 @@ static void mtp_hpd_enable_detection(struct
> intel_encoder *encoder)
>
> static void mtp_hpd_irq_setup(struct intel_display *display)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> @@ -1074,7 +1071,7 @@ static void mtp_hpd_irq_setup(struct intel_display
> *display)
> intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
>
> mtp_hpd_invert(display);
> - ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
> + ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
>
> mtp_ddi_hpd_detection_setup(display);
> mtp_tc_hpd_detection_setup(display);
> @@ -1082,13 +1079,12 @@ static void mtp_hpd_irq_setup(struct intel_display
> *display)
>
> static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
>
> - ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
> + ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
>
> mtp_ddi_hpd_detection_setup(display);
> mtp_tc_hpd_detection_setup(display);
> @@ -1248,7 +1244,7 @@ static void spt_hpd_irq_setup(struct intel_display
> *display)
> enabled_irqs = intel_hpd_enabled_irqs(display, display-
> >hotplug.pch_hpd);
> hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
>
> - ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> + ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
>
> spt_hpd_detection_setup(display);
> }
> @@ -1300,16 +1296,15 @@ static void ilk_hpd_enable_detection(struct
> intel_encoder *encoder)
>
> static void ilk_hpd_irq_setup(struct intel_display *display)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
> hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
>
> if (DISPLAY_VER(display) >= 8)
> - bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
> + bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);
> else
> - ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
> + ilk_update_display_irq(display, hotplug_irqs, enabled_irqs);
>
> ilk_hpd_detection_setup(display);
>
> @@ -1373,13 +1368,12 @@ static void bxt_hpd_enable_detection(struct
> intel_encoder *encoder)
>
> static void bxt_hpd_irq_setup(struct intel_display *display)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 hotplug_irqs, enabled_irqs;
>
> enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
> hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
>
> - bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
> + bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);
>
> bxt_hpd_detection_setup(display);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> index 10e26c3db946..65f60615f387 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> @@ -281,6 +281,7 @@ static int ilk_pipe_crc_ctl_reg(enum
> intel_pipe_crc_source *source,
> static void
> intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
> {
> + struct intel_display *display = to_intel_display(crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_crtc_state *pipe_config;
> struct drm_atomic_state *state;
> @@ -288,7 +289,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc
> *crtc, bool enable)
> int ret;
>
> if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
> - i915gm_irq_cstate_wa(dev_priv, enable);
> + i915gm_irq_cstate_wa(display, enable);
>
> drm_modeset_acquire_init(&ctx, 0);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c
> b/drivers/gpu/drm/i915/display/intel_tv.c
> index 5dbe857ea85b..2e3f3f0207e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -1594,7 +1594,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
> /* Disable TV interrupts around load detect or we'll recurse */
> if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
> spin_lock_irq(&dev_priv->irq_lock);
> - i915_disable_pipestat(dev_priv, 0,
> + i915_disable_pipestat(display, 0,
> PIPE_HOTPLUG_INTERRUPT_STATUS |
> PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
> spin_unlock_irq(&dev_priv->irq_lock);
> @@ -1669,7 +1669,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
> /* Restore interrupt config */
> if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
> spin_lock_irq(&dev_priv->irq_lock);
> - i915_enable_pipestat(dev_priv, 0,
> + i915_enable_pipestat(display, 0,
> PIPE_HOTPLUG_INTERRUPT_STATUS |
> PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
> spin_unlock_irq(&dev_priv->irq_lock);
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 70e550539bb2..8739195aba69 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2689,22 +2689,24 @@ static const struct drm_plane_funcs tgl_plane_funcs
> = {
> static void
> skl_plane_enable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> spin_lock_irq(&i915->irq_lock);
> - bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane-
> >id));
> + bdw_enable_pipe_irq(display, pipe,
> GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
> spin_unlock_irq(&i915->irq_lock);
> }
>
> static void
> skl_plane_disable_flip_done(struct intel_plane *plane)
> {
> + struct intel_display *display = to_intel_display(plane);
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> spin_lock_irq(&i915->irq_lock);
> - bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane-
> >id));
> + bdw_disable_pipe_irq(display, pipe,
> GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
> spin_unlock_irq(&i915->irq_lock);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 2cfaedb04876..4b46c59588b8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -550,6 +550,7 @@ static unsigned int init_emon(struct intel_uncore
> *uncore)
> static bool gen5_rps_enable(struct intel_rps *rps)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> + struct intel_display *display = &i915->display;
> struct intel_uncore *uncore = rps_to_uncore(rps);
> u8 fstart, vstart;
> u32 rgvmodectl;
> @@ -608,7 +609,7 @@ static bool gen5_rps_enable(struct intel_rps *rps)
> rps->ips.last_time2 = ktime_get_raw_ns();
>
> spin_lock(&i915->irq_lock);
> - ilk_enable_display_irq(i915, DE_PCU_EVENT);
> + ilk_enable_display_irq(display, DE_PCU_EVENT);
> spin_unlock(&i915->irq_lock);
>
> spin_unlock_irq(&mchdev_lock);
> @@ -621,13 +622,14 @@ static bool gen5_rps_enable(struct intel_rps *rps)
> static void gen5_rps_disable(struct intel_rps *rps)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> + struct intel_display *display = &i915->display;
> struct intel_uncore *uncore = rps_to_uncore(rps);
> u16 rgvswctl;
>
> spin_lock_irq(&mchdev_lock);
>
> spin_lock(&i915->irq_lock);
> - ilk_disable_display_irq(i915, DE_PCU_EVENT);
> + ilk_disable_display_irq(display, DE_PCU_EVENT);
> spin_unlock(&i915->irq_lock);
>
> rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3b05eb3f9cbc..ba3afc7e38ac 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -284,7 +284,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void
> *arg)
>
> /* Call regardless, as some status bits might not be
> * signalled in IIR */
> - i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
> + i9xx_pipestat_irq_ack(display, iir, pipe_stats);
>
> if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> I915_LPE_PIPE_B_INTERRUPT))
> @@ -311,7 +311,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void
> *arg)
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> vlv_display_error_irq_handler(display, eir, dpinvgtt);
>
> - valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
> + valleyview_pipestat_irq_handler(display, pipe_stats);
> } while (0);
>
> pmu_irq_stats(dev_priv, ret);
> @@ -374,7 +374,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void
> *arg)
>
> /* Call regardless, as some status bits might not be
> * signalled in IIR */
> - i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
> + i9xx_pipestat_irq_ack(display, iir, pipe_stats);
>
> if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> I915_LPE_PIPE_B_INTERRUPT |
> @@ -397,7 +397,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void
> *arg)
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> vlv_display_error_irq_handler(display, eir, dpinvgtt);
>
> - valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
> + valleyview_pipestat_irq_handler(display, pipe_stats);
> } while (0);
>
> pmu_irq_stats(dev_priv, ret);
> @@ -418,6 +418,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void
> *arg)
> static irqreturn_t ilk_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private *i915 = arg;
> + struct intel_display *display = &i915->display;
> void __iomem * const regs = intel_uncore_regs(&i915->uncore);
> u32 de_iir, gt_iir, de_ier, sde_ier = 0;
> irqreturn_t ret = IRQ_NONE;
> @@ -458,9 +459,9 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
> if (de_iir) {
> raw_reg_write(regs, DEIIR, de_iir);
> if (DISPLAY_VER(i915) >= 7)
> - ivb_display_irq_handler(i915, de_iir);
> + ivb_display_irq_handler(display, de_iir);
> else
> - ilk_display_irq_handler(i915, de_iir);
> + ilk_display_irq_handler(display, de_iir);
> ret = IRQ_HANDLED;
> }
>
> @@ -506,6 +507,7 @@ static inline void gen8_master_intr_enable(void
> __iomem * const regs)
> static irqreturn_t gen8_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private *dev_priv = arg;
> + struct intel_display *display = &dev_priv->display;
> void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore);
> u32 master_ctl;
>
> @@ -524,7 +526,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
> /* IRQs are synced during runtime_suspend, we don't require a wakeref
> */
> if (master_ctl & ~GEN8_GT_IRQS) {
> disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> - gen8_de_irq_handler(dev_priv, master_ctl);
> + gen8_de_irq_handler(display, master_ctl);
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> }
>
> @@ -556,6 +558,7 @@ static inline void gen11_master_intr_enable(void
> __iomem * const regs)
> static irqreturn_t gen11_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private *i915 = arg;
> + struct intel_display *display = &i915->display;
> void __iomem * const regs = intel_uncore_regs(&i915->uncore);
> struct intel_gt *gt = to_gt(i915);
> u32 master_ctl;
> @@ -575,13 +578,13 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
>
> /* IRQs are synced during runtime_suspend, we don't require a wakeref
> */
> if (master_ctl & GEN11_DISPLAY_IRQ)
> - gen11_display_irq_handler(i915);
> + gen11_display_irq_handler(display);
>
> - gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
> + gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
>
> gen11_master_intr_enable(regs);
>
> - gen11_gu_misc_irq_handler(i915, gu_misc_iir);
> + gen11_gu_misc_irq_handler(display, gu_misc_iir);
>
> pmu_irq_stats(i915, IRQ_HANDLED);
>
> @@ -613,6 +616,7 @@ static inline void dg1_master_intr_enable(void __iomem
> * const regs)
> static irqreturn_t dg1_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = arg;
> + struct intel_display *display = &i915->display;
> struct intel_gt *gt = to_gt(i915);
> void __iomem * const regs = intel_uncore_regs(gt->uncore);
> u32 master_tile_ctl, master_ctl;
> @@ -641,13 +645,13 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> gen11_gt_irq_handler(gt, master_ctl);
>
> if (master_ctl & GEN11_DISPLAY_IRQ)
> - gen11_display_irq_handler(i915);
> + gen11_display_irq_handler(display);
>
> - gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
> + gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
>
> dg1_master_intr_enable(regs);
>
> - gen11_gu_misc_irq_handler(i915, gu_misc_iir);
> + gen11_gu_misc_irq_handler(display, gu_misc_iir);
>
> pmu_irq_stats(i915, IRQ_HANDLED);
>
> @@ -691,24 +695,27 @@ static void ilk_irq_reset(struct drm_i915_private
> *dev_priv)
>
> static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> +
> intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
> intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
>
> gen5_gt_irq_reset(to_gt(dev_priv));
>
> spin_lock_irq(&dev_priv->irq_lock);
> - vlv_display_irq_reset(dev_priv);
> + vlv_display_irq_reset(display);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
>
> gen8_master_intr_disable(intel_uncore_regs(uncore));
>
> gen8_gt_irq_reset(to_gt(dev_priv));
> - gen8_display_irq_reset(dev_priv);
> + gen8_display_irq_reset(display);
> gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
>
> if (HAS_PCH_SPLIT(dev_priv))
> @@ -718,13 +725,14 @@ static void gen8_irq_reset(struct drm_i915_private
> *dev_priv)
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_gt *gt = to_gt(dev_priv);
> struct intel_uncore *uncore = gt->uncore;
>
> gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
>
> gen11_gt_irq_reset(gt);
> - gen11_display_irq_reset(dev_priv);
> + gen11_display_irq_reset(display);
>
> gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
> gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
> @@ -732,6 +740,7 @@ static void gen11_irq_reset(struct drm_i915_private
> *dev_priv)
>
> static void dg1_irq_reset(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
> struct intel_gt *gt;
> unsigned int i;
> @@ -741,7 +750,7 @@ static void dg1_irq_reset(struct drm_i915_private
> *dev_priv)
> for_each_gt(gt, dev_priv, i)
> gen11_gt_irq_reset(gt);
>
> - gen11_display_irq_reset(dev_priv);
> + gen11_display_irq_reset(display);
>
> gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
> gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
> @@ -751,6 +760,7 @@ static void dg1_irq_reset(struct drm_i915_private
> *dev_priv)
>
> static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
>
> intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0);
> @@ -761,23 +771,27 @@ static void cherryview_irq_reset(struct
> drm_i915_private *dev_priv)
> gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
>
> spin_lock_irq(&dev_priv->irq_lock);
> - vlv_display_irq_reset(dev_priv);
> + vlv_display_irq_reset(display);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> +
> gen5_gt_irq_postinstall(to_gt(dev_priv));
>
> - ilk_de_irq_postinstall(dev_priv);
> + ilk_de_irq_postinstall(display);
> }
>
> static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> +
> gen5_gt_irq_postinstall(to_gt(dev_priv));
>
> spin_lock_irq(&dev_priv->irq_lock);
> - vlv_display_irq_postinstall(dev_priv);
> + vlv_display_irq_postinstall(display);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER,
> MASTER_INTERRUPT_ENABLE);
> @@ -786,20 +800,23 @@ static void valleyview_irq_postinstall(struct
> drm_i915_private *dev_priv)
>
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> +
> gen8_gt_irq_postinstall(to_gt(dev_priv));
> - gen8_de_irq_postinstall(dev_priv);
> + gen8_de_irq_postinstall(display);
>
> gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
> }
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_gt *gt = to_gt(dev_priv);
> struct intel_uncore *uncore = gt->uncore;
> u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>
> gen11_gt_irq_postinstall(gt);
> - gen11_de_irq_postinstall(dev_priv);
> + gen11_de_irq_postinstall(display);
>
> gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked,
> gu_misc_masked);
>
> @@ -809,6 +826,7 @@ static void gen11_irq_postinstall(struct drm_i915_private
> *dev_priv)
>
> static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
> u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> struct intel_gt *gt;
> @@ -819,7 +837,7 @@ static void dg1_irq_postinstall(struct drm_i915_private
> *dev_priv)
>
> gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked,
> gu_misc_masked);
>
> - dg1_de_irq_postinstall(dev_priv);
> + dg1_de_irq_postinstall(display);
>
> dg1_master_intr_enable(intel_uncore_regs(uncore));
> intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> @@ -827,10 +845,12 @@ static void dg1_irq_postinstall(struct drm_i915_private
> *dev_priv)
>
> static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> +
> gen8_gt_irq_postinstall(to_gt(dev_priv));
>
> spin_lock_irq(&dev_priv->irq_lock);
> - vlv_display_irq_postinstall(dev_priv);
> + vlv_display_irq_postinstall(display);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ,
> GEN8_MASTER_IRQ_CONTROL);
> @@ -900,9 +920,10 @@ static void i9xx_error_irq_handler(struct
> drm_i915_private *dev_priv,
>
> static void i915_irq_reset(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
>
> - i9xx_display_irq_reset(dev_priv);
> + i9xx_display_irq_reset(display);
>
> gen2_error_reset(uncore, GEN2_ERROR_REGS);
> gen2_irq_reset(uncore, GEN2_IRQ_REGS);
> @@ -911,6 +932,7 @@ static void i915_irq_reset(struct drm_i915_private
> *dev_priv)
>
> static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
> u32 enable_mask;
>
> @@ -942,11 +964,11 @@ static void i915_irq_postinstall(struct
> drm_i915_private *dev_priv)
> /* Interrupt setup is already guaranteed to be single-threaded, this is
> * just to make the assert_spin_locked check happy. */
> spin_lock_irq(&dev_priv->irq_lock);
> - i915_enable_pipestat(dev_priv, PIPE_A,
> PIPE_CRC_DONE_INTERRUPT_STATUS);
> - i915_enable_pipestat(dev_priv, PIPE_B,
> PIPE_CRC_DONE_INTERRUPT_STATUS);
> + i915_enable_pipestat(display, PIPE_A,
> PIPE_CRC_DONE_INTERRUPT_STATUS);
> + i915_enable_pipestat(display, PIPE_B,
> PIPE_CRC_DONE_INTERRUPT_STATUS);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> - i915_enable_asle_pipestat(dev_priv);
> + i915_enable_asle_pipestat(display);
> }
>
> static irqreturn_t i915_irq_handler(int irq, void *arg)
> @@ -979,7 +1001,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>
> /* Call regardless, as some status bits might not be
> * signalled in IIR */
> - i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
> + i9xx_pipestat_irq_ack(display, iir, pipe_stats);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
> @@ -995,7 +1017,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
> if (hotplug_status)
> i9xx_hpd_irq_handler(display, hotplug_status);
>
> - i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
> + i915_pipestat_irq_handler(display, iir, pipe_stats);
> } while (0);
>
> pmu_irq_stats(dev_priv, ret);
> @@ -1007,9 +1029,10 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>
> static void i965_irq_reset(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
>
> - i9xx_display_irq_reset(dev_priv);
> + i9xx_display_irq_reset(display);
>
> gen2_error_reset(uncore, GEN2_ERROR_REGS);
> gen2_irq_reset(uncore, GEN2_IRQ_REGS);
> @@ -1037,6 +1060,7 @@ static u32 i965_error_mask(struct drm_i915_private
> *i915)
>
> static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
> u32 enable_mask;
>
> @@ -1065,12 +1089,12 @@ static void i965_irq_postinstall(struct
> drm_i915_private *dev_priv)
> /* Interrupt setup is already guaranteed to be single-threaded, this is
> * just to make the assert_spin_locked check happy. */
> spin_lock_irq(&dev_priv->irq_lock);
> - i915_enable_pipestat(dev_priv, PIPE_A,
> PIPE_GMBUS_INTERRUPT_STATUS);
> - i915_enable_pipestat(dev_priv, PIPE_A,
> PIPE_CRC_DONE_INTERRUPT_STATUS);
> - i915_enable_pipestat(dev_priv, PIPE_B,
> PIPE_CRC_DONE_INTERRUPT_STATUS);
> + i915_enable_pipestat(display, PIPE_A,
> PIPE_GMBUS_INTERRUPT_STATUS);
> + i915_enable_pipestat(display, PIPE_A,
> PIPE_CRC_DONE_INTERRUPT_STATUS);
> + i915_enable_pipestat(display, PIPE_B,
> PIPE_CRC_DONE_INTERRUPT_STATUS);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> - i915_enable_asle_pipestat(dev_priv);
> + i915_enable_asle_pipestat(display);
> }
>
> static irqreturn_t i965_irq_handler(int irq, void *arg)
> @@ -1102,7 +1126,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>
> /* Call regardless, as some status bits might not be
> * signalled in IIR */
> - i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
> + i9xx_pipestat_irq_ack(display, iir, pipe_stats);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
> @@ -1123,7 +1147,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
> if (hotplug_status)
> i9xx_hpd_irq_handler(display, hotplug_status);
>
> - i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
> + i965_pipestat_irq_handler(display, iir, pipe_stats);
> } while (0);
>
> pmu_irq_stats(dev_priv, IRQ_HANDLED);
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c
> b/drivers/gpu/drm/xe/display/xe_display.c
> index 263459323bf7..8e61cfa06647 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -220,11 +220,13 @@ void xe_display_unregister(struct xe_device *xe)
>
> void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
> {
> + struct intel_display *display = &xe->display;
> +
> if (!xe->info.probe_display)
> return;
>
> if (master_ctl & DISPLAY_IRQ)
> - gen11_display_irq_handler(xe);
> + gen11_display_irq_handler(display);
> }
>
> void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
> @@ -240,19 +242,23 @@ void xe_display_irq_enable(struct xe_device *xe, u32
> gu_misc_iir)
>
> void xe_display_irq_reset(struct xe_device *xe)
> {
> + struct intel_display *display = &xe->display;
> +
> if (!xe->info.probe_display)
> return;
>
> - gen11_display_irq_reset(xe);
> + gen11_display_irq_reset(display);
> }
>
> void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> {
> + struct intel_display *display = &xe->display;
> +
> if (!xe->info.probe_display)
> return;
>
> if (gt->info.id == XE_GT0)
> - gen11_de_irq_postinstall(xe);
> + gen11_de_irq_postinstall(display);
> }
>
> static bool suspend_to_idle(void)
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 8/9] drm/i915/irq: convert rest of intel_display_irq.[ch] to struct intel_display
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (6 preceding siblings ...)
2025-03-11 18:00 ` [PATCH 7/9] drm/i915/irq: convert intel_display_irq.[ch] interfaces " Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-12 5:53 ` Shankar, Uma
2025-03-11 18:00 ` [PATCH 9/9] drm/i915/display: rename I915_HAS_HOTPLUG() to HAS_HOTPLUG Jani Nikula
` (10 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_display_irq.[ch] to struct
intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 527 ++++++++----------
1 file changed, 247 insertions(+), 280 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 68f903c35978..6f78fe6de06a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -115,9 +115,8 @@ static void intel_pipe_fault_irq_handler(struct intel_display *display,
}
static void
-intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
+intel_handle_vblank(struct intel_display *display, enum pipe pipe)
{
- struct intel_display *display = &dev_priv->display;
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drm_crtc_handle_vblank(&crtc->base);
@@ -136,14 +135,14 @@ void ilk_update_display_irq(struct intel_display *display,
u32 new_val;
lockdep_assert_held(&dev_priv->irq_lock);
- drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
+ drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
new_val = dev_priv->irq_mask;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
if (new_val != dev_priv->irq_mask &&
- !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
+ !drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) {
dev_priv->irq_mask = new_val;
intel_de_write(display, DEIMR, dev_priv->irq_mask);
intel_de_posting_read(display, DEIMR);
@@ -175,9 +174,9 @@ void bdw_update_port_irq(struct intel_display *display,
lockdep_assert_held(&dev_priv->irq_lock);
- drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
+ drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
- if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
+ if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))
return;
old_val = intel_de_read(display, GEN8_DE_PORT_IMR);
@@ -208,17 +207,17 @@ static void bdw_update_pipe_irq(struct intel_display *display,
lockdep_assert_held(&dev_priv->irq_lock);
- drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
+ drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
- if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
+ if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))
return;
- new_val = dev_priv->display.irq.de_irq_mask[pipe];
+ new_val = display->irq.de_irq_mask[pipe];
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) {
- dev_priv->display.irq.de_irq_mask[pipe] = new_val;
+ if (new_val != display->irq.de_irq_mask[pipe]) {
+ display->irq.de_irq_mask[pipe] = new_val;
intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]);
intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));
}
@@ -252,11 +251,11 @@ void ibx_display_interrupt_update(struct intel_display *display,
sdeimr &= ~interrupt_mask;
sdeimr |= (~enabled_irq_mask & interrupt_mask);
- drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
+ drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
lockdep_assert_held(&dev_priv->irq_lock);
- if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
+ if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))
return;
intel_de_write(display, SDEIMR, sdeimr);
@@ -322,20 +321,20 @@ void i915_enable_pipestat(struct intel_display *display,
enum pipe pipe, u32 status_mask)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
- i915_reg_t reg = PIPESTAT(dev_priv, pipe);
+ i915_reg_t reg = PIPESTAT(display, pipe);
u32 enable_mask;
- drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
+ drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
"pipe %c: status_mask=0x%x\n",
pipe_name(pipe), status_mask);
lockdep_assert_held(&dev_priv->irq_lock);
- drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
+ drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv));
- if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)
+ if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)
return;
- dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask;
+ display->irq.pipestat_irq_mask[pipe] |= status_mask;
enable_mask = i915_pipestat_enable_mask(display, pipe);
intel_de_write(display, reg, enable_mask | status_mask);
@@ -346,20 +345,20 @@ void i915_disable_pipestat(struct intel_display *display,
enum pipe pipe, u32 status_mask)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
- i915_reg_t reg = PIPESTAT(dev_priv, pipe);
+ i915_reg_t reg = PIPESTAT(display, pipe);
u32 enable_mask;
- drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
+ drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
"pipe %c: status_mask=0x%x\n",
pipe_name(pipe), status_mask);
lockdep_assert_held(&dev_priv->irq_lock);
- drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
+ drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv));
- if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0)
+ if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0)
return;
- dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask;
+ display->irq.pipestat_irq_mask[pipe] &= ~status_mask;
enable_mask = i915_pipestat_enable_mask(display, pipe);
intel_de_write(display, reg, enable_mask | status_mask);
@@ -368,15 +367,13 @@ void i915_disable_pipestat(struct intel_display *display,
static bool i915_has_legacy_blc_interrupt(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
- if (IS_I85X(i915))
+ if (display->platform.i85x)
return true;
- if (IS_PINEVIEW(i915))
+ if (display->platform.pineview)
return true;
- return IS_DISPLAY_VER(display, 3, 4) && IS_MOBILE(i915);
+ return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile;
}
/**
@@ -396,7 +393,7 @@ void i915_enable_asle_pipestat(struct intel_display *display)
spin_lock_irq(&dev_priv->irq_lock);
i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
- if (DISPLAY_VER(dev_priv) >= 4)
+ if (DISPLAY_VER(display) >= 4)
i915_enable_pipestat(display, PIPE_A,
PIPE_LEGACY_BLC_EVENT_STATUS);
@@ -404,13 +401,12 @@ void i915_enable_asle_pipestat(struct intel_display *display)
}
#if IS_ENABLED(CONFIG_DEBUG_FS)
-static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
+static void display_pipe_crc_irq_handler(struct intel_display *display,
enum pipe pipe,
u32 crc0, u32 crc1,
u32 crc2, u32 crc3,
u32 crc4)
{
- struct intel_display *display = &dev_priv->display;
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
@@ -427,7 +423,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
* don't trust that one either.
*/
if (pipe_crc->skipped <= 0 ||
- (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
+ (DISPLAY_VER(display) >= 8 && pipe_crc->skipped == 1)) {
pipe_crc->skipped++;
spin_unlock(&pipe_crc->lock);
return;
@@ -440,20 +436,19 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
}
#else
static inline void
-display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
+display_pipe_crc_irq_handler(struct intel_display *display,
enum pipe pipe,
u32 crc0, u32 crc1,
u32 crc2, u32 crc3,
u32 crc4) {}
#endif
-static void flip_done_handler(struct drm_i915_private *i915,
+static void flip_done_handler(struct intel_display *display,
enum pipe pipe)
{
- struct intel_display *display = &i915->display;
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
- spin_lock(&i915->drm.event_lock);
+ spin_lock(&display->drm->event_lock);
if (crtc->flip_done_event) {
trace_intel_crtc_flip_done(crtc);
@@ -461,25 +456,21 @@ static void flip_done_handler(struct drm_i915_private *i915,
crtc->flip_done_event = NULL;
}
- spin_unlock(&i915->drm.event_lock);
+ spin_unlock(&display->drm->event_lock);
}
-static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
+static void hsw_pipe_crc_irq_handler(struct intel_display *display,
enum pipe pipe)
{
- struct intel_display *display = &dev_priv->display;
-
- display_pipe_crc_irq_handler(dev_priv, pipe,
+ display_pipe_crc_irq_handler(display, pipe,
intel_de_read(display, PIPE_CRC_RES_HSW(pipe)),
0, 0, 0, 0);
}
-static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
+static void ivb_pipe_crc_irq_handler(struct intel_display *display,
enum pipe pipe)
{
- struct intel_display *display = &dev_priv->display;
-
- display_pipe_crc_irq_handler(dev_priv, pipe,
+ display_pipe_crc_irq_handler(display, pipe,
intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)),
intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)),
intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)),
@@ -487,40 +478,38 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe)));
}
-static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
+static void i9xx_pipe_crc_irq_handler(struct intel_display *display,
enum pipe pipe)
{
- struct intel_display *display = &dev_priv->display;
u32 res1, res2;
- if (DISPLAY_VER(dev_priv) >= 3)
- res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(dev_priv, pipe));
+ if (DISPLAY_VER(display) >= 3)
+ res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe));
else
res1 = 0;
- if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
- res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(dev_priv, pipe));
+ if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
+ res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe));
else
res2 = 0;
- display_pipe_crc_irq_handler(dev_priv, pipe,
- intel_de_read(display, PIPE_CRC_RES_RED(dev_priv, pipe)),
- intel_de_read(display, PIPE_CRC_RES_GREEN(dev_priv, pipe)),
- intel_de_read(display, PIPE_CRC_RES_BLUE(dev_priv, pipe)),
+ display_pipe_crc_irq_handler(display, pipe,
+ intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)),
+ intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)),
+ intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)),
res1, res2);
}
-static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
+static void i9xx_pipestat_irq_reset(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
enum pipe pipe;
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
intel_de_write(display,
- PIPESTAT(dev_priv, pipe),
+ PIPESTAT(display, pipe),
PIPESTAT_INT_STATUS_MASK | PIPE_FIFO_UNDERRUN_STATUS);
- dev_priv->display.irq.pipestat_irq_mask[pipe] = 0;
+ display->irq.pipestat_irq_mask[pipe] = 0;
}
}
@@ -532,13 +521,13 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
spin_lock(&dev_priv->irq_lock);
- if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
- !dev_priv->display.irq.vlv_display_irqs_enabled) {
+ if ((display->platform.valleyview || display->platform.cherryview) &&
+ !display->irq.vlv_display_irqs_enabled) {
spin_unlock(&dev_priv->irq_lock);
return;
}
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
i915_reg_t reg;
u32 status_mask, enable_mask, iir_bit = 0;
@@ -566,12 +555,12 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
break;
}
if (iir & iir_bit)
- status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe];
+ status_mask |= display->irq.pipestat_irq_mask[pipe];
if (!status_mask)
continue;
- reg = PIPESTAT(dev_priv, pipe);
+ reg = PIPESTAT(display, pipe);
pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;
enable_mask = i915_pipestat_enable_mask(display, pipe);
@@ -595,19 +584,18 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
void i915_pipestat_irq_handler(struct intel_display *display,
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
bool blc_event = false;
enum pipe pipe;
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
- intel_handle_vblank(dev_priv, pipe);
+ intel_handle_vblank(display, pipe);
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
blc_event = true;
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+ i9xx_pipe_crc_irq_handler(display, pipe);
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
intel_cpu_fifo_underrun_irq_handler(display, pipe);
@@ -620,19 +608,18 @@ void i915_pipestat_irq_handler(struct intel_display *display,
void i965_pipestat_irq_handler(struct intel_display *display,
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
bool blc_event = false;
enum pipe pipe;
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
- intel_handle_vblank(dev_priv, pipe);
+ intel_handle_vblank(display, pipe);
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
blc_event = true;
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+ i9xx_pipe_crc_irq_handler(display, pipe);
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
intel_cpu_fifo_underrun_irq_handler(display, pipe);
@@ -648,18 +635,17 @@ void i965_pipestat_irq_handler(struct intel_display *display,
void valleyview_pipestat_irq_handler(struct intel_display *display,
u32 pipe_stats[I915_MAX_PIPES])
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
- intel_handle_vblank(dev_priv, pipe);
+ intel_handle_vblank(display, pipe);
if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
- flip_done_handler(dev_priv, pipe);
+ flip_done_handler(display, pipe);
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+ i9xx_pipe_crc_irq_handler(display, pipe);
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
intel_cpu_fifo_underrun_irq_handler(display, pipe);
@@ -669,9 +655,8 @@ void valleyview_pipestat_irq_handler(struct intel_display *display,
intel_gmbus_irq_handler(display);
}
-static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+static void ibx_irq_handler(struct intel_display *display, u32 pch_iir)
{
- struct intel_display *display = &dev_priv->display;
enum pipe pipe;
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
@@ -680,7 +665,7 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
if (pch_iir & SDE_AUDIO_POWER_MASK) {
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
SDE_AUDIO_POWER_SHIFT);
- drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
+ drm_dbg(display->drm, "PCH audio power change on port %d\n",
port_name(port));
}
@@ -691,26 +676,26 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_gmbus_irq_handler(display);
if (pch_iir & SDE_AUDIO_HDCP_MASK)
- drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
+ drm_dbg(display->drm, "PCH HDCP audio interrupt\n");
if (pch_iir & SDE_AUDIO_TRANS_MASK)
- drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
+ drm_dbg(display->drm, "PCH transcoder audio interrupt\n");
if (pch_iir & SDE_POISON)
- drm_err(&dev_priv->drm, "PCH poison interrupt\n");
+ drm_err(display->drm, "PCH poison interrupt\n");
if (pch_iir & SDE_FDI_MASK) {
- for_each_pipe(dev_priv, pipe)
- drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
+ for_each_pipe(display, pipe)
+ drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",
pipe_name(pipe),
intel_de_read(display, FDI_RX_IIR(pipe)));
}
if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
- drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
+ drm_dbg(display->drm, "PCH transcoder CRC done interrupt\n");
if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"PCH transcoder CRC error interrupt\n");
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
@@ -753,14 +738,13 @@ static const struct pipe_fault_handler ivb_pipe_fault_handlers[] = {
{}
};
-static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
+static void ivb_err_int_handler(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
u32 err_int = intel_de_read(display, GEN7_ERR_INT);
enum pipe pipe;
if (err_int & ERR_INT_POISON)
- drm_err(&dev_priv->drm, "Poison interrupt\n");
+ drm_err(display->drm, "Poison interrupt\n");
if (err_int & ERR_INT_INVALID_GTT_PTE)
drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");
@@ -768,17 +752,17 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
if (err_int & ERR_INT_INVALID_PTE_DATA)
drm_err_ratelimited(display->drm, "Invalid PTE data\n");
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
u32 fault_errors;
if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
intel_cpu_fifo_underrun_irq_handler(display, pipe);
if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
- if (IS_IVYBRIDGE(dev_priv))
- ivb_pipe_crc_irq_handler(dev_priv, pipe);
+ if (display->platform.ivybridge)
+ ivb_pipe_crc_irq_handler(display, pipe);
else
- hsw_pipe_crc_irq_handler(dev_priv, pipe);
+ hsw_pipe_crc_irq_handler(display, pipe);
}
fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe);
@@ -790,25 +774,23 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
intel_de_write(display, GEN7_ERR_INT, err_int);
}
-static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
+static void cpt_serr_int_handler(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
u32 serr_int = intel_de_read(display, SERR_INT);
enum pipe pipe;
if (serr_int & SERR_INT_POISON)
- drm_err(&dev_priv->drm, "PCH poison interrupt\n");
+ drm_err(display->drm, "PCH poison interrupt\n");
- for_each_pipe(dev_priv, pipe)
+ for_each_pipe(display, pipe)
if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
intel_pch_fifo_underrun_irq_handler(display, pipe);
intel_de_write(display, SERR_INT, serr_int);
}
-static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+static void cpt_irq_handler(struct intel_display *display, u32 pch_iir)
{
- struct intel_display *display = &dev_priv->display;
enum pipe pipe;
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
@@ -817,7 +799,7 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
SDE_AUDIO_POWER_SHIFT_CPT);
- drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
+ drm_dbg(display->drm, "PCH audio power change on port %c\n",
port_name(port));
}
@@ -828,20 +810,20 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_gmbus_irq_handler(display);
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
- drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
+ drm_dbg(display->drm, "Audio CP request interrupt\n");
if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
- drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
+ drm_dbg(display->drm, "Audio CP change interrupt\n");
if (pch_iir & SDE_FDI_MASK_CPT) {
- for_each_pipe(dev_priv, pipe)
- drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
+ for_each_pipe(display, pipe)
+ drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",
pipe_name(pipe),
intel_de_read(display, FDI_RX_IIR(pipe)));
}
if (pch_iir & SDE_ERROR_CPT)
- cpt_serr_int_handler(dev_priv);
+ cpt_serr_int_handler(display);
}
static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe)
@@ -910,23 +892,23 @@ void ilk_display_irq_handler(struct intel_display *display, u32 de_iir)
intel_opregion_asle_intr(display);
if (de_iir & DE_POISON)
- drm_err(&dev_priv->drm, "Poison interrupt\n");
+ drm_err(display->drm, "Poison interrupt\n");
if (de_iir & DE_GTT_FAULT)
ilk_gtt_fault_irq_handler(display);
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
if (de_iir & DE_PIPE_VBLANK(pipe))
- intel_handle_vblank(dev_priv, pipe);
+ intel_handle_vblank(display, pipe);
if (de_iir & DE_PLANE_FLIP_DONE(pipe))
- flip_done_handler(dev_priv, pipe);
+ flip_done_handler(display, pipe);
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
intel_cpu_fifo_underrun_irq_handler(display, pipe);
if (de_iir & DE_PIPE_CRC_DONE(pipe))
- i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+ i9xx_pipe_crc_irq_handler(display, pipe);
}
/* check event from PCH */
@@ -934,15 +916,15 @@ void ilk_display_irq_handler(struct intel_display *display, u32 de_iir)
u32 pch_iir = intel_de_read(display, SDEIIR);
if (HAS_PCH_CPT(dev_priv))
- cpt_irq_handler(dev_priv, pch_iir);
+ cpt_irq_handler(display, pch_iir);
else
- ibx_irq_handler(dev_priv, pch_iir);
+ ibx_irq_handler(display, pch_iir);
/* should clear PCH hotplug event before clear CPU irq */
intel_de_write(display, SDEIIR, pch_iir);
}
- if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
+ if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT)
gen5_rps_irq_handler(&to_gt(dev_priv)->rps);
}
@@ -956,12 +938,12 @@ void ivb_display_irq_handler(struct intel_display *display, u32 de_iir)
ilk_hpd_irq_handler(display, hotplug_trigger);
if (de_iir & DE_ERR_INT_IVB)
- ivb_err_int_handler(dev_priv);
+ ivb_err_int_handler(display);
if (de_iir & DE_EDP_PSR_INT_HSW) {
struct intel_encoder *encoder;
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(display->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
u32 psr_iir;
@@ -977,35 +959,35 @@ void ivb_display_irq_handler(struct intel_display *display, u32 de_iir)
if (de_iir & DE_GSE_IVB)
intel_opregion_asle_intr(display);
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
- intel_handle_vblank(dev_priv, pipe);
+ intel_handle_vblank(display, pipe);
if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
- flip_done_handler(dev_priv, pipe);
+ flip_done_handler(display, pipe);
}
/* check event from PCH */
if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
u32 pch_iir = intel_de_read(display, SDEIIR);
- cpt_irq_handler(dev_priv, pch_iir);
+ cpt_irq_handler(display, pch_iir);
/* clear PCH hotplug event before clear CPU irq */
intel_de_write(display, SDEIIR, pch_iir);
}
}
-static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
+static u32 gen8_de_port_aux_mask(struct intel_display *display)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 20)
+ if (DISPLAY_VER(display) >= 20)
return 0;
- else if (DISPLAY_VER(dev_priv) >= 14)
+ else if (DISPLAY_VER(display) >= 14)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB;
- else if (DISPLAY_VER(dev_priv) >= 13)
+ else if (DISPLAY_VER(display) >= 13)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
@@ -1015,7 +997,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
TGL_DE_PORT_AUX_USBC2 |
TGL_DE_PORT_AUX_USBC3 |
TGL_DE_PORT_AUX_USBC4;
- else if (DISPLAY_VER(dev_priv) >= 12)
+ else if (DISPLAY_VER(display) >= 12)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
@@ -1027,12 +1009,12 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
TGL_DE_PORT_AUX_USBC6;
mask = GEN8_AUX_CHANNEL_A;
- if (DISPLAY_VER(dev_priv) >= 9)
+ if (DISPLAY_VER(display) >= 9)
mask |= GEN9_AUX_CHANNEL_B |
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (DISPLAY_VER(dev_priv) == 11) {
+ if (DISPLAY_VER(display) == 11) {
mask |= ICL_AUX_CHANNEL_F;
mask |= ICL_AUX_CHANNEL_E;
}
@@ -1040,10 +1022,8 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
return mask;
}
-static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
+static u32 gen8_de_pipe_fault_mask(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
if (DISPLAY_VER(display) >= 14)
return MTL_PIPEDMC_ATS_FAULT |
MTL_PLANE_ATS_FAULT |
@@ -1195,15 +1175,14 @@ gen8_pipe_fault_handlers(struct intel_display *display)
return bdw_pipe_fault_handlers;
}
-static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
+static void intel_pmdemand_irq_handler(struct intel_display *display)
{
- wake_up_all(&dev_priv->display.pmdemand.waitqueue);
+ wake_up_all(&display->pmdemand.waitqueue);
}
static void
-gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
+gen8_de_misc_irq_handler(struct intel_display *display, u32 iir)
{
- struct intel_display *display = &dev_priv->display;
bool found = false;
if (HAS_DBUF_OVERLAP_DETECTION(display)) {
@@ -1213,20 +1192,20 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
}
}
- if (DISPLAY_VER(dev_priv) >= 14) {
+ if (DISPLAY_VER(display) >= 14) {
if (iir & (XELPDP_PMDEMAND_RSP |
XELPDP_PMDEMAND_RSPTOUT_ERR)) {
if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"Error waiting for Punit PM Demand Response\n");
- intel_pmdemand_irq_handler(dev_priv);
+ intel_pmdemand_irq_handler(display);
found = true;
}
if (iir & XELPDP_RM_TIMEOUT) {
u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);
- drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n", val);
+ drm_warn(display->drm, "Register Access Timeout = 0x%x\n", val);
found = true;
}
} else if (iir & GEN8_DE_MISC_GSE) {
@@ -1239,12 +1218,12 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
u32 psr_iir;
i915_reg_t iir_reg;
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(display->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- if (DISPLAY_VER(dev_priv) >= 12)
- iir_reg = TRANS_PSR_IIR(dev_priv,
- intel_dp->psr.transcoder);
+ if (DISPLAY_VER(display) >= 12)
+ iir_reg = TRANS_PSR_IIR(display,
+ intel_dp->psr.transcoder);
else
iir_reg = EDP_PSR_IIR;
@@ -1256,19 +1235,18 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
intel_psr_irq_handler(intel_dp, psr_iir);
/* prior GEN12 only have one EDP PSR */
- if (DISPLAY_VER(dev_priv) < 12)
+ if (DISPLAY_VER(display) < 12)
break;
}
}
if (!found)
- drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);
+ drm_err(display->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);
}
-static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+static void gen11_dsi_te_interrupt_handler(struct intel_display *display,
u32 te_trigger)
{
- struct intel_display *display = &dev_priv->display;
enum pipe pipe = INVALID_PIPE;
enum transcoder dsi_trans;
enum port port;
@@ -1278,7 +1256,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
* Incase of dual link, TE comes from DSI_1
* this is to check if dual link is enabled
*/
- val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0));
+ val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0));
val &= PORT_SYNC_MODE_ENABLE;
/*
@@ -1294,12 +1272,12 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
val = val & OP_MODE_MASK;
if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
- drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
+ drm_err(display->drm, "DSI trancoder not configured in command mode\n");
return;
}
/* Get PIPE for handling VBLANK event */
- val = intel_de_read(display, TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
+ val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));
switch (val & TRANS_DDI_EDP_INPUT_MASK) {
case TRANS_DDI_EDP_INPUT_A_ON:
pipe = PIPE_A;
@@ -1311,28 +1289,28 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
pipe = PIPE_C;
break;
default:
- drm_err(&dev_priv->drm, "Invalid PIPE\n");
+ drm_err(display->drm, "Invalid PIPE\n");
return;
}
- intel_handle_vblank(dev_priv, pipe);
+ intel_handle_vblank(display, pipe);
/* clear TE in dsi IIR */
port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0);
}
-static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
+static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display)
{
- if (DISPLAY_VER(i915) >= 9)
+ if (DISPLAY_VER(display) >= 9)
return GEN9_PIPE_PLANE1_FLIP_DONE;
else
return GEN8_PIPE_PRIMARY_FLIP_DONE;
}
-static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir)
+static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_iir, u32 *pica_iir)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 pica_ier = 0;
*pica_iir = 0;
@@ -1346,7 +1324,7 @@ static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_i
* their flags both in the PICA and SDE IIR.
*/
if (*pch_iir & SDE_PICAINTERRUPT) {
- drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL);
+ drm_WARN_ON(display->drm, INTEL_PCH_TYPE(i915) < PCH_MTL);
pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0);
*pica_iir = intel_de_read(display, PICAINTERRUPT_IIR);
@@ -1365,26 +1343,26 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
u32 iir;
enum pipe pipe;
- drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));
+ drm_WARN_ON_ONCE(display->drm, !HAS_DISPLAY(display));
if (master_ctl & GEN8_DE_MISC_IRQ) {
iir = intel_de_read(display, GEN8_DE_MISC_IIR);
if (iir) {
intel_de_write(display, GEN8_DE_MISC_IIR, iir);
- gen8_de_misc_irq_handler(dev_priv, iir);
+ gen8_de_misc_irq_handler(display, iir);
} else {
- drm_err_ratelimited(&dev_priv->drm,
+ drm_err_ratelimited(display->drm,
"The master control interrupt lied (DE MISC)!\n");
}
}
- if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
+ if (DISPLAY_VER(display) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
iir = intel_de_read(display, GEN11_DE_HPD_IIR);
if (iir) {
intel_de_write(display, GEN11_DE_HPD_IIR, iir);
gen11_hpd_irq_handler(display, iir);
} else {
- drm_err_ratelimited(&dev_priv->drm,
+ drm_err_ratelimited(display->drm,
"The master control interrupt lied, (DE HPD)!\n");
}
}
@@ -1396,19 +1374,19 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
intel_de_write(display, GEN8_DE_PORT_IIR, iir);
- if (iir & gen8_de_port_aux_mask(dev_priv)) {
+ if (iir & gen8_de_port_aux_mask(display)) {
intel_dp_aux_irq_handler(display);
found = true;
}
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
+ if (display->platform.geminilake || display->platform.broxton) {
u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
if (hotplug_trigger) {
bxt_hpd_irq_handler(display, hotplug_trigger);
found = true;
}
- } else if (IS_BROADWELL(dev_priv)) {
+ } else if (display->platform.broadwell) {
u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
if (hotplug_trigger) {
@@ -1417,31 +1395,31 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
}
}
- if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
+ if ((display->platform.geminilake || display->platform.broxton) &&
(iir & BXT_DE_PORT_GMBUS)) {
intel_gmbus_irq_handler(display);
found = true;
}
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(display) >= 11) {
u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
if (te_trigger) {
- gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
+ gen11_dsi_te_interrupt_handler(display, te_trigger);
found = true;
}
}
if (!found)
- drm_err_ratelimited(&dev_priv->drm,
+ drm_err_ratelimited(display->drm,
"Unexpected DE Port interrupt\n");
} else {
- drm_err_ratelimited(&dev_priv->drm,
+ drm_err_ratelimited(display->drm,
"The master control interrupt lied (DE PORT)!\n");
}
}
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
u32 fault_errors;
if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
@@ -1449,7 +1427,7 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));
if (!iir) {
- drm_err_ratelimited(&dev_priv->drm,
+ drm_err_ratelimited(display->drm,
"The master control interrupt lied (DE PIPE)!\n");
continue;
}
@@ -1457,29 +1435,29 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir);
if (iir & GEN8_PIPE_VBLANK)
- intel_handle_vblank(dev_priv, pipe);
+ intel_handle_vblank(display, pipe);
- if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
- flip_done_handler(dev_priv, pipe);
+ if (iir & gen8_de_pipe_flip_done_mask(display))
+ flip_done_handler(display, pipe);
- if (HAS_DSB(dev_priv)) {
+ if (HAS_DSB(display)) {
if (iir & GEN12_DSB_INT(INTEL_DSB_0))
- intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0);
+ intel_dsb_irq_handler(display, pipe, INTEL_DSB_0);
if (iir & GEN12_DSB_INT(INTEL_DSB_1))
- intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1);
+ intel_dsb_irq_handler(display, pipe, INTEL_DSB_1);
if (iir & GEN12_DSB_INT(INTEL_DSB_2))
- intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2);
+ intel_dsb_irq_handler(display, pipe, INTEL_DSB_2);
}
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
- hsw_pipe_crc_irq_handler(dev_priv, pipe);
+ hsw_pipe_crc_irq_handler(display, pipe);
if (iir & GEN8_PIPE_FIFO_UNDERRUN)
intel_cpu_fifo_underrun_irq_handler(display, pipe);
- fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
+ fault_errors = iir & gen8_de_pipe_fault_mask(display);
if (fault_errors)
intel_pipe_fault_irq_handler(display,
gen8_pipe_fault_handlers(display),
@@ -1495,7 +1473,7 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
* scheme also closed the SDE interrupt handling race we've seen
* on older pch-split platforms. But this needs testing.
*/
- gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir);
+ gen8_read_and_ack_pch_irqs(display, &iir, &pica_iir);
if (iir) {
if (pica_iir)
xelpdp_pica_irq_handler(display, pica_iir);
@@ -1505,13 +1483,13 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
spt_irq_handler(display, iir);
else
- cpt_irq_handler(dev_priv, iir);
+ cpt_irq_handler(display, iir);
} else {
/*
* Like on previous PCH there seems to be something
* fishy going on with forwarding PCH interrupts.
*/
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"The master control interrupt lied (SDE)!\n");
}
}
@@ -1556,10 +1534,9 @@ void gen11_display_irq_handler(struct intel_display *display)
enable_rpm_wakeref_asserts(&i915->runtime_pm);
}
-static void i915gm_irq_cstate_wa_enable(struct drm_i915_private *i915)
+static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
- lockdep_assert_held(&i915->drm.vblank_time_lock);
+ lockdep_assert_held(&display->drm->vblank_time_lock);
/*
* Vblank/CRC interrupts fail to wake the device up from C2+.
@@ -1567,33 +1544,30 @@ static void i915gm_irq_cstate_wa_enable(struct drm_i915_private *i915)
* the problem. There is a small power cost so we do this
* only when vblank/CRC interrupts are actually enabled.
*/
- if (i915->display.irq.vblank_enabled++ == 0)
+ if (display->irq.vblank_enabled++ == 0)
intel_de_write(display, SCPD0,
_MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
}
-static void i915gm_irq_cstate_wa_disable(struct drm_i915_private *i915)
+static void i915gm_irq_cstate_wa_disable(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
- lockdep_assert_held(&i915->drm.vblank_time_lock);
+ lockdep_assert_held(&display->drm->vblank_time_lock);
- if (--i915->display.irq.vblank_enabled == 0)
+ if (--display->irq.vblank_enabled == 0)
intel_de_write(display, SCPD0,
_MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
}
void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
- spin_lock_irq(&i915->drm.vblank_time_lock);
+ spin_lock_irq(&display->drm->vblank_time_lock);
if (enable)
- i915gm_irq_cstate_wa_enable(i915);
+ i915gm_irq_cstate_wa_enable(display);
else
- i915gm_irq_cstate_wa_disable(i915);
+ i915gm_irq_cstate_wa_disable(display);
- spin_unlock_irq(&i915->drm.vblank_time_lock);
+ spin_unlock_irq(&display->drm->vblank_time_lock);
}
int i8xx_enable_vblank(struct drm_crtc *crtc)
@@ -1624,20 +1598,20 @@ void i8xx_disable_vblank(struct drm_crtc *crtc)
int i915gm_enable_vblank(struct drm_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc->dev);
+ struct intel_display *display = to_intel_display(crtc->dev);
- i915gm_irq_cstate_wa_enable(i915);
+ i915gm_irq_cstate_wa_enable(display);
return i8xx_enable_vblank(crtc);
}
void i915gm_disable_vblank(struct drm_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc->dev);
+ struct intel_display *display = to_intel_display(crtc->dev);
i8xx_disable_vblank(crtc);
- i915gm_irq_cstate_wa_disable(i915);
+ i915gm_irq_cstate_wa_disable(display);
}
int i965_enable_vblank(struct drm_crtc *crtc)
@@ -1674,7 +1648,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
- u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
+ u32 bit = DISPLAY_VER(display) >= 7 ?
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -1684,7 +1658,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
/* Even though there is no DMC, frame counter can get stuck when
* PSR is active as no frames are generated.
*/
- if (HAS_PSR(dev_priv))
+ if (HAS_PSR(display))
drm_crtc_vblank_restore(crtc);
return 0;
@@ -1696,7 +1670,7 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
- u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
+ u32 bit = DISPLAY_VER(display) >= 7 ?
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -1764,7 +1738,7 @@ int bdw_enable_vblank(struct drm_crtc *_crtc)
/* Even if there is no DMC, frame counter can get stuck when
* PSR is active as no frames are generated, so check only for PSR.
*/
- if (HAS_PSR(dev_priv))
+ if (HAS_PSR(display))
drm_crtc_vblank_restore(&crtc->base);
return 0;
@@ -1897,11 +1871,11 @@ void vlv_display_error_irq_handler(struct intel_display *display,
vlv_page_table_error_irq_handler(display, dpinvgtt);
}
-static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)
+static void _vlv_display_irq_reset(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
- if (IS_CHERRYVIEW(dev_priv))
+ if (display->platform.cherryview)
intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
else
intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
@@ -1910,9 +1884,9 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)
VLV_ERROR_REGS);
i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0);
- intel_de_rmw(display, PORT_HOTPLUG_STAT(dev_priv), 0, 0);
+ intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
- i9xx_pipestat_irq_reset(dev_priv);
+ i9xx_pipestat_irq_reset(display);
intel_display_irq_regs_reset(display, VLV_IRQ_REGS);
dev_priv->irq_mask = ~0u;
@@ -1920,22 +1894,18 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)
void vlv_display_irq_reset(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
- if (dev_priv->display.irq.vlv_display_irqs_enabled)
- _vlv_display_irq_reset(dev_priv);
+ if (display->irq.vlv_display_irqs_enabled)
+ _vlv_display_irq_reset(display);
}
void i9xx_display_irq_reset(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
- if (I915_HAS_HOTPLUG(i915)) {
+ if (I915_HAS_HOTPLUG(display)) {
i915_hotplug_interrupt_update(display, 0xffffffff, 0);
- intel_de_rmw(display, PORT_HOTPLUG_STAT(i915), 0, 0);
+ intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
}
- i9xx_pipestat_irq_reset(i915);
+ i9xx_pipestat_irq_reset(display);
}
static u32 vlv_error_mask(void)
@@ -1951,10 +1921,10 @@ void vlv_display_irq_postinstall(struct intel_display *display)
u32 enable_mask;
enum pipe pipe;
- if (!dev_priv->display.irq.vlv_display_irqs_enabled)
+ if (!display->irq.vlv_display_irqs_enabled)
return;
- if (IS_CHERRYVIEW(dev_priv))
+ if (display->platform.cherryview)
intel_de_write(display, DPINVGTT,
DPINVGTT_STATUS_MASK_CHV |
DPINVGTT_EN_MASK_CHV);
@@ -1969,7 +1939,7 @@ void vlv_display_irq_postinstall(struct intel_display *display)
pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
- for_each_pipe(dev_priv, pipe)
+ for_each_pipe(display, pipe)
i915_enable_pipestat(display, pipe, pipestat_mask);
enable_mask = I915_DISPLAY_PORT_INTERRUPT |
@@ -1979,11 +1949,11 @@ void vlv_display_irq_postinstall(struct intel_display *display)
I915_LPE_PIPE_B_INTERRUPT |
I915_MASTER_ERROR_INTERRUPT;
- if (IS_CHERRYVIEW(dev_priv))
+ if (display->platform.cherryview)
enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
I915_LPE_PIPE_C_INTERRUPT;
- drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
+ drm_WARN_ON(display->drm, dev_priv->irq_mask != ~0u);
dev_priv->irq_mask = ~enable_mask;
@@ -1992,16 +1962,15 @@ void vlv_display_irq_postinstall(struct intel_display *display)
void gen8_display_irq_reset(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
- for_each_pipe(dev_priv, pipe)
+ for_each_pipe(display, pipe)
if (intel_display_power_is_enabled(display,
POWER_DOMAIN_PIPE(pipe)))
intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
@@ -2017,15 +1986,15 @@ void gen11_display_irq_reset(struct intel_display *display)
u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
enum transcoder trans;
- for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
+ for_each_cpu_transcoder_masked(display, trans, trans_mask) {
enum intel_display_power_domain domain;
domain = POWER_DOMAIN_TRANSCODER(trans);
@@ -2033,10 +2002,10 @@ void gen11_display_irq_reset(struct intel_display *display)
continue;
intel_de_write(display,
- TRANS_PSR_IMR(dev_priv, trans),
+ TRANS_PSR_IMR(display, trans),
0xffffffff);
intel_de_write(display,
- TRANS_PSR_IIR(dev_priv, trans),
+ TRANS_PSR_IIR(display, trans),
0xffffffff);
}
} else {
@@ -2044,7 +2013,7 @@ void gen11_display_irq_reset(struct intel_display *display)
intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
}
- for_each_pipe(dev_priv, pipe)
+ for_each_pipe(display, pipe)
if (intel_display_power_is_enabled(display,
POWER_DOMAIN_PIPE(pipe)))
intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
@@ -2052,7 +2021,7 @@ void gen11_display_irq_reset(struct intel_display *display)
intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS);
intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(display) >= 14)
intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS);
else
intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS);
@@ -2066,7 +2035,7 @@ void gen8_irq_power_well_post_enable(struct intel_display *display,
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
- gen8_de_pipe_flip_done_mask(dev_priv);
+ gen8_de_pipe_flip_done_mask(display);
enum pipe pipe;
spin_lock_irq(&dev_priv->irq_lock);
@@ -2076,10 +2045,10 @@ void gen8_irq_power_well_post_enable(struct intel_display *display,
return;
}
- for_each_pipe_masked(dev_priv, pipe, pipe_mask)
+ for_each_pipe_masked(display, pipe, pipe_mask)
intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
- dev_priv->display.irq.de_irq_mask[pipe],
- ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier);
+ display->irq.de_irq_mask[pipe],
+ ~display->irq.de_irq_mask[pipe] | extra_ier);
spin_unlock_irq(&dev_priv->irq_lock);
}
@@ -2097,7 +2066,7 @@ void gen8_irq_power_well_pre_disable(struct intel_display *display,
return;
}
- for_each_pipe_masked(dev_priv, pipe, pipe_mask)
+ for_each_pipe_masked(display, pipe, pipe_mask)
intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
spin_unlock_irq(&dev_priv->irq_lock);
@@ -2117,9 +2086,9 @@ void gen8_irq_power_well_pre_disable(struct intel_display *display,
* to avoid races with the irq handler, assuming we have MSI. Shared legacy
* interrupts could still race.
*/
-static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
+static void ibx_irq_postinstall(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 mask;
if (HAS_PCH_NOP(dev_priv))
@@ -2141,13 +2110,13 @@ void valleyview_enable_display_irqs(struct intel_display *display)
lockdep_assert_held(&dev_priv->irq_lock);
- if (dev_priv->display.irq.vlv_display_irqs_enabled)
+ if (display->irq.vlv_display_irqs_enabled)
return;
- dev_priv->display.irq.vlv_display_irqs_enabled = true;
+ display->irq.vlv_display_irqs_enabled = true;
if (intel_irqs_enabled(dev_priv)) {
- _vlv_display_irq_reset(dev_priv);
+ _vlv_display_irq_reset(display);
vlv_display_irq_postinstall(display);
}
}
@@ -2158,13 +2127,13 @@ void valleyview_disable_display_irqs(struct intel_display *display)
lockdep_assert_held(&dev_priv->irq_lock);
- if (!dev_priv->display.irq.vlv_display_irqs_enabled)
+ if (!display->irq.vlv_display_irqs_enabled)
return;
- dev_priv->display.irq.vlv_display_irqs_enabled = false;
+ display->irq.vlv_display_irqs_enabled = false;
if (intel_irqs_enabled(dev_priv))
- _vlv_display_irq_reset(dev_priv);
+ _vlv_display_irq_reset(display);
}
void ilk_de_irq_postinstall(struct intel_display *display)
@@ -2173,7 +2142,7 @@ void ilk_de_irq_postinstall(struct intel_display *display)
u32 display_mask, extra_mask;
- if (DISPLAY_VER(i915) >= 7) {
+ if (DISPLAY_VER(display) >= 7) {
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
@@ -2194,59 +2163,59 @@ void ilk_de_irq_postinstall(struct intel_display *display)
DE_DP_A_HOTPLUG);
}
- if (IS_HASWELL(i915)) {
+ if (display->platform.haswell) {
intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR);
display_mask |= DE_EDP_PSR_INT_HSW;
}
- if (IS_IRONLAKE_M(i915))
+ if (display->platform.ironlake && display->platform.mobile)
extra_mask |= DE_PCU_EVENT;
i915->irq_mask = ~display_mask;
- ibx_irq_postinstall(i915);
+ ibx_irq_postinstall(display);
intel_display_irq_regs_init(display, DE_IRQ_REGS, i915->irq_mask,
display_mask | extra_mask);
}
-static void mtp_irq_postinstall(struct drm_i915_private *i915);
-static void icp_irq_postinstall(struct drm_i915_private *i915);
+static void mtp_irq_postinstall(struct intel_display *display);
+static void icp_irq_postinstall(struct intel_display *display);
void gen8_de_irq_postinstall(struct intel_display *display)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
- u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
+ u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
GEN8_PIPE_CDCLK_CRC_DONE;
u32 de_pipe_enables;
- u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
+ u32 de_port_masked = gen8_de_port_aux_mask(display);
u32 de_port_enables;
u32 de_misc_masked = GEN8_DE_EDP_PSR;
u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
enum pipe pipe;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
- if (DISPLAY_VER(dev_priv) >= 14)
- mtp_irq_postinstall(dev_priv);
+ if (DISPLAY_VER(display) >= 14)
+ mtp_irq_postinstall(display);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- icp_irq_postinstall(dev_priv);
+ icp_irq_postinstall(display);
else if (HAS_PCH_SPLIT(dev_priv))
- ibx_irq_postinstall(dev_priv);
+ ibx_irq_postinstall(display);
- if (DISPLAY_VER(dev_priv) < 11)
+ if (DISPLAY_VER(display) < 11)
de_misc_masked |= GEN8_DE_MISC_GSE;
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+ if (display->platform.geminilake || display->platform.broxton)
de_port_masked |= BXT_DE_PORT_GMBUS;
- if (DISPLAY_VER(dev_priv) >= 14) {
+ if (DISPLAY_VER(display) >= 14) {
de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
XELPDP_PMDEMAND_RSP | XELPDP_RM_TIMEOUT;
- } else if (DISPLAY_VER(dev_priv) >= 11) {
+ } else if (DISPLAY_VER(display) >= 11) {
enum port port;
if (intel_bios_is_dsi_present(display, &port))
@@ -2256,25 +2225,25 @@ void gen8_de_irq_postinstall(struct intel_display *display)
if (HAS_DBUF_OVERLAP_DETECTION(display))
de_misc_masked |= XE2LPD_DBUF_OVERLAP_DETECTED;
- if (HAS_DSB(dev_priv))
+ if (HAS_DSB(display))
de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) |
GEN12_DSB_INT(INTEL_DSB_1) |
GEN12_DSB_INT(INTEL_DSB_2);
de_pipe_enables = de_pipe_masked |
GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
- gen8_de_pipe_flip_done_mask(dev_priv);
+ gen8_de_pipe_flip_done_mask(display);
de_port_enables = de_port_masked;
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+ if (display->platform.geminilake || display->platform.broxton)
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
- else if (IS_BROADWELL(dev_priv))
+ else if (display->platform.broadwell)
de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
enum transcoder trans;
- for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
+ for_each_cpu_transcoder_masked(display, trans, trans_mask) {
enum intel_display_power_domain domain;
domain = POWER_DOMAIN_TRANSCODER(trans);
@@ -2282,19 +2251,19 @@ void gen8_de_irq_postinstall(struct intel_display *display)
continue;
intel_display_irq_regs_assert_irr_is_zero(display,
- TRANS_PSR_IIR(dev_priv, trans));
+ TRANS_PSR_IIR(display, trans));
}
} else {
intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR);
}
- for_each_pipe(dev_priv, pipe) {
- dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked;
+ for_each_pipe(display, pipe) {
+ display->irq.de_irq_mask[pipe] = ~de_pipe_masked;
if (intel_display_power_is_enabled(display,
POWER_DOMAIN_PIPE(pipe)))
intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
- dev_priv->display.irq.de_irq_mask[pipe],
+ display->irq.de_irq_mask[pipe],
de_pipe_enables);
}
@@ -2303,7 +2272,7 @@ void gen8_de_irq_postinstall(struct intel_display *display)
intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked,
de_misc_masked);
- if (IS_DISPLAY_VER(dev_priv, 11, 13)) {
+ if (IS_DISPLAY_VER(display, 11, 13)) {
u32 de_hpd_masked = 0;
u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
GEN11_DE_TBT_HOTPLUG_MASK;
@@ -2313,9 +2282,8 @@ void gen8_de_irq_postinstall(struct intel_display *display)
}
}
-static void mtp_irq_postinstall(struct drm_i915_private *i915)
+static void mtp_irq_postinstall(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT;
u32 de_hpd_mask = XELPDP_AUX_TC_MASK;
u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK |
@@ -2327,9 +2295,8 @@ static void mtp_irq_postinstall(struct drm_i915_private *i915)
intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+static void icp_irq_postinstall(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
u32 mask = SDE_GMBUS_ICP;
intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* RE: [PATCH 8/9] drm/i915/irq: convert rest of intel_display_irq.[ch] to struct intel_display
2025-03-11 18:00 ` [PATCH 8/9] drm/i915/irq: convert rest of intel_display_irq.[ch] " Jani Nikula
@ 2025-03-12 5:53 ` Shankar, Uma
0 siblings, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 5:53 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 8/9] drm/i915/irq: convert rest of intel_display_irq.[ch] to struct
> intel_display
>
> Going forward, struct intel_display is the main display device data
> pointer. Convert as much as possible of intel_display_irq.[ch] to struct
> intel_display.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_irq.c | 527 ++++++++----------
> 1 file changed, 247 insertions(+), 280 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 68f903c35978..6f78fe6de06a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -115,9 +115,8 @@ static void intel_pipe_fault_irq_handler(struct
> intel_display *display,
> }
>
> static void
> -intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
> +intel_handle_vblank(struct intel_display *display, enum pipe pipe)
> {
> - struct intel_display *display = &dev_priv->display;
> struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
>
> drm_crtc_handle_vblank(&crtc->base);
> @@ -136,14 +135,14 @@ void ilk_update_display_irq(struct intel_display
> *display,
> u32 new_val;
>
> lockdep_assert_held(&dev_priv->irq_lock);
> - drm_WARN_ON(&dev_priv->drm, enabled_irq_mask &
> ~interrupt_mask);
> + drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
>
> new_val = dev_priv->irq_mask;
> new_val &= ~interrupt_mask;
> new_val |= (~enabled_irq_mask & interrupt_mask);
>
> if (new_val != dev_priv->irq_mask &&
> - !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
> + !drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) {
> dev_priv->irq_mask = new_val;
> intel_de_write(display, DEIMR, dev_priv->irq_mask);
> intel_de_posting_read(display, DEIMR);
> @@ -175,9 +174,9 @@ void bdw_update_port_irq(struct intel_display *display,
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> - drm_WARN_ON(&dev_priv->drm, enabled_irq_mask &
> ~interrupt_mask);
> + drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
>
> - if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
> + if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))
> return;
>
> old_val = intel_de_read(display, GEN8_DE_PORT_IMR);
> @@ -208,17 +207,17 @@ static void bdw_update_pipe_irq(struct intel_display
> *display,
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> - drm_WARN_ON(&dev_priv->drm, enabled_irq_mask &
> ~interrupt_mask);
> + drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
>
> - if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
> + if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))
> return;
>
> - new_val = dev_priv->display.irq.de_irq_mask[pipe];
> + new_val = display->irq.de_irq_mask[pipe];
> new_val &= ~interrupt_mask;
> new_val |= (~enabled_irq_mask & interrupt_mask);
>
> - if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) {
> - dev_priv->display.irq.de_irq_mask[pipe] = new_val;
> + if (new_val != display->irq.de_irq_mask[pipe]) {
> + display->irq.de_irq_mask[pipe] = new_val;
> intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display-
> >irq.de_irq_mask[pipe]);
> intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));
> }
> @@ -252,11 +251,11 @@ void ibx_display_interrupt_update(struct intel_display
> *display,
> sdeimr &= ~interrupt_mask;
> sdeimr |= (~enabled_irq_mask & interrupt_mask);
>
> - drm_WARN_ON(&dev_priv->drm, enabled_irq_mask &
> ~interrupt_mask);
> + drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> - if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
> + if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))
> return;
>
> intel_de_write(display, SDEIMR, sdeimr);
> @@ -322,20 +321,20 @@ void i915_enable_pipestat(struct intel_display
> *display,
> enum pipe pipe, u32 status_mask)
> {
> struct drm_i915_private *dev_priv = to_i915(display->drm);
> - i915_reg_t reg = PIPESTAT(dev_priv, pipe);
> + i915_reg_t reg = PIPESTAT(display, pipe);
> u32 enable_mask;
>
> - drm_WARN_ONCE(&dev_priv->drm, status_mask &
> ~PIPESTAT_INT_STATUS_MASK,
> + drm_WARN_ONCE(display->drm, status_mask &
> ~PIPESTAT_INT_STATUS_MASK,
> "pipe %c: status_mask=0x%x\n",
> pipe_name(pipe), status_mask);
>
> lockdep_assert_held(&dev_priv->irq_lock);
> - drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
> + drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv));
>
> - if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) ==
> status_mask)
> + if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)
> return;
>
> - dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask;
> + display->irq.pipestat_irq_mask[pipe] |= status_mask;
> enable_mask = i915_pipestat_enable_mask(display, pipe);
>
> intel_de_write(display, reg, enable_mask | status_mask);
> @@ -346,20 +345,20 @@ void i915_disable_pipestat(struct intel_display
> *display,
> enum pipe pipe, u32 status_mask)
> {
> struct drm_i915_private *dev_priv = to_i915(display->drm);
> - i915_reg_t reg = PIPESTAT(dev_priv, pipe);
> + i915_reg_t reg = PIPESTAT(display, pipe);
> u32 enable_mask;
>
> - drm_WARN_ONCE(&dev_priv->drm, status_mask &
> ~PIPESTAT_INT_STATUS_MASK,
> + drm_WARN_ONCE(display->drm, status_mask &
> ~PIPESTAT_INT_STATUS_MASK,
> "pipe %c: status_mask=0x%x\n",
> pipe_name(pipe), status_mask);
>
> lockdep_assert_held(&dev_priv->irq_lock);
> - drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
> + drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv));
>
> - if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0)
> + if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0)
> return;
>
> - dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask;
> + display->irq.pipestat_irq_mask[pipe] &= ~status_mask;
> enable_mask = i915_pipestat_enable_mask(display, pipe);
>
> intel_de_write(display, reg, enable_mask | status_mask);
> @@ -368,15 +367,13 @@ void i915_disable_pipestat(struct intel_display
> *display,
>
> static bool i915_has_legacy_blc_interrupt(struct intel_display *display)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> -
> - if (IS_I85X(i915))
> + if (display->platform.i85x)
> return true;
>
> - if (IS_PINEVIEW(i915))
> + if (display->platform.pineview)
> return true;
>
> - return IS_DISPLAY_VER(display, 3, 4) && IS_MOBILE(i915);
> + return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile;
> }
>
> /**
> @@ -396,7 +393,7 @@ void i915_enable_asle_pipestat(struct intel_display
> *display)
> spin_lock_irq(&dev_priv->irq_lock);
>
> i915_enable_pipestat(display, PIPE_B,
> PIPE_LEGACY_BLC_EVENT_STATUS);
> - if (DISPLAY_VER(dev_priv) >= 4)
> + if (DISPLAY_VER(display) >= 4)
> i915_enable_pipestat(display, PIPE_A,
> PIPE_LEGACY_BLC_EVENT_STATUS);
>
> @@ -404,13 +401,12 @@ void i915_enable_asle_pipestat(struct intel_display
> *display)
> }
>
> #if IS_ENABLED(CONFIG_DEBUG_FS)
> -static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> +static void display_pipe_crc_irq_handler(struct intel_display *display,
> enum pipe pipe,
> u32 crc0, u32 crc1,
> u32 crc2, u32 crc3,
> u32 crc4)
> {
> - struct intel_display *display = &dev_priv->display;
> struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
> struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
> u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
> @@ -427,7 +423,7 @@ static void display_pipe_crc_irq_handler(struct
> drm_i915_private *dev_priv,
> * don't trust that one either.
> */
> if (pipe_crc->skipped <= 0 ||
> - (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
> + (DISPLAY_VER(display) >= 8 && pipe_crc->skipped == 1)) {
> pipe_crc->skipped++;
> spin_unlock(&pipe_crc->lock);
> return;
> @@ -440,20 +436,19 @@ static void display_pipe_crc_irq_handler(struct
> drm_i915_private *dev_priv,
> }
> #else
> static inline void
> -display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> +display_pipe_crc_irq_handler(struct intel_display *display,
> enum pipe pipe,
> u32 crc0, u32 crc1,
> u32 crc2, u32 crc3,
> u32 crc4) {}
> #endif
>
> -static void flip_done_handler(struct drm_i915_private *i915,
> +static void flip_done_handler(struct intel_display *display,
> enum pipe pipe)
> {
> - struct intel_display *display = &i915->display;
> struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
>
> - spin_lock(&i915->drm.event_lock);
> + spin_lock(&display->drm->event_lock);
>
> if (crtc->flip_done_event) {
> trace_intel_crtc_flip_done(crtc);
> @@ -461,25 +456,21 @@ static void flip_done_handler(struct drm_i915_private
> *i915,
> crtc->flip_done_event = NULL;
> }
>
> - spin_unlock(&i915->drm.event_lock);
> + spin_unlock(&display->drm->event_lock);
> }
>
> -static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> +static void hsw_pipe_crc_irq_handler(struct intel_display *display,
> enum pipe pipe)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> - display_pipe_crc_irq_handler(dev_priv, pipe,
> + display_pipe_crc_irq_handler(display, pipe,
> intel_de_read(display,
> PIPE_CRC_RES_HSW(pipe)),
> 0, 0, 0, 0);
> }
>
> -static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> +static void ivb_pipe_crc_irq_handler(struct intel_display *display,
> enum pipe pipe)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> - display_pipe_crc_irq_handler(dev_priv, pipe,
> + display_pipe_crc_irq_handler(display, pipe,
> intel_de_read(display,
> PIPE_CRC_RES_1_IVB(pipe)),
> intel_de_read(display,
> PIPE_CRC_RES_2_IVB(pipe)),
> intel_de_read(display,
> PIPE_CRC_RES_3_IVB(pipe)),
> @@ -487,40 +478,38 @@ static void ivb_pipe_crc_irq_handler(struct
> drm_i915_private *dev_priv,
> intel_de_read(display,
> PIPE_CRC_RES_5_IVB(pipe)));
> }
>
> -static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> +static void i9xx_pipe_crc_irq_handler(struct intel_display *display,
> enum pipe pipe)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 res1, res2;
>
> - if (DISPLAY_VER(dev_priv) >= 3)
> - res1 = intel_de_read(display,
> PIPE_CRC_RES_RES1_I915(dev_priv, pipe));
> + if (DISPLAY_VER(display) >= 3)
> + res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display,
> pipe));
> else
> res1 = 0;
>
> - if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
> - res2 = intel_de_read(display,
> PIPE_CRC_RES_RES2_G4X(dev_priv, pipe));
> + if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
> + res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display,
> pipe));
> else
> res2 = 0;
>
> - display_pipe_crc_irq_handler(dev_priv, pipe,
> - intel_de_read(display,
> PIPE_CRC_RES_RED(dev_priv, pipe)),
> - intel_de_read(display,
> PIPE_CRC_RES_GREEN(dev_priv, pipe)),
> - intel_de_read(display,
> PIPE_CRC_RES_BLUE(dev_priv, pipe)),
> + display_pipe_crc_irq_handler(display, pipe,
> + intel_de_read(display,
> PIPE_CRC_RES_RED(display, pipe)),
> + intel_de_read(display,
> PIPE_CRC_RES_GREEN(display, pipe)),
> + intel_de_read(display,
> PIPE_CRC_RES_BLUE(display, pipe)),
> res1, res2);
> }
>
> -static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
> +static void i9xx_pipestat_irq_reset(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> enum pipe pipe;
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> intel_de_write(display,
> - PIPESTAT(dev_priv, pipe),
> + PIPESTAT(display, pipe),
> PIPESTAT_INT_STATUS_MASK |
> PIPE_FIFO_UNDERRUN_STATUS);
>
> - dev_priv->display.irq.pipestat_irq_mask[pipe] = 0;
> + display->irq.pipestat_irq_mask[pipe] = 0;
> }
> }
>
> @@ -532,13 +521,13 @@ void i9xx_pipestat_irq_ack(struct intel_display
> *display,
>
> spin_lock(&dev_priv->irq_lock);
>
> - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> - !dev_priv->display.irq.vlv_display_irqs_enabled) {
> + if ((display->platform.valleyview || display->platform.cherryview) &&
> + !display->irq.vlv_display_irqs_enabled) {
> spin_unlock(&dev_priv->irq_lock);
> return;
> }
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> i915_reg_t reg;
> u32 status_mask, enable_mask, iir_bit = 0;
>
> @@ -566,12 +555,12 @@ void i9xx_pipestat_irq_ack(struct intel_display
> *display,
> break;
> }
> if (iir & iir_bit)
> - status_mask |= dev_priv-
> >display.irq.pipestat_irq_mask[pipe];
> + status_mask |= display->irq.pipestat_irq_mask[pipe];
>
> if (!status_mask)
> continue;
>
> - reg = PIPESTAT(dev_priv, pipe);
> + reg = PIPESTAT(display, pipe);
> pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;
> enable_mask = i915_pipestat_enable_mask(display, pipe);
>
> @@ -595,19 +584,18 @@ void i9xx_pipestat_irq_ack(struct intel_display
> *display,
> void i915_pipestat_irq_handler(struct intel_display *display,
> u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> bool blc_event = false;
> enum pipe pipe;
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
> - intel_handle_vblank(dev_priv, pipe);
> + intel_handle_vblank(display, pipe);
>
> if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
> blc_event = true;
>
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> - i9xx_pipe_crc_irq_handler(dev_priv, pipe);
> + i9xx_pipe_crc_irq_handler(display, pipe);
>
> if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> intel_cpu_fifo_underrun_irq_handler(display, pipe);
> @@ -620,19 +608,18 @@ void i915_pipestat_irq_handler(struct intel_display
> *display,
> void i965_pipestat_irq_handler(struct intel_display *display,
> u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> bool blc_event = false;
> enum pipe pipe;
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> if (pipe_stats[pipe] &
> PIPE_START_VBLANK_INTERRUPT_STATUS)
> - intel_handle_vblank(dev_priv, pipe);
> + intel_handle_vblank(display, pipe);
>
> if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
> blc_event = true;
>
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> - i9xx_pipe_crc_irq_handler(dev_priv, pipe);
> + i9xx_pipe_crc_irq_handler(display, pipe);
>
> if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> intel_cpu_fifo_underrun_irq_handler(display, pipe);
> @@ -648,18 +635,17 @@ void i965_pipestat_irq_handler(struct intel_display
> *display,
> void valleyview_pipestat_irq_handler(struct intel_display *display,
> u32 pipe_stats[I915_MAX_PIPES])
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> if (pipe_stats[pipe] &
> PIPE_START_VBLANK_INTERRUPT_STATUS)
> - intel_handle_vblank(dev_priv, pipe);
> + intel_handle_vblank(display, pipe);
>
> if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
> - flip_done_handler(dev_priv, pipe);
> + flip_done_handler(display, pipe);
>
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> - i9xx_pipe_crc_irq_handler(dev_priv, pipe);
> + i9xx_pipe_crc_irq_handler(display, pipe);
>
> if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> intel_cpu_fifo_underrun_irq_handler(display, pipe);
> @@ -669,9 +655,8 @@ void valleyview_pipestat_irq_handler(struct intel_display
> *display,
> intel_gmbus_irq_handler(display);
> }
>
> -static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> +static void ibx_irq_handler(struct intel_display *display, u32 pch_iir)
> {
> - struct intel_display *display = &dev_priv->display;
> enum pipe pipe;
> u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
>
> @@ -680,7 +665,7 @@ static void ibx_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> if (pch_iir & SDE_AUDIO_POWER_MASK) {
> int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
> SDE_AUDIO_POWER_SHIFT);
> - drm_dbg(&dev_priv->drm, "PCH audio power change on port
> %d\n",
> + drm_dbg(display->drm, "PCH audio power change on port %d\n",
> port_name(port));
> }
>
> @@ -691,26 +676,26 @@ static void ibx_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> intel_gmbus_irq_handler(display);
>
> if (pch_iir & SDE_AUDIO_HDCP_MASK)
> - drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
> + drm_dbg(display->drm, "PCH HDCP audio interrupt\n");
>
> if (pch_iir & SDE_AUDIO_TRANS_MASK)
> - drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
> + drm_dbg(display->drm, "PCH transcoder audio interrupt\n");
>
> if (pch_iir & SDE_POISON)
> - drm_err(&dev_priv->drm, "PCH poison interrupt\n");
> + drm_err(display->drm, "PCH poison interrupt\n");
>
> if (pch_iir & SDE_FDI_MASK) {
> - for_each_pipe(dev_priv, pipe)
> - drm_dbg(&dev_priv->drm, " pipe %c FDI IIR:
> 0x%08x\n",
> + for_each_pipe(display, pipe)
> + drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",
> pipe_name(pipe),
> intel_de_read(display, FDI_RX_IIR(pipe)));
> }
>
> if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
> - drm_dbg(&dev_priv->drm, "PCH transcoder CRC done
> interrupt\n");
> + drm_dbg(display->drm, "PCH transcoder CRC done interrupt\n");
>
> if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
> - drm_dbg(&dev_priv->drm,
> + drm_dbg(display->drm,
> "PCH transcoder CRC error interrupt\n");
>
> if (pch_iir & SDE_TRANSA_FIFO_UNDER)
> @@ -753,14 +738,13 @@ static const struct pipe_fault_handler
> ivb_pipe_fault_handlers[] = {
> {}
> };
>
> -static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
> +static void ivb_err_int_handler(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 err_int = intel_de_read(display, GEN7_ERR_INT);
> enum pipe pipe;
>
> if (err_int & ERR_INT_POISON)
> - drm_err(&dev_priv->drm, "Poison interrupt\n");
> + drm_err(display->drm, "Poison interrupt\n");
>
> if (err_int & ERR_INT_INVALID_GTT_PTE)
> drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");
> @@ -768,17 +752,17 @@ static void ivb_err_int_handler(struct
> drm_i915_private *dev_priv)
> if (err_int & ERR_INT_INVALID_PTE_DATA)
> drm_err_ratelimited(display->drm, "Invalid PTE data\n");
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> u32 fault_errors;
>
> if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
> intel_cpu_fifo_underrun_irq_handler(display, pipe);
>
> if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
> - if (IS_IVYBRIDGE(dev_priv))
> - ivb_pipe_crc_irq_handler(dev_priv, pipe);
> + if (display->platform.ivybridge)
> + ivb_pipe_crc_irq_handler(display, pipe);
> else
> - hsw_pipe_crc_irq_handler(dev_priv, pipe);
> + hsw_pipe_crc_irq_handler(display, pipe);
> }
>
> fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe);
> @@ -790,25 +774,23 @@ static void ivb_err_int_handler(struct
> drm_i915_private *dev_priv)
> intel_de_write(display, GEN7_ERR_INT, err_int);
> }
>
> -static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
> +static void cpt_serr_int_handler(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 serr_int = intel_de_read(display, SERR_INT);
> enum pipe pipe;
>
> if (serr_int & SERR_INT_POISON)
> - drm_err(&dev_priv->drm, "PCH poison interrupt\n");
> + drm_err(display->drm, "PCH poison interrupt\n");
>
> - for_each_pipe(dev_priv, pipe)
> + for_each_pipe(display, pipe)
> if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
> intel_pch_fifo_underrun_irq_handler(display, pipe);
>
> intel_de_write(display, SERR_INT, serr_int);
> }
>
> -static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> +static void cpt_irq_handler(struct intel_display *display, u32 pch_iir)
> {
> - struct intel_display *display = &dev_priv->display;
> enum pipe pipe;
> u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
>
> @@ -817,7 +799,7 @@ static void cpt_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
> int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
> SDE_AUDIO_POWER_SHIFT_CPT);
> - drm_dbg(&dev_priv->drm, "PCH audio power change on port
> %c\n",
> + drm_dbg(display->drm, "PCH audio power change on port %c\n",
> port_name(port));
> }
>
> @@ -828,20 +810,20 @@ static void cpt_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> intel_gmbus_irq_handler(display);
>
> if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
> - drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
> + drm_dbg(display->drm, "Audio CP request interrupt\n");
>
> if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
> - drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
> + drm_dbg(display->drm, "Audio CP change interrupt\n");
>
> if (pch_iir & SDE_FDI_MASK_CPT) {
> - for_each_pipe(dev_priv, pipe)
> - drm_dbg(&dev_priv->drm, " pipe %c FDI IIR:
> 0x%08x\n",
> + for_each_pipe(display, pipe)
> + drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",
> pipe_name(pipe),
> intel_de_read(display, FDI_RX_IIR(pipe)));
> }
>
> if (pch_iir & SDE_ERROR_CPT)
> - cpt_serr_int_handler(dev_priv);
> + cpt_serr_int_handler(display);
> }
>
> static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe)
> @@ -910,23 +892,23 @@ void ilk_display_irq_handler(struct intel_display
> *display, u32 de_iir)
> intel_opregion_asle_intr(display);
>
> if (de_iir & DE_POISON)
> - drm_err(&dev_priv->drm, "Poison interrupt\n");
> + drm_err(display->drm, "Poison interrupt\n");
>
> if (de_iir & DE_GTT_FAULT)
> ilk_gtt_fault_irq_handler(display);
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> if (de_iir & DE_PIPE_VBLANK(pipe))
> - intel_handle_vblank(dev_priv, pipe);
> + intel_handle_vblank(display, pipe);
>
> if (de_iir & DE_PLANE_FLIP_DONE(pipe))
> - flip_done_handler(dev_priv, pipe);
> + flip_done_handler(display, pipe);
>
> if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
> intel_cpu_fifo_underrun_irq_handler(display, pipe);
>
> if (de_iir & DE_PIPE_CRC_DONE(pipe))
> - i9xx_pipe_crc_irq_handler(dev_priv, pipe);
> + i9xx_pipe_crc_irq_handler(display, pipe);
> }
>
> /* check event from PCH */
> @@ -934,15 +916,15 @@ void ilk_display_irq_handler(struct intel_display
> *display, u32 de_iir)
> u32 pch_iir = intel_de_read(display, SDEIIR);
>
> if (HAS_PCH_CPT(dev_priv))
> - cpt_irq_handler(dev_priv, pch_iir);
> + cpt_irq_handler(display, pch_iir);
> else
> - ibx_irq_handler(dev_priv, pch_iir);
> + ibx_irq_handler(display, pch_iir);
>
> /* should clear PCH hotplug event before clear CPU irq */
> intel_de_write(display, SDEIIR, pch_iir);
> }
>
> - if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
> + if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT)
> gen5_rps_irq_handler(&to_gt(dev_priv)->rps);
> }
>
> @@ -956,12 +938,12 @@ void ivb_display_irq_handler(struct intel_display
> *display, u32 de_iir)
> ilk_hpd_irq_handler(display, hotplug_trigger);
>
> if (de_iir & DE_ERR_INT_IVB)
> - ivb_err_int_handler(dev_priv);
> + ivb_err_int_handler(display);
>
> if (de_iir & DE_EDP_PSR_INT_HSW) {
> struct intel_encoder *encoder;
>
> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + for_each_intel_encoder_with_psr(display->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> u32 psr_iir;
>
> @@ -977,35 +959,35 @@ void ivb_display_irq_handler(struct intel_display
> *display, u32 de_iir)
> if (de_iir & DE_GSE_IVB)
> intel_opregion_asle_intr(display);
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
> - intel_handle_vblank(dev_priv, pipe);
> + intel_handle_vblank(display, pipe);
>
> if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
> - flip_done_handler(dev_priv, pipe);
> + flip_done_handler(display, pipe);
> }
>
> /* check event from PCH */
> if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
> u32 pch_iir = intel_de_read(display, SDEIIR);
>
> - cpt_irq_handler(dev_priv, pch_iir);
> + cpt_irq_handler(display, pch_iir);
>
> /* clear PCH hotplug event before clear CPU irq */
> intel_de_write(display, SDEIIR, pch_iir);
> }
> }
>
> -static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
> +static u32 gen8_de_port_aux_mask(struct intel_display *display)
> {
> u32 mask;
>
> - if (DISPLAY_VER(dev_priv) >= 20)
> + if (DISPLAY_VER(display) >= 20)
> return 0;
> - else if (DISPLAY_VER(dev_priv) >= 14)
> + else if (DISPLAY_VER(display) >= 14)
> return TGL_DE_PORT_AUX_DDIA |
> TGL_DE_PORT_AUX_DDIB;
> - else if (DISPLAY_VER(dev_priv) >= 13)
> + else if (DISPLAY_VER(display) >= 13)
> return TGL_DE_PORT_AUX_DDIA |
> TGL_DE_PORT_AUX_DDIB |
> TGL_DE_PORT_AUX_DDIC |
> @@ -1015,7 +997,7 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
> TGL_DE_PORT_AUX_USBC2 |
> TGL_DE_PORT_AUX_USBC3 |
> TGL_DE_PORT_AUX_USBC4;
> - else if (DISPLAY_VER(dev_priv) >= 12)
> + else if (DISPLAY_VER(display) >= 12)
> return TGL_DE_PORT_AUX_DDIA |
> TGL_DE_PORT_AUX_DDIB |
> TGL_DE_PORT_AUX_DDIC |
> @@ -1027,12 +1009,12 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
> TGL_DE_PORT_AUX_USBC6;
>
> mask = GEN8_AUX_CHANNEL_A;
> - if (DISPLAY_VER(dev_priv) >= 9)
> + if (DISPLAY_VER(display) >= 9)
> mask |= GEN9_AUX_CHANNEL_B |
> GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
>
> - if (DISPLAY_VER(dev_priv) == 11) {
> + if (DISPLAY_VER(display) == 11) {
> mask |= ICL_AUX_CHANNEL_F;
> mask |= ICL_AUX_CHANNEL_E;
> }
> @@ -1040,10 +1022,8 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
> return mask;
> }
>
> -static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
> +static u32 gen8_de_pipe_fault_mask(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> -
> if (DISPLAY_VER(display) >= 14)
> return MTL_PIPEDMC_ATS_FAULT |
> MTL_PLANE_ATS_FAULT |
> @@ -1195,15 +1175,14 @@ gen8_pipe_fault_handlers(struct intel_display
> *display)
> return bdw_pipe_fault_handlers;
> }
>
> -static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
> +static void intel_pmdemand_irq_handler(struct intel_display *display)
> {
> - wake_up_all(&dev_priv->display.pmdemand.waitqueue);
> + wake_up_all(&display->pmdemand.waitqueue);
> }
>
> static void
> -gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> +gen8_de_misc_irq_handler(struct intel_display *display, u32 iir)
> {
> - struct intel_display *display = &dev_priv->display;
> bool found = false;
>
> if (HAS_DBUF_OVERLAP_DETECTION(display)) {
> @@ -1213,20 +1192,20 @@ gen8_de_misc_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> }
> }
>
> - if (DISPLAY_VER(dev_priv) >= 14) {
> + if (DISPLAY_VER(display) >= 14) {
> if (iir & (XELPDP_PMDEMAND_RSP |
> XELPDP_PMDEMAND_RSPTOUT_ERR)) {
> if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
> - drm_dbg(&dev_priv->drm,
> + drm_dbg(display->drm,
> "Error waiting for Punit PM Demand
> Response\n");
>
> - intel_pmdemand_irq_handler(dev_priv);
> + intel_pmdemand_irq_handler(display);
> found = true;
> }
>
> if (iir & XELPDP_RM_TIMEOUT) {
> u32 val = intel_de_read(display,
> RM_TIMEOUT_REG_CAPTURE);
> - drm_warn(&dev_priv->drm, "Register Access Timeout =
> 0x%x\n", val);
> + drm_warn(display->drm, "Register Access Timeout =
> 0x%x\n", val);
> found = true;
> }
> } else if (iir & GEN8_DE_MISC_GSE) {
> @@ -1239,12 +1218,12 @@ gen8_de_misc_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> u32 psr_iir;
> i915_reg_t iir_reg;
>
> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + for_each_intel_encoder_with_psr(display->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - if (DISPLAY_VER(dev_priv) >= 12)
> - iir_reg = TRANS_PSR_IIR(dev_priv,
> - intel_dp->psr.transcoder);
> + if (DISPLAY_VER(display) >= 12)
> + iir_reg = TRANS_PSR_IIR(display,
> + intel_dp-
> >psr.transcoder);
> else
> iir_reg = EDP_PSR_IIR;
>
> @@ -1256,19 +1235,18 @@ gen8_de_misc_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> intel_psr_irq_handler(intel_dp, psr_iir);
>
> /* prior GEN12 only have one EDP PSR */
> - if (DISPLAY_VER(dev_priv) < 12)
> + if (DISPLAY_VER(display) < 12)
> break;
> }
> }
>
> if (!found)
> - drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt:
> 0x%08x\n", iir);
> + drm_err(display->drm, "Unexpected DE Misc interrupt:
> 0x%08x\n", iir);
> }
>
> -static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
> +static void gen11_dsi_te_interrupt_handler(struct intel_display *display,
> u32 te_trigger)
> {
> - struct intel_display *display = &dev_priv->display;
> enum pipe pipe = INVALID_PIPE;
> enum transcoder dsi_trans;
> enum port port;
> @@ -1278,7 +1256,7 @@ static void gen11_dsi_te_interrupt_handler(struct
> drm_i915_private *dev_priv,
> * Incase of dual link, TE comes from DSI_1
> * this is to check if dual link is enabled
> */
> - val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(dev_priv,
> TRANSCODER_DSI_0));
> + val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display,
> TRANSCODER_DSI_0));
> val &= PORT_SYNC_MODE_ENABLE;
>
> /*
> @@ -1294,12 +1272,12 @@ static void gen11_dsi_te_interrupt_handler(struct
> drm_i915_private *dev_priv,
> val = val & OP_MODE_MASK;
>
> if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
> - drm_err(&dev_priv->drm, "DSI trancoder not configured in
> command mode\n");
> + drm_err(display->drm, "DSI trancoder not configured in
> command mode\n");
> return;
> }
>
> /* Get PIPE for handling VBLANK event */
> - val = intel_de_read(display, TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
> + val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));
> switch (val & TRANS_DDI_EDP_INPUT_MASK) {
> case TRANS_DDI_EDP_INPUT_A_ON:
> pipe = PIPE_A;
> @@ -1311,28 +1289,28 @@ static void gen11_dsi_te_interrupt_handler(struct
> drm_i915_private *dev_priv,
> pipe = PIPE_C;
> break;
> default:
> - drm_err(&dev_priv->drm, "Invalid PIPE\n");
> + drm_err(display->drm, "Invalid PIPE\n");
> return;
> }
>
> - intel_handle_vblank(dev_priv, pipe);
> + intel_handle_vblank(display, pipe);
>
> /* clear TE in dsi IIR */
> port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
> intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0);
> }
>
> -static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
> +static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display)
> {
> - if (DISPLAY_VER(i915) >= 9)
> + if (DISPLAY_VER(display) >= 9)
> return GEN9_PIPE_PLANE1_FLIP_DONE;
> else
> return GEN8_PIPE_PRIMARY_FLIP_DONE;
> }
>
> -static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32
> *pch_iir, u32 *pica_iir)
> +static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32
> *pch_iir, u32 *pica_iir)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> u32 pica_ier = 0;
>
> *pica_iir = 0;
> @@ -1346,7 +1324,7 @@ static void gen8_read_and_ack_pch_irqs(struct
> drm_i915_private *i915, u32 *pch_i
> * their flags both in the PICA and SDE IIR.
> */
> if (*pch_iir & SDE_PICAINTERRUPT) {
> - drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) <
> PCH_MTL);
> + drm_WARN_ON(display->drm, INTEL_PCH_TYPE(i915) <
> PCH_MTL);
>
> pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0);
> *pica_iir = intel_de_read(display, PICAINTERRUPT_IIR);
> @@ -1365,26 +1343,26 @@ void gen8_de_irq_handler(struct intel_display
> *display, u32 master_ctl)
> u32 iir;
> enum pipe pipe;
>
> - drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));
> + drm_WARN_ON_ONCE(display->drm, !HAS_DISPLAY(display));
>
> if (master_ctl & GEN8_DE_MISC_IRQ) {
> iir = intel_de_read(display, GEN8_DE_MISC_IIR);
> if (iir) {
> intel_de_write(display, GEN8_DE_MISC_IIR, iir);
> - gen8_de_misc_irq_handler(dev_priv, iir);
> + gen8_de_misc_irq_handler(display, iir);
> } else {
> - drm_err_ratelimited(&dev_priv->drm,
> + drm_err_ratelimited(display->drm,
> "The master control interrupt lied (DE
> MISC)!\n");
> }
> }
>
> - if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl &
> GEN11_DE_HPD_IRQ)) {
> + if (DISPLAY_VER(display) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
> iir = intel_de_read(display, GEN11_DE_HPD_IIR);
> if (iir) {
> intel_de_write(display, GEN11_DE_HPD_IIR, iir);
> gen11_hpd_irq_handler(display, iir);
> } else {
> - drm_err_ratelimited(&dev_priv->drm,
> + drm_err_ratelimited(display->drm,
> "The master control interrupt lied,
> (DE HPD)!\n");
> }
> }
> @@ -1396,19 +1374,19 @@ void gen8_de_irq_handler(struct intel_display
> *display, u32 master_ctl)
>
> intel_de_write(display, GEN8_DE_PORT_IIR, iir);
>
> - if (iir & gen8_de_port_aux_mask(dev_priv)) {
> + if (iir & gen8_de_port_aux_mask(display)) {
> intel_dp_aux_irq_handler(display);
> found = true;
> }
>
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> {
> + if (display->platform.geminilake || display-
> >platform.broxton) {
> u32 hotplug_trigger = iir &
> BXT_DE_PORT_HOTPLUG_MASK;
>
> if (hotplug_trigger) {
> bxt_hpd_irq_handler(display,
> hotplug_trigger);
> found = true;
> }
> - } else if (IS_BROADWELL(dev_priv)) {
> + } else if (display->platform.broadwell) {
> u32 hotplug_trigger = iir &
> BDW_DE_PORT_HOTPLUG_MASK;
>
> if (hotplug_trigger) {
> @@ -1417,31 +1395,31 @@ void gen8_de_irq_handler(struct intel_display
> *display, u32 master_ctl)
> }
> }
>
> - if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> &&
> + if ((display->platform.geminilake || display-
> >platform.broxton) &&
> (iir & BXT_DE_PORT_GMBUS)) {
> intel_gmbus_irq_handler(display);
> found = true;
> }
>
> - if (DISPLAY_VER(dev_priv) >= 11) {
> + if (DISPLAY_VER(display) >= 11) {
> u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
>
> if (te_trigger) {
> -
> gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
> +
> gen11_dsi_te_interrupt_handler(display, te_trigger);
> found = true;
> }
> }
>
> if (!found)
> - drm_err_ratelimited(&dev_priv->drm,
> + drm_err_ratelimited(display->drm,
> "Unexpected DE Port
> interrupt\n");
> } else {
> - drm_err_ratelimited(&dev_priv->drm,
> + drm_err_ratelimited(display->drm,
> "The master control interrupt lied (DE
> PORT)!\n");
> }
> }
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(display, pipe) {
> u32 fault_errors;
>
> if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
> @@ -1449,7 +1427,7 @@ void gen8_de_irq_handler(struct intel_display *display,
> u32 master_ctl)
>
> iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));
> if (!iir) {
> - drm_err_ratelimited(&dev_priv->drm,
> + drm_err_ratelimited(display->drm,
> "The master control interrupt lied (DE
> PIPE)!\n");
> continue;
> }
> @@ -1457,29 +1435,29 @@ void gen8_de_irq_handler(struct intel_display
> *display, u32 master_ctl)
> intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir);
>
> if (iir & GEN8_PIPE_VBLANK)
> - intel_handle_vblank(dev_priv, pipe);
> + intel_handle_vblank(display, pipe);
>
> - if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
> - flip_done_handler(dev_priv, pipe);
> + if (iir & gen8_de_pipe_flip_done_mask(display))
> + flip_done_handler(display, pipe);
>
> - if (HAS_DSB(dev_priv)) {
> + if (HAS_DSB(display)) {
> if (iir & GEN12_DSB_INT(INTEL_DSB_0))
> - intel_dsb_irq_handler(&dev_priv->display, pipe,
> INTEL_DSB_0);
> + intel_dsb_irq_handler(display, pipe,
> INTEL_DSB_0);
>
> if (iir & GEN12_DSB_INT(INTEL_DSB_1))
> - intel_dsb_irq_handler(&dev_priv->display, pipe,
> INTEL_DSB_1);
> + intel_dsb_irq_handler(display, pipe,
> INTEL_DSB_1);
>
> if (iir & GEN12_DSB_INT(INTEL_DSB_2))
> - intel_dsb_irq_handler(&dev_priv->display, pipe,
> INTEL_DSB_2);
> + intel_dsb_irq_handler(display, pipe,
> INTEL_DSB_2);
> }
>
> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
> - hsw_pipe_crc_irq_handler(dev_priv, pipe);
> + hsw_pipe_crc_irq_handler(display, pipe);
>
> if (iir & GEN8_PIPE_FIFO_UNDERRUN)
> intel_cpu_fifo_underrun_irq_handler(display, pipe);
>
> - fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
> + fault_errors = iir & gen8_de_pipe_fault_mask(display);
> if (fault_errors)
> intel_pipe_fault_irq_handler(display,
>
> gen8_pipe_fault_handlers(display),
> @@ -1495,7 +1473,7 @@ void gen8_de_irq_handler(struct intel_display *display,
> u32 master_ctl)
> * scheme also closed the SDE interrupt handling race we've
> seen
> * on older pch-split platforms. But this needs testing.
> */
> - gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir);
> + gen8_read_and_ack_pch_irqs(display, &iir, &pica_iir);
> if (iir) {
> if (pica_iir)
> xelpdp_pica_irq_handler(display, pica_iir);
> @@ -1505,13 +1483,13 @@ void gen8_de_irq_handler(struct intel_display
> *display, u32 master_ctl)
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> spt_irq_handler(display, iir);
> else
> - cpt_irq_handler(dev_priv, iir);
> + cpt_irq_handler(display, iir);
> } else {
> /*
> * Like on previous PCH there seems to be something
> * fishy going on with forwarding PCH interrupts.
> */
> - drm_dbg(&dev_priv->drm,
> + drm_dbg(display->drm,
> "The master control interrupt lied (SDE)!\n");
> }
> }
> @@ -1556,10 +1534,9 @@ void gen11_display_irq_handler(struct intel_display
> *display)
> enable_rpm_wakeref_asserts(&i915->runtime_pm);
> }
>
> -static void i915gm_irq_cstate_wa_enable(struct drm_i915_private *i915)
> +static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> - lockdep_assert_held(&i915->drm.vblank_time_lock);
> + lockdep_assert_held(&display->drm->vblank_time_lock);
>
> /*
> * Vblank/CRC interrupts fail to wake the device up from C2+.
> @@ -1567,33 +1544,30 @@ static void i915gm_irq_cstate_wa_enable(struct
> drm_i915_private *i915)
> * the problem. There is a small power cost so we do this
> * only when vblank/CRC interrupts are actually enabled.
> */
> - if (i915->display.irq.vblank_enabled++ == 0)
> + if (display->irq.vblank_enabled++ == 0)
> intel_de_write(display, SCPD0,
>
> _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
> }
>
> -static void i915gm_irq_cstate_wa_disable(struct drm_i915_private *i915)
> +static void i915gm_irq_cstate_wa_disable(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> - lockdep_assert_held(&i915->drm.vblank_time_lock);
> + lockdep_assert_held(&display->drm->vblank_time_lock);
>
> - if (--i915->display.irq.vblank_enabled == 0)
> + if (--display->irq.vblank_enabled == 0)
> intel_de_write(display, SCPD0,
>
> _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
> }
>
> void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> -
> - spin_lock_irq(&i915->drm.vblank_time_lock);
> + spin_lock_irq(&display->drm->vblank_time_lock);
>
> if (enable)
> - i915gm_irq_cstate_wa_enable(i915);
> + i915gm_irq_cstate_wa_enable(display);
> else
> - i915gm_irq_cstate_wa_disable(i915);
> + i915gm_irq_cstate_wa_disable(display);
>
> - spin_unlock_irq(&i915->drm.vblank_time_lock);
> + spin_unlock_irq(&display->drm->vblank_time_lock);
> }
>
> int i8xx_enable_vblank(struct drm_crtc *crtc)
> @@ -1624,20 +1598,20 @@ void i8xx_disable_vblank(struct drm_crtc *crtc)
>
> int i915gm_enable_vblank(struct drm_crtc *crtc)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->dev);
> + struct intel_display *display = to_intel_display(crtc->dev);
>
> - i915gm_irq_cstate_wa_enable(i915);
> + i915gm_irq_cstate_wa_enable(display);
>
> return i8xx_enable_vblank(crtc);
> }
>
> void i915gm_disable_vblank(struct drm_crtc *crtc)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->dev);
> + struct intel_display *display = to_intel_display(crtc->dev);
>
> i8xx_disable_vblank(crtc);
>
> - i915gm_irq_cstate_wa_disable(i915);
> + i915gm_irq_cstate_wa_disable(display);
> }
>
> int i965_enable_vblank(struct drm_crtc *crtc)
> @@ -1674,7 +1648,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> unsigned long irqflags;
> - u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
> + u32 bit = DISPLAY_VER(display) >= 7 ?
> DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> @@ -1684,7 +1658,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
> /* Even though there is no DMC, frame counter can get stuck when
> * PSR is active as no frames are generated.
> */
> - if (HAS_PSR(dev_priv))
> + if (HAS_PSR(display))
> drm_crtc_vblank_restore(crtc);
>
> return 0;
> @@ -1696,7 +1670,7 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> unsigned long irqflags;
> - u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
> + u32 bit = DISPLAY_VER(display) >= 7 ?
> DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> @@ -1764,7 +1738,7 @@ int bdw_enable_vblank(struct drm_crtc *_crtc)
> /* Even if there is no DMC, frame counter can get stuck when
> * PSR is active as no frames are generated, so check only for PSR.
> */
> - if (HAS_PSR(dev_priv))
> + if (HAS_PSR(display))
> drm_crtc_vblank_restore(&crtc->base);
>
> return 0;
> @@ -1897,11 +1871,11 @@ void vlv_display_error_irq_handler(struct
> intel_display *display,
> vlv_page_table_error_irq_handler(display, dpinvgtt);
> }
>
> -static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> +static void _vlv_display_irq_reset(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> - if (IS_CHERRYVIEW(dev_priv))
> + if (display->platform.cherryview)
> intel_de_write(display, DPINVGTT,
> DPINVGTT_STATUS_MASK_CHV);
> else
> intel_de_write(display, DPINVGTT,
> DPINVGTT_STATUS_MASK_VLV);
> @@ -1910,9 +1884,9 @@ static void _vlv_display_irq_reset(struct
> drm_i915_private *dev_priv)
> VLV_ERROR_REGS);
>
> i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0);
> - intel_de_rmw(display, PORT_HOTPLUG_STAT(dev_priv), 0, 0);
> + intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
>
> - i9xx_pipestat_irq_reset(dev_priv);
> + i9xx_pipestat_irq_reset(display);
>
> intel_display_irq_regs_reset(display, VLV_IRQ_REGS);
> dev_priv->irq_mask = ~0u;
> @@ -1920,22 +1894,18 @@ static void _vlv_display_irq_reset(struct
> drm_i915_private *dev_priv)
>
> void vlv_display_irq_reset(struct intel_display *display)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> -
> - if (dev_priv->display.irq.vlv_display_irqs_enabled)
> - _vlv_display_irq_reset(dev_priv);
> + if (display->irq.vlv_display_irqs_enabled)
> + _vlv_display_irq_reset(display);
> }
>
> void i9xx_display_irq_reset(struct intel_display *display)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> -
> - if (I915_HAS_HOTPLUG(i915)) {
> + if (I915_HAS_HOTPLUG(display)) {
> i915_hotplug_interrupt_update(display, 0xffffffff, 0);
> - intel_de_rmw(display, PORT_HOTPLUG_STAT(i915), 0, 0);
> + intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
> }
>
> - i9xx_pipestat_irq_reset(i915);
> + i9xx_pipestat_irq_reset(display);
> }
>
> static u32 vlv_error_mask(void)
> @@ -1951,10 +1921,10 @@ void vlv_display_irq_postinstall(struct intel_display
> *display)
> u32 enable_mask;
> enum pipe pipe;
>
> - if (!dev_priv->display.irq.vlv_display_irqs_enabled)
> + if (!display->irq.vlv_display_irqs_enabled)
> return;
>
> - if (IS_CHERRYVIEW(dev_priv))
> + if (display->platform.cherryview)
> intel_de_write(display, DPINVGTT,
> DPINVGTT_STATUS_MASK_CHV |
> DPINVGTT_EN_MASK_CHV);
> @@ -1969,7 +1939,7 @@ void vlv_display_irq_postinstall(struct intel_display
> *display)
> pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
>
> i915_enable_pipestat(display, PIPE_A,
> PIPE_GMBUS_INTERRUPT_STATUS);
> - for_each_pipe(dev_priv, pipe)
> + for_each_pipe(display, pipe)
> i915_enable_pipestat(display, pipe, pipestat_mask);
>
> enable_mask = I915_DISPLAY_PORT_INTERRUPT |
> @@ -1979,11 +1949,11 @@ void vlv_display_irq_postinstall(struct intel_display
> *display)
> I915_LPE_PIPE_B_INTERRUPT |
> I915_MASTER_ERROR_INTERRUPT;
>
> - if (IS_CHERRYVIEW(dev_priv))
> + if (display->platform.cherryview)
> enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
> I915_LPE_PIPE_C_INTERRUPT;
>
> - drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
> + drm_WARN_ON(display->drm, dev_priv->irq_mask != ~0u);
>
> dev_priv->irq_mask = ~enable_mask;
>
> @@ -1992,16 +1962,15 @@ void vlv_display_irq_postinstall(struct intel_display
> *display)
>
> void gen8_display_irq_reset(struct intel_display *display)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
>
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(display))
> return;
>
> intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
> intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
>
> - for_each_pipe(dev_priv, pipe)
> + for_each_pipe(display, pipe)
> if (intel_display_power_is_enabled(display,
>
> POWER_DOMAIN_PIPE(pipe)))
> intel_display_irq_regs_reset(display,
> GEN8_DE_PIPE_IRQ_REGS(pipe));
> @@ -2017,15 +1986,15 @@ void gen11_display_irq_reset(struct intel_display
> *display)
> u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
>
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(display))
> return;
>
> intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(display) >= 12) {
> enum transcoder trans;
>
> - for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
> + for_each_cpu_transcoder_masked(display, trans, trans_mask) {
> enum intel_display_power_domain domain;
>
> domain = POWER_DOMAIN_TRANSCODER(trans);
> @@ -2033,10 +2002,10 @@ void gen11_display_irq_reset(struct intel_display
> *display)
> continue;
>
> intel_de_write(display,
> - TRANS_PSR_IMR(dev_priv, trans),
> + TRANS_PSR_IMR(display, trans),
> 0xffffffff);
> intel_de_write(display,
> - TRANS_PSR_IIR(dev_priv, trans),
> + TRANS_PSR_IIR(display, trans),
> 0xffffffff);
> }
> } else {
> @@ -2044,7 +2013,7 @@ void gen11_display_irq_reset(struct intel_display
> *display)
> intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
> }
>
> - for_each_pipe(dev_priv, pipe)
> + for_each_pipe(display, pipe)
> if (intel_display_power_is_enabled(display,
>
> POWER_DOMAIN_PIPE(pipe)))
> intel_display_irq_regs_reset(display,
> GEN8_DE_PIPE_IRQ_REGS(pipe));
> @@ -2052,7 +2021,7 @@ void gen11_display_irq_reset(struct intel_display
> *display)
> intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS);
> intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);
>
> - if (DISPLAY_VER(dev_priv) >= 14)
> + if (DISPLAY_VER(display) >= 14)
> intel_display_irq_regs_reset(display,
> PICAINTERRUPT_IRQ_REGS);
> else
> intel_display_irq_regs_reset(display,
> GEN11_DE_HPD_IRQ_REGS);
> @@ -2066,7 +2035,7 @@ void gen8_irq_power_well_post_enable(struct
> intel_display *display,
> {
> struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
> - gen8_de_pipe_flip_done_mask(dev_priv);
> + gen8_de_pipe_flip_done_mask(display);
> enum pipe pipe;
>
> spin_lock_irq(&dev_priv->irq_lock);
> @@ -2076,10 +2045,10 @@ void gen8_irq_power_well_post_enable(struct
> intel_display *display,
> return;
> }
>
> - for_each_pipe_masked(dev_priv, pipe, pipe_mask)
> + for_each_pipe_masked(display, pipe, pipe_mask)
> intel_display_irq_regs_init(display,
> GEN8_DE_PIPE_IRQ_REGS(pipe),
> - dev_priv-
> >display.irq.de_irq_mask[pipe],
> - ~dev_priv-
> >display.irq.de_irq_mask[pipe] | extra_ier);
> + display->irq.de_irq_mask[pipe],
> + ~display->irq.de_irq_mask[pipe] |
> extra_ier);
>
> spin_unlock_irq(&dev_priv->irq_lock);
> }
> @@ -2097,7 +2066,7 @@ void gen8_irq_power_well_pre_disable(struct
> intel_display *display,
> return;
> }
>
> - for_each_pipe_masked(dev_priv, pipe, pipe_mask)
> + for_each_pipe_masked(display, pipe, pipe_mask)
> intel_display_irq_regs_reset(display,
> GEN8_DE_PIPE_IRQ_REGS(pipe));
>
> spin_unlock_irq(&dev_priv->irq_lock);
> @@ -2117,9 +2086,9 @@ void gen8_irq_power_well_pre_disable(struct
> intel_display *display,
> * to avoid races with the irq handler, assuming we have MSI. Shared legacy
> * interrupts could still race.
> */
> -static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
> +static void ibx_irq_postinstall(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 mask;
>
> if (HAS_PCH_NOP(dev_priv))
> @@ -2141,13 +2110,13 @@ void valleyview_enable_display_irqs(struct
> intel_display *display)
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> - if (dev_priv->display.irq.vlv_display_irqs_enabled)
> + if (display->irq.vlv_display_irqs_enabled)
> return;
>
> - dev_priv->display.irq.vlv_display_irqs_enabled = true;
> + display->irq.vlv_display_irqs_enabled = true;
>
> if (intel_irqs_enabled(dev_priv)) {
> - _vlv_display_irq_reset(dev_priv);
> + _vlv_display_irq_reset(display);
> vlv_display_irq_postinstall(display);
> }
> }
> @@ -2158,13 +2127,13 @@ void valleyview_disable_display_irqs(struct
> intel_display *display)
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> - if (!dev_priv->display.irq.vlv_display_irqs_enabled)
> + if (!display->irq.vlv_display_irqs_enabled)
> return;
>
> - dev_priv->display.irq.vlv_display_irqs_enabled = false;
> + display->irq.vlv_display_irqs_enabled = false;
>
> if (intel_irqs_enabled(dev_priv))
> - _vlv_display_irq_reset(dev_priv);
> + _vlv_display_irq_reset(display);
> }
>
> void ilk_de_irq_postinstall(struct intel_display *display)
> @@ -2173,7 +2142,7 @@ void ilk_de_irq_postinstall(struct intel_display
> *display)
>
> u32 display_mask, extra_mask;
>
> - if (DISPLAY_VER(i915) >= 7) {
> + if (DISPLAY_VER(display) >= 7) {
> display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
> DE_PCH_EVENT_IVB |
> DE_AUX_CHANNEL_A_IVB);
> extra_mask = (DE_PIPEC_VBLANK_IVB |
> DE_PIPEB_VBLANK_IVB |
> @@ -2194,59 +2163,59 @@ void ilk_de_irq_postinstall(struct intel_display
> *display)
> DE_DP_A_HOTPLUG);
> }
>
> - if (IS_HASWELL(i915)) {
> + if (display->platform.haswell) {
> intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR);
> display_mask |= DE_EDP_PSR_INT_HSW;
> }
>
> - if (IS_IRONLAKE_M(i915))
> + if (display->platform.ironlake && display->platform.mobile)
> extra_mask |= DE_PCU_EVENT;
>
> i915->irq_mask = ~display_mask;
>
> - ibx_irq_postinstall(i915);
> + ibx_irq_postinstall(display);
>
> intel_display_irq_regs_init(display, DE_IRQ_REGS, i915->irq_mask,
> display_mask | extra_mask);
> }
>
> -static void mtp_irq_postinstall(struct drm_i915_private *i915);
> -static void icp_irq_postinstall(struct drm_i915_private *i915);
> +static void mtp_irq_postinstall(struct intel_display *display);
> +static void icp_irq_postinstall(struct intel_display *display);
>
> void gen8_de_irq_postinstall(struct intel_display *display)
> {
> struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> - u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
> + u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
> GEN8_PIPE_CDCLK_CRC_DONE;
> u32 de_pipe_enables;
> - u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
> + u32 de_port_masked = gen8_de_port_aux_mask(display);
> u32 de_port_enables;
> u32 de_misc_masked = GEN8_DE_EDP_PSR;
> u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
> enum pipe pipe;
>
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(display))
> return;
>
> - if (DISPLAY_VER(dev_priv) >= 14)
> - mtp_irq_postinstall(dev_priv);
> + if (DISPLAY_VER(display) >= 14)
> + mtp_irq_postinstall(display);
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> - icp_irq_postinstall(dev_priv);
> + icp_irq_postinstall(display);
> else if (HAS_PCH_SPLIT(dev_priv))
> - ibx_irq_postinstall(dev_priv);
> + ibx_irq_postinstall(display);
>
> - if (DISPLAY_VER(dev_priv) < 11)
> + if (DISPLAY_VER(display) < 11)
> de_misc_masked |= GEN8_DE_MISC_GSE;
>
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> + if (display->platform.geminilake || display->platform.broxton)
> de_port_masked |= BXT_DE_PORT_GMBUS;
>
> - if (DISPLAY_VER(dev_priv) >= 14) {
> + if (DISPLAY_VER(display) >= 14) {
> de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> XELPDP_PMDEMAND_RSP |
> XELPDP_RM_TIMEOUT;
> - } else if (DISPLAY_VER(dev_priv) >= 11) {
> + } else if (DISPLAY_VER(display) >= 11) {
> enum port port;
>
> if (intel_bios_is_dsi_present(display, &port))
> @@ -2256,25 +2225,25 @@ void gen8_de_irq_postinstall(struct intel_display
> *display)
> if (HAS_DBUF_OVERLAP_DETECTION(display))
> de_misc_masked |= XE2LPD_DBUF_OVERLAP_DETECTED;
>
> - if (HAS_DSB(dev_priv))
> + if (HAS_DSB(display))
> de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) |
> GEN12_DSB_INT(INTEL_DSB_1) |
> GEN12_DSB_INT(INTEL_DSB_2);
>
> de_pipe_enables = de_pipe_masked |
> GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
> - gen8_de_pipe_flip_done_mask(dev_priv);
> + gen8_de_pipe_flip_done_mask(display);
>
> de_port_enables = de_port_masked;
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> + if (display->platform.geminilake || display->platform.broxton)
> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> - else if (IS_BROADWELL(dev_priv))
> + else if (display->platform.broadwell)
> de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(display) >= 12) {
> enum transcoder trans;
>
> - for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
> + for_each_cpu_transcoder_masked(display, trans, trans_mask) {
> enum intel_display_power_domain domain;
>
> domain = POWER_DOMAIN_TRANSCODER(trans);
> @@ -2282,19 +2251,19 @@ void gen8_de_irq_postinstall(struct intel_display
> *display)
> continue;
>
> intel_display_irq_regs_assert_irr_is_zero(display,
> -
> TRANS_PSR_IIR(dev_priv, trans));
> +
> TRANS_PSR_IIR(display, trans));
> }
> } else {
> intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR);
> }
>
> - for_each_pipe(dev_priv, pipe) {
> - dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked;
> + for_each_pipe(display, pipe) {
> + display->irq.de_irq_mask[pipe] = ~de_pipe_masked;
>
> if (intel_display_power_is_enabled(display,
>
> POWER_DOMAIN_PIPE(pipe)))
> intel_display_irq_regs_init(display,
> GEN8_DE_PIPE_IRQ_REGS(pipe),
> - dev_priv-
> >display.irq.de_irq_mask[pipe],
> + display-
> >irq.de_irq_mask[pipe],
> de_pipe_enables);
> }
>
> @@ -2303,7 +2272,7 @@ void gen8_de_irq_postinstall(struct intel_display
> *display)
> intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS,
> ~de_misc_masked,
> de_misc_masked);
>
> - if (IS_DISPLAY_VER(dev_priv, 11, 13)) {
> + if (IS_DISPLAY_VER(display, 11, 13)) {
> u32 de_hpd_masked = 0;
> u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
> GEN11_DE_TBT_HOTPLUG_MASK;
> @@ -2313,9 +2282,8 @@ void gen8_de_irq_postinstall(struct intel_display
> *display)
> }
> }
>
> -static void mtp_irq_postinstall(struct drm_i915_private *i915)
> +static void mtp_irq_postinstall(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT;
> u32 de_hpd_mask = XELPDP_AUX_TC_MASK;
> u32 de_hpd_enables = de_hpd_mask |
> XELPDP_DP_ALT_HOTPLUG_MASK |
> @@ -2327,9 +2295,8 @@ static void mtp_irq_postinstall(struct
> drm_i915_private *i915)
> intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +static void icp_irq_postinstall(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> u32 mask = SDE_GMBUS_ICP;
>
> intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 9/9] drm/i915/display: rename I915_HAS_HOTPLUG() to HAS_HOTPLUG
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (7 preceding siblings ...)
2025-03-11 18:00 ` [PATCH 8/9] drm/i915/irq: convert rest of intel_display_irq.[ch] " Jani Nikula
@ 2025-03-11 18:00 ` Jani Nikula
2025-03-12 6:39 ` Shankar, Uma
2025-03-11 19:13 ` [PATCH 0/9] drm/i915/display: conversions to struct intel_display Ville Syrjälä
` (9 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-11 18:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Most of the other display feature check macros are just
HAS_<something>. Follow suit with hotplug check.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_device.h | 2 +-
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index a7f360f89410..cca22d2402e8 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -877,7 +877,7 @@ intel_crt_detect(struct drm_connector *connector,
wakeref = intel_display_power_get(display, encoder->power_domain);
- if (I915_HAS_HOTPLUG(display)) {
+ if (HAS_HOTPLUG(display)) {
/* We can not rely on the HPD pin always being correctly wired
* up, for example many KVM do not pass it through, and so
* only trust an assertion that the monitor is connected.
@@ -901,7 +901,7 @@ intel_crt_detect(struct drm_connector *connector,
* broken monitor (without edid) to work behind a broken kvm (that fails
* to have the right resistors for HP detection) needs to fix this up.
* For now just bail out. */
- if (I915_HAS_HOTPLUG(display)) {
+ if (HAS_HOTPLUG(display)) {
status = connector_status_disconnected;
goto out;
}
@@ -1081,7 +1081,7 @@ void intel_crt_init(struct intel_display *display)
crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
- if (I915_HAS_HOTPLUG(display) &&
+ if (HAS_HOTPLUG(display) &&
!dmi_check_system(intel_spurious_crt_detect)) {
crt->base.hpd_pin = HPD_CRT;
crt->base.hotplug = intel_encoder_hotplug;
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 717286981687..af574ae1c57e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -169,6 +169,7 @@ struct intel_display_platforms {
#define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4)
#define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
#define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch)
+#define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug)
#define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx)
#define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc)
#define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell)
@@ -192,7 +193,6 @@ struct intel_display_platforms {
#define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)
#define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
#define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
-#define I915_HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical)
#define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 6f78fe6de06a..d9f9b9f78abb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1900,7 +1900,7 @@ void vlv_display_irq_reset(struct intel_display *display)
void i9xx_display_irq_reset(struct intel_display *display)
{
- if (I915_HAS_HOTPLUG(display)) {
+ if (HAS_HOTPLUG(display)) {
i915_hotplug_interrupt_update(display, 0xffffffff, 0);
intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 1bcff3a47745..2463e61e7802 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -1481,7 +1481,7 @@ void intel_hotplug_irq_init(struct intel_display *display)
intel_hpd_init_early(display);
if (HAS_GMCH(display)) {
- if (I915_HAS_HOTPLUG(display))
+ if (HAS_HOTPLUG(display))
display->funcs.hotplug = &i915_hpd_funcs;
} else {
if (HAS_PCH_DG2(i915))
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 6e2d9929b4d7..757b9ce7e3b1 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2036,7 +2036,7 @@ static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
struct intel_display *display = to_intel_display(&intel_sdvo->base);
u16 hotplug;
- if (!I915_HAS_HOTPLUG(display))
+ if (!HAS_HOTPLUG(display))
return 0;
/*
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ba3afc7e38ac..c1f938a1da44 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -954,7 +954,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
enable_mask |= I915_ASLE_INTERRUPT;
}
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (HAS_HOTPLUG(dev_priv)) {
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
}
@@ -995,7 +995,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
ret = IRQ_HANDLED;
- if (I915_HAS_HOTPLUG(dev_priv) &&
+ if (HAS_HOTPLUG(dev_priv) &&
iir & I915_DISPLAY_PORT_INTERRUPT)
hotplug_status = i9xx_hpd_irq_ack(display);
--
2.39.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* RE: [PATCH 9/9] drm/i915/display: rename I915_HAS_HOTPLUG() to HAS_HOTPLUG
2025-03-11 18:00 ` [PATCH 9/9] drm/i915/display: rename I915_HAS_HOTPLUG() to HAS_HOTPLUG Jani Nikula
@ 2025-03-12 6:39 ` Shankar, Uma
0 siblings, 0 replies; 34+ messages in thread
From: Shankar, Uma @ 2025-03-12 6:39 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, March 11, 2025 11:31 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 9/9] drm/i915/display: rename I915_HAS_HOTPLUG() to
> HAS_HOTPLUG
>
> Most of the other display feature check macros are just HAS_<something>. Follow
> suit with hotplug check.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_display_device.h | 2 +-
> drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 4 ++--
> 6 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index a7f360f89410..cca22d2402e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -877,7 +877,7 @@ intel_crt_detect(struct drm_connector *connector,
>
> wakeref = intel_display_power_get(display, encoder->power_domain);
>
> - if (I915_HAS_HOTPLUG(display)) {
> + if (HAS_HOTPLUG(display)) {
> /* We can not rely on the HPD pin always being correctly wired
> * up, for example many KVM do not pass it through, and so
> * only trust an assertion that the monitor is connected.
> @@ -901,7 +901,7 @@ intel_crt_detect(struct drm_connector *connector,
> * broken monitor (without edid) to work behind a broken kvm (that fails
> * to have the right resistors for HP detection) needs to fix this up.
> * For now just bail out. */
> - if (I915_HAS_HOTPLUG(display)) {
> + if (HAS_HOTPLUG(display)) {
> status = connector_status_disconnected;
> goto out;
> }
> @@ -1081,7 +1081,7 @@ void intel_crt_init(struct intel_display *display)
>
> crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
>
> - if (I915_HAS_HOTPLUG(display) &&
> + if (HAS_HOTPLUG(display) &&
> !dmi_check_system(intel_spurious_crt_detect)) {
> crt->base.hpd_pin = HPD_CRT;
> crt->base.hotplug = intel_encoder_hotplug; diff --git
> a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 717286981687..af574ae1c57e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -169,6 +169,7 @@ struct intel_display_platforms {
> #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4)
> #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10
> || (__display)->platform.kabylake)
> #define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch)
> +#define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)-
> >has_hotplug)
> #define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 &&
> !(__display)->platform.dgfx)
> #define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc)
> #define HAS_IPS(__display) ((__display)->platform.haswell_ult ||
> (__display)->platform.broadwell)
> @@ -192,7 +193,6 @@ struct intel_display_platforms {
> #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)
> #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
> #define INTEL_NUM_PIPES(__display)
> (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
> -#define I915_HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)-
> >has_hotplug)
> #define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)-
> >overlay_needs_physical)
> #define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)-
> >supports_tv)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 6f78fe6de06a..d9f9b9f78abb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1900,7 +1900,7 @@ void vlv_display_irq_reset(struct intel_display *display)
>
> void i9xx_display_irq_reset(struct intel_display *display) {
> - if (I915_HAS_HOTPLUG(display)) {
> + if (HAS_HOTPLUG(display)) {
> i915_hotplug_interrupt_update(display, 0xffffffff, 0);
> intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 1bcff3a47745..2463e61e7802 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -1481,7 +1481,7 @@ void intel_hotplug_irq_init(struct intel_display
> *display)
> intel_hpd_init_early(display);
>
> if (HAS_GMCH(display)) {
> - if (I915_HAS_HOTPLUG(display))
> + if (HAS_HOTPLUG(display))
> display->funcs.hotplug = &i915_hpd_funcs;
> } else {
> if (HAS_PCH_DG2(i915))
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 6e2d9929b4d7..757b9ce7e3b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -2036,7 +2036,7 @@ static u16 intel_sdvo_get_hotplug_support(struct
> intel_sdvo *intel_sdvo)
> struct intel_display *display = to_intel_display(&intel_sdvo->base);
> u16 hotplug;
>
> - if (!I915_HAS_HOTPLUG(display))
> + if (!HAS_HOTPLUG(display))
> return 0;
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index ba3afc7e38ac..c1f938a1da44 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -954,7 +954,7 @@ static void i915_irq_postinstall(struct drm_i915_private
> *dev_priv)
> enable_mask |= I915_ASLE_INTERRUPT;
> }
>
> - if (I915_HAS_HOTPLUG(dev_priv)) {
> + if (HAS_HOTPLUG(dev_priv)) {
> dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
> enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
> }
> @@ -995,7 +995,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>
> ret = IRQ_HANDLED;
>
> - if (I915_HAS_HOTPLUG(dev_priv) &&
> + if (HAS_HOTPLUG(dev_priv) &&
> iir & I915_DISPLAY_PORT_INTERRUPT)
> hotplug_status = i9xx_hpd_irq_ack(display);
>
> --
> 2.39.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/9] drm/i915/display: conversions to struct intel_display
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (8 preceding siblings ...)
2025-03-11 18:00 ` [PATCH 9/9] drm/i915/display: rename I915_HAS_HOTPLUG() to HAS_HOTPLUG Jani Nikula
@ 2025-03-11 19:13 ` Ville Syrjälä
2025-03-11 22:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversions to struct intel_display (rev2) Patchwork
` (8 subsequent siblings)
18 siblings, 0 replies; 34+ messages in thread
From: Ville Syrjälä @ 2025-03-11 19:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Mar 11, 2025 at 08:00:34PM +0200, Jani Nikula wrote:
> Primarily convert all hotplug and irq code to struct intel_display, and
> then some.
>
> Jani Nikula (9):
> drm/i915/color: prefer display->platform.<platform> checks
> drm/i915/connector: convert intel_connector.c to struct intel_display
> drm/i915/hotplug: convert intel_hotplug.[ch] to struct intel_display
> drm/i915/hotplug: convert hotplug debugfs to struct intel_display
> drm/i915/hotplug: convert hotplug irq handling to intel_de_*()
> drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct
> intel_display
> drm/i915/irq: convert intel_display_irq.[ch] interfaces to struct
> intel_display
> drm/i915/irq: convert rest of intel_display_irq.[ch] to struct
> intel_display
> drm/i915/display: rename I915_HAS_HOTPLUG() to HAS_HOTPLUG
Looked reasonable to me. Series is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> drivers/gpu/drm/i915/display/i9xx_plane.c | 24 +-
> drivers/gpu/drm/i915/display/intel_color.c | 16 +-
> .../gpu/drm/i915/display/intel_connector.c | 45 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 10 +-
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> .../drm/i915/display/intel_display_device.h | 2 +-
> .../drm/i915/display/intel_display_driver.c | 16 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 742 +++++++++---------
> .../gpu/drm/i915/display/intel_display_irq.h | 75 +-
> .../i915/display/intel_display_power_well.c | 18 +-
> .../drm/i915/display/intel_display_reset.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> .../drm/i915/display/intel_fifo_underrun.c | 27 +-
> drivers/gpu/drm/i915/display/intel_hotplug.c | 348 ++++----
> drivers/gpu/drm/i915/display/intel_hotplug.h | 26 +-
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 623 +++++++--------
> .../gpu/drm/i915/display/intel_hotplug_irq.h | 28 +-
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 3 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
> .../drm/i915/display/skl_universal_plane.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
> drivers/gpu/drm/i915/i915_driver.c | 14 +-
> drivers/gpu/drm/i915/i915_irq.c | 123 +--
> drivers/gpu/drm/xe/display/xe_display.c | 38 +-
> 25 files changed, 1118 insertions(+), 1086 deletions(-)
>
> --
> 2.39.5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 34+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversions to struct intel_display (rev2)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (9 preceding siblings ...)
2025-03-11 19:13 ` [PATCH 0/9] drm/i915/display: conversions to struct intel_display Ville Syrjälä
@ 2025-03-11 22:15 ` Patchwork
2025-03-11 22:15 ` ✗ Fi.CI.SPARSE: " Patchwork
` (7 subsequent siblings)
18 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2025-03-11 22:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/144748/
State : warning
== Summary ==
Error: dim checkpatch failed
fc2a574ff265 drm/i915/color: prefer display->platform.<platform> checks
c4dad7534cae drm/i915/connector: convert intel_connector.c to struct intel_display
0a57aa3579c0 drm/i915/hotplug: convert intel_hotplug.[ch] to struct intel_display
a3234e5395ae drm/i915/hotplug: convert hotplug debugfs to struct intel_display
029255db0f20 drm/i915/hotplug: convert hotplug irq handling to intel_de_*()
23c758a65d75 drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct intel_display
3a7889c2117f drm/i915/irq: convert intel_display_irq.[ch] interfaces to struct intel_display
-:856: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#856: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:74:
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-:857: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#857: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:75:
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
total: 0 errors, 2 warnings, 0 checks, 1501 lines checked
96c281bad56a drm/i915/irq: convert rest of intel_display_irq.[ch] to struct intel_display
cf710043edb9 drm/i915/display: rename I915_HAS_HOTPLUG() to HAS_HOTPLUG
^ permalink raw reply [flat|nested] 34+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915/display: conversions to struct intel_display (rev2)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (10 preceding siblings ...)
2025-03-11 22:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversions to struct intel_display (rev2) Patchwork
@ 2025-03-11 22:15 ` Patchwork
2025-03-11 22:40 ` ✗ i915.CI.BAT: failure " Patchwork
` (6 subsequent siblings)
18 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2025-03-11 22:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/144748/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 34+ messages in thread* ✗ i915.CI.BAT: failure for drm/i915/display: conversions to struct intel_display (rev2)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (11 preceding siblings ...)
2025-03-11 22:15 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2025-03-11 22:40 ` Patchwork
2025-03-12 8:51 ` Jani Nikula
2025-03-12 9:54 ` ✓ i915.CI.BAT: success " Patchwork
` (5 subsequent siblings)
18 siblings, 1 reply; 34+ messages in thread
From: Patchwork @ 2025-03-11 22:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12278 bytes --]
== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/144748/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16265 -> Patchwork_144748v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_144748v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_144748v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/index.html
Participating hosts (44 -> 43)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_144748v2:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@module-reload:
- bat-rpls-4: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][3] +3 other tests fail
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html
Known issues
------------
Here are the changes found in Patchwork_144748v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_auth@basic-auth:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][6] ([i915#10462]) +1 other test dmesg-warn
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@core_auth@basic-auth.html
* igt@debugfs_test@basic-hwmon:
- bat-twl-2: NOTRUN -> [SKIP][7] ([i915#9318])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@debugfs_test@basic-hwmon.html
* igt@dmabuf@all-tests:
- fi-pnv-d510: NOTRUN -> [INCOMPLETE][8] ([i915#12904]) +1 other test incomplete
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-pnv-d510/igt@dmabuf@all-tests.html
- bat-apl-1: NOTRUN -> [INCOMPLETE][9] ([i915#12904]) +1 other test incomplete
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@dmabuf@all-tests.html
* igt@fbdev@info:
- fi-kbl-8809g: NOTRUN -> [SKIP][10] ([i915#1849])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@fbdev@info.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][11] ([i915#2190])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
- fi-skl-6600u: NOTRUN -> [SKIP][12] ([i915#2190])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-twl-2: NOTRUN -> [SKIP][13] ([i915#10213] / [i915#11671]) +3 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adls-6: NOTRUN -> [SKIP][14] ([i915#4613]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-kbl-8809g: NOTRUN -> [SKIP][15] ([i915#4613]) +3 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html
- bat-apl-1: NOTRUN -> [SKIP][16] +3 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-6600u: NOTRUN -> [SKIP][17] ([i915#4613]) +3 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html
* igt@gem_tiled_pread_basic:
- bat-twl-2: NOTRUN -> [SKIP][18] ([i915#11031])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-twl-2: NOTRUN -> [SKIP][19] ([i915#10209] / [i915#11681])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [PASS][20] -> [DMESG-FAIL][21] ([i915#12061]) +1 other test dmesg-fail
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-twl-2: NOTRUN -> [SKIP][22] ([i915#11030] / [i915#11731]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][23] +62 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
- fi-skl-6600u: NOTRUN -> [SKIP][24] +10 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@kms_dsc@dsc-basic.html
- bat-twl-2: NOTRUN -> [SKIP][25] ([i915#9886])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-twl-2: NOTRUN -> [SKIP][26] ([i915#11032])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][27] -> [SKIP][28] ([i915#9197]) +3 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_psr@psr-primary-mmap-gtt:
- fi-pnv-d510: NOTRUN -> [SKIP][29] +33 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-pnv-d510/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-twl-2: NOTRUN -> [SKIP][30] ([i915#8809])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-twl-2: NOTRUN -> [SKIP][31] ([i915#10212] / [i915#3708])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- bat-twl-2: NOTRUN -> [SKIP][32] ([i915#10214] / [i915#3708])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-twl-2: NOTRUN -> [SKIP][33] ([i915#10216] / [i915#3708])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- bat-adls-6: [ABORT][34] ([i915#13571]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-adls-6/igt@core_hotunplug@unbind-rebind.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-adls-6/igt@core_hotunplug@unbind-rebind.html
* igt@i915_selftest@live:
- bat-mtlp-8: [DMESG-FAIL][36] ([i915#12061]) -> [PASS][37] +1 other test pass
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-8/igt@i915_selftest@live.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-8/igt@i915_selftest@live.html
- fi-bsw-n3050: [DMESG-FAIL][38] ([i915#12435]) -> [PASS][39] +1 other test pass
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/fi-bsw-n3050/igt@i915_selftest@live.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-bsw-n3050/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-9: [DMESG-FAIL][40] ([i915#12061]) -> [PASS][41] +1 other test pass
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
* igt@vgem_basic@unload:
- bat-apl-1: [ABORT][42] -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-apl-1/igt@vgem_basic@unload.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@vgem_basic@unload.html
[i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
[i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
[i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
[i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
[i915#11030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11030
[i915#11031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11031
[i915#11032]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11032
[i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11731]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11731
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
[i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
[i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_16265 -> Patchwork_144748v2
CI-20190529: 20190529
CI_DRM_16265: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8270: 49751c5c11723262ec66e564c76503f74a9fa831 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_144748v2: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/index.html
[-- Attachment #2: Type: text/html, Size: 14224 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: ✗ i915.CI.BAT: failure for drm/i915/display: conversions to struct intel_display (rev2)
2025-03-11 22:40 ` ✗ i915.CI.BAT: failure " Patchwork
@ 2025-03-12 8:51 ` Jani Nikula
2025-03-12 10:30 ` Ravali, JupallyX
0 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2025-03-12 8:51 UTC (permalink / raw)
To: I915-ci-infra; +Cc: intel-gfx
On Tue, 11 Mar 2025, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: drm/i915/display: conversions to struct intel_display (rev2)
> URL : https://patchwork.freedesktop.org/series/144748/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_16265 -> Patchwork_144748v2
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_144748v2 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_144748v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/index.html
>
> Participating hosts (44 -> 43)
> ------------------------------
>
> Missing (1): fi-snb-2520m
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_144748v2:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_pm_rpm@module-reload:
> - bat-rpls-4: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
Seems unrelated.
>
> * igt@kms_addfb_basic@too-high:
> - fi-kbl-8809g: NOTRUN -> [FAIL][3] +3 other tests fail
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html
>
> * igt@kms_force_connector_basic@force-connector-state:
> - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][4]
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
>
> * igt@kms_force_connector_basic@force-edid:
> - fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][5]
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html
We seem to be probing amdgpu again for fi-kbl-8809g. Weren't we supposed
to block that?
Please fix/re-report.
BR,
Jani.
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_144748v2 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@core_auth@basic-auth:
> - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][6] ([i915#10462]) +1 other test dmesg-warn
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@core_auth@basic-auth.html
>
> * igt@debugfs_test@basic-hwmon:
> - bat-twl-2: NOTRUN -> [SKIP][7] ([i915#9318])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@debugfs_test@basic-hwmon.html
>
> * igt@dmabuf@all-tests:
> - fi-pnv-d510: NOTRUN -> [INCOMPLETE][8] ([i915#12904]) +1 other test incomplete
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-pnv-d510/igt@dmabuf@all-tests.html
> - bat-apl-1: NOTRUN -> [INCOMPLETE][9] ([i915#12904]) +1 other test incomplete
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@dmabuf@all-tests.html
>
> * igt@fbdev@info:
> - fi-kbl-8809g: NOTRUN -> [SKIP][10] ([i915#1849])
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@fbdev@info.html
>
> * igt@gem_huc_copy@huc-copy:
> - fi-kbl-8809g: NOTRUN -> [SKIP][11] ([i915#2190])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
> - fi-skl-6600u: NOTRUN -> [SKIP][12] ([i915#2190])
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_lmem_swapping@basic:
> - bat-twl-2: NOTRUN -> [SKIP][13] ([i915#10213] / [i915#11671]) +3 other tests skip
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@gem_lmem_swapping@basic.html
>
> * igt@gem_lmem_swapping@parallel-random-engines:
> - bat-adls-6: NOTRUN -> [SKIP][14] ([i915#4613]) +3 other tests skip
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html
> - fi-kbl-8809g: NOTRUN -> [SKIP][15] ([i915#4613]) +3 other tests skip
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html
> - bat-apl-1: NOTRUN -> [SKIP][16] +3 other tests skip
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@gem_lmem_swapping@parallel-random-engines.html
>
> * igt@gem_lmem_swapping@random-engines:
> - fi-skl-6600u: NOTRUN -> [SKIP][17] ([i915#4613]) +3 other tests skip
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html
>
> * igt@gem_tiled_pread_basic:
> - bat-twl-2: NOTRUN -> [SKIP][18] ([i915#11031])
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@gem_tiled_pread_basic.html
>
> * igt@i915_pm_rps@basic-api:
> - bat-twl-2: NOTRUN -> [SKIP][19] ([i915#10209] / [i915#11681])
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@i915_pm_rps@basic-api.html
>
> * igt@i915_selftest@live@workarounds:
> - bat-mtlp-6: [PASS][20] -> [DMESG-FAIL][21] ([i915#12061]) +1 other test dmesg-fail
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - bat-twl-2: NOTRUN -> [SKIP][22] ([i915#11030] / [i915#11731]) +1 other test skip
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_dsc@dsc-basic:
> - fi-kbl-8809g: NOTRUN -> [SKIP][23] +62 other tests skip
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
> - fi-skl-6600u: NOTRUN -> [SKIP][24] +10 other tests skip
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@kms_dsc@dsc-basic.html
> - bat-twl-2: NOTRUN -> [SKIP][25] ([i915#9886])
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_dsc@dsc-basic.html
>
> * igt@kms_force_connector_basic@force-load-detect:
> - bat-twl-2: NOTRUN -> [SKIP][26] ([i915#11032])
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_force_connector_basic@force-load-detect.html
>
> * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
> - bat-dg2-11: [PASS][27] -> [SKIP][28] ([i915#9197]) +3 other tests skip
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
>
> * igt@kms_psr@psr-primary-mmap-gtt:
> - fi-pnv-d510: NOTRUN -> [SKIP][29] +33 other tests skip
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-pnv-d510/igt@kms_psr@psr-primary-mmap-gtt.html
>
> * igt@kms_setmode@basic-clone-single-crtc:
> - bat-twl-2: NOTRUN -> [SKIP][30] ([i915#8809])
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_setmode@basic-clone-single-crtc.html
>
> * igt@prime_vgem@basic-fence-read:
> - bat-twl-2: NOTRUN -> [SKIP][31] ([i915#10212] / [i915#3708])
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-fence-read.html
>
> * igt@prime_vgem@basic-read:
> - bat-twl-2: NOTRUN -> [SKIP][32] ([i915#10214] / [i915#3708])
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-read.html
>
> * igt@prime_vgem@basic-write:
> - bat-twl-2: NOTRUN -> [SKIP][33] ([i915#10216] / [i915#3708])
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-write.html
>
>
> #### Possible fixes ####
>
> * igt@core_hotunplug@unbind-rebind:
> - bat-adls-6: [ABORT][34] ([i915#13571]) -> [PASS][35]
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-adls-6/igt@core_hotunplug@unbind-rebind.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-adls-6/igt@core_hotunplug@unbind-rebind.html
>
> * igt@i915_selftest@live:
> - bat-mtlp-8: [DMESG-FAIL][36] ([i915#12061]) -> [PASS][37] +1 other test pass
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-8/igt@i915_selftest@live.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-8/igt@i915_selftest@live.html
> - fi-bsw-n3050: [DMESG-FAIL][38] ([i915#12435]) -> [PASS][39] +1 other test pass
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/fi-bsw-n3050/igt@i915_selftest@live.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-bsw-n3050/igt@i915_selftest@live.html
>
> * igt@i915_selftest@live@workarounds:
> - bat-mtlp-9: [DMESG-FAIL][40] ([i915#12061]) -> [PASS][41] +1 other test pass
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
>
> * igt@vgem_basic@unload:
> - bat-apl-1: [ABORT][42] -> [PASS][43]
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-apl-1/igt@vgem_basic@unload.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@vgem_basic@unload.html
>
>
> [i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
> [i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
> [i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
> [i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
> [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
> [i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
> [i915#11030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11030
> [i915#11031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11031
> [i915#11032]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11032
> [i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
> [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
> [i915#11731]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11731
> [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
> [i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
> [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
> [i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
> [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
> [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
> [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
> [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
> [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
> [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
> [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
> [i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_16265 -> Patchwork_144748v2
>
> CI-20190529: 20190529
> CI_DRM_16265: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_8270: 49751c5c11723262ec66e564c76503f74a9fa831 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_144748v2: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/index.html
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 34+ messages in thread
* RE: ✗ i915.CI.BAT: failure for drm/i915/display: conversions to struct intel_display (rev2)
2025-03-12 8:51 ` Jani Nikula
@ 2025-03-12 10:30 ` Ravali, JupallyX
0 siblings, 0 replies; 34+ messages in thread
From: Ravali, JupallyX @ 2025-03-12 10:30 UTC (permalink / raw)
To: i915-ci-infra@lists.freedesktop.org; +Cc: intel-gfx@lists.freedesktop.org
Hi,
https://patchwork.freedesktop.org/series/144748/ - Re-reported.
i915.CI.BAT - Re-reported.
Thanks,
Ravali.
-----Original Message-----
From: I915-ci-infra <i915-ci-infra-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
Sent: 12 March 2025 14:22
To: I915-ci-infra@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ i915.CI.BAT: failure for drm/i915/display: conversions to struct intel_display (rev2)
On Tue, 11 Mar 2025, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: drm/i915/display: conversions to struct intel_display (rev2)
> URL : https://patchwork.freedesktop.org/series/144748/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_16265 -> Patchwork_144748v2
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_144748v2 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_144748v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/index.html
>
> Participating hosts (44 -> 43)
> ------------------------------
>
> Missing (1): fi-snb-2520m
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_144748v2:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_pm_rpm@module-reload:
> - bat-rpls-4: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-rpls-4
> /igt@i915_pm_rpm@module-reload.html
Seems unrelated.
>
> * igt@kms_addfb_basic@too-high:
> - fi-kbl-8809g: NOTRUN -> [FAIL][3] +3 other tests fail
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-880
> 9g/igt@kms_addfb_basic@too-high.html
>
> * igt@kms_force_connector_basic@force-connector-state:
> - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][4]
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-880
> 9g/igt@kms_force_connector_basic@force-connector-state.html
>
> * igt@kms_force_connector_basic@force-edid:
> - fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][5]
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-880
> 9g/igt@kms_force_connector_basic@force-edid.html
We seem to be probing amdgpu again for fi-kbl-8809g. Weren't we supposed to block that?
Please fix/re-report.
BR,
Jani.
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_144748v2 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@core_auth@basic-auth:
> - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][6] ([i915#10462]) +1 other test dmesg-warn
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-880
> 9g/igt@core_auth@basic-auth.html
>
> * igt@debugfs_test@basic-hwmon:
> - bat-twl-2: NOTRUN -> [SKIP][7] ([i915#9318])
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@debugfs_test@basic-hwmon.html
>
> * igt@dmabuf@all-tests:
> - fi-pnv-d510: NOTRUN -> [INCOMPLETE][8] ([i915#12904]) +1 other test incomplete
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-pnv-d510/igt@dmabuf@all-tests.html
> - bat-apl-1: NOTRUN -> [INCOMPLETE][9] ([i915#12904]) +1 other test incomplete
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/
> igt@dmabuf@all-tests.html
>
> * igt@fbdev@info:
> - fi-kbl-8809g: NOTRUN -> [SKIP][10] ([i915#1849])
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-880
> 9g/igt@fbdev@info.html
>
> * igt@gem_huc_copy@huc-copy:
> - fi-kbl-8809g: NOTRUN -> [SKIP][11] ([i915#2190])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
> - fi-skl-6600u: NOTRUN -> [SKIP][12] ([i915#2190])
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-660
> 0u/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_lmem_swapping@basic:
> - bat-twl-2: NOTRUN -> [SKIP][13] ([i915#10213] / [i915#11671]) +3 other tests skip
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@gem_lmem_swapping@basic.html
>
> * igt@gem_lmem_swapping@parallel-random-engines:
> - bat-adls-6: NOTRUN -> [SKIP][14] ([i915#4613]) +3 other tests skip
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html
> - fi-kbl-8809g: NOTRUN -> [SKIP][15] ([i915#4613]) +3 other tests skip
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html
> - bat-apl-1: NOTRUN -> [SKIP][16] +3 other tests skip
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/
> igt@gem_lmem_swapping@parallel-random-engines.html
>
> * igt@gem_lmem_swapping@random-engines:
> - fi-skl-6600u: NOTRUN -> [SKIP][17] ([i915#4613]) +3 other tests skip
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-660
> 0u/igt@gem_lmem_swapping@random-engines.html
>
> * igt@gem_tiled_pread_basic:
> - bat-twl-2: NOTRUN -> [SKIP][18] ([i915#11031])
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@gem_tiled_pread_basic.html
>
> * igt@i915_pm_rps@basic-api:
> - bat-twl-2: NOTRUN -> [SKIP][19] ([i915#10209] / [i915#11681])
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@i915_pm_rps@basic-api.html
>
> * igt@i915_selftest@live@workarounds:
> - bat-mtlp-6: [PASS][20] -> [DMESG-FAIL][21] ([i915#12061]) +1 other test dmesg-fail
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-6
> /igt@i915_selftest@live@workarounds.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - bat-twl-2: NOTRUN -> [SKIP][22] ([i915#11030] / [i915#11731]) +1 other test skip
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_dsc@dsc-basic:
> - fi-kbl-8809g: NOTRUN -> [SKIP][23] +62 other tests skip
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
> - fi-skl-6600u: NOTRUN -> [SKIP][24] +10 other tests skip
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@kms_dsc@dsc-basic.html
> - bat-twl-2: NOTRUN -> [SKIP][25] ([i915#9886])
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@kms_dsc@dsc-basic.html
>
> * igt@kms_force_connector_basic@force-load-detect:
> - bat-twl-2: NOTRUN -> [SKIP][26] ([i915#11032])
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@kms_force_connector_basic@force-load-detect.html
>
> * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
> - bat-dg2-11: [PASS][27] -> [SKIP][28] ([i915#9197]) +3 other tests skip
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-dg2-11
> /igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
>
> * igt@kms_psr@psr-primary-mmap-gtt:
> - fi-pnv-d510: NOTRUN -> [SKIP][29] +33 other tests skip
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-pnv-d51
> 0/igt@kms_psr@psr-primary-mmap-gtt.html
>
> * igt@kms_setmode@basic-clone-single-crtc:
> - bat-twl-2: NOTRUN -> [SKIP][30] ([i915#8809])
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@kms_setmode@basic-clone-single-crtc.html
>
> * igt@prime_vgem@basic-fence-read:
> - bat-twl-2: NOTRUN -> [SKIP][31] ([i915#10212] / [i915#3708])
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@prime_vgem@basic-fence-read.html
>
> * igt@prime_vgem@basic-read:
> - bat-twl-2: NOTRUN -> [SKIP][32] ([i915#10214] / [i915#3708])
> [32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@prime_vgem@basic-read.html
>
> * igt@prime_vgem@basic-write:
> - bat-twl-2: NOTRUN -> [SKIP][33] ([i915#10216] / [i915#3708])
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/
> igt@prime_vgem@basic-write.html
>
>
> #### Possible fixes ####
>
> * igt@core_hotunplug@unbind-rebind:
> - bat-adls-6: [ABORT][34] ([i915#13571]) -> [PASS][35]
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-adls-6/igt@core_hotunplug@unbind-rebind.html
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-adls-6
> /igt@core_hotunplug@unbind-rebind.html
>
> * igt@i915_selftest@live:
> - bat-mtlp-8: [DMESG-FAIL][36] ([i915#12061]) -> [PASS][37] +1 other test pass
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-8/igt@i915_selftest@live.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-8/igt@i915_selftest@live.html
> - fi-bsw-n3050: [DMESG-FAIL][38] ([i915#12435]) -> [PASS][39] +1 other test pass
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/fi-bsw-n3050/igt@i915_selftest@live.html
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-bsw-n30
> 50/igt@i915_selftest@live.html
>
> * igt@i915_selftest@live@workarounds:
> - bat-mtlp-9: [DMESG-FAIL][40] ([i915#12061]) -> [PASS][41] +1 other test pass
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-9
> /igt@i915_selftest@live@workarounds.html
>
> * igt@vgem_basic@unload:
> - bat-apl-1: [ABORT][42] -> [PASS][43]
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-apl-1/igt@vgem_basic@unload.html
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/
> igt@vgem_basic@unload.html
>
>
> [i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
> [i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
> [i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
> [i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
> [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
> [i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
> [i915#11030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11030
> [i915#11031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11031
> [i915#11032]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11032
> [i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
> [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
> [i915#11731]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11731
> [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
> [i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
> [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
> [i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
> [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
> [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
> [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
> [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
> [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
> [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
> [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
> [i915#9886]:
> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_16265 -> Patchwork_144748v2
>
> CI-20190529: 20190529
> CI_DRM_16265: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_8270: 49751c5c11723262ec66e564c76503f74a9fa831 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_144748v2: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/index.html
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 34+ messages in thread
* ✓ i915.CI.BAT: success for drm/i915/display: conversions to struct intel_display (rev2)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (12 preceding siblings ...)
2025-03-11 22:40 ` ✗ i915.CI.BAT: failure " Patchwork
@ 2025-03-12 9:54 ` Patchwork
2025-03-13 14:50 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversions to struct intel_display (rev3) Patchwork
` (4 subsequent siblings)
18 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2025-03-12 9:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12437 bytes --]
== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/144748/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16265 -> Patchwork_144748v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/index.html
Participating hosts (44 -> 43)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_144748v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_auth@basic-auth:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][1] ([i915#10462]) +1 other test dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@core_auth@basic-auth.html
* igt@debugfs_test@basic-hwmon:
- bat-twl-2: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@debugfs_test@basic-hwmon.html
* igt@dmabuf@all-tests:
- fi-pnv-d510: NOTRUN -> [INCOMPLETE][3] ([i915#12904]) +1 other test incomplete
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-pnv-d510/igt@dmabuf@all-tests.html
- bat-apl-1: NOTRUN -> [INCOMPLETE][4] ([i915#12904]) +1 other test incomplete
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@dmabuf@all-tests.html
* igt@fbdev@info:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([i915#1849])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@fbdev@info.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-twl-2: NOTRUN -> [SKIP][8] ([i915#10213] / [i915#11671]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adls-6: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-kbl-8809g: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html
- bat-apl-1: NOTRUN -> [SKIP][11] +3 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-6600u: NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html
* igt@gem_tiled_pread_basic:
- bat-twl-2: NOTRUN -> [SKIP][13] ([i915#11031])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rpm@module-reload:
- bat-rpls-4: [PASS][14] -> [FAIL][15] ([i915#13901])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
* igt@i915_pm_rps@basic-api:
- bat-twl-2: NOTRUN -> [SKIP][16] ([i915#10209] / [i915#11681])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [PASS][17] -> [DMESG-FAIL][18] ([i915#12061]) +1 other test dmesg-fail
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][19] ([i915#13903]) +2 other tests fail
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-twl-2: NOTRUN -> [SKIP][20] ([i915#11030] / [i915#11731]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][21] +62 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
- fi-skl-6600u: NOTRUN -> [SKIP][22] +10 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-skl-6600u/igt@kms_dsc@dsc-basic.html
- bat-twl-2: NOTRUN -> [SKIP][23] ([i915#9886])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][24] ([i915#13905])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][25] ([i915#13905])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-twl-2: NOTRUN -> [SKIP][26] ([i915#11032])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-8809g: NOTRUN -> [FAIL][27] ([i915#13904])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-kbl-8809g/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][28] -> [SKIP][29] ([i915#9197]) +3 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_psr@psr-primary-mmap-gtt:
- fi-pnv-d510: NOTRUN -> [SKIP][30] +33 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-pnv-d510/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-twl-2: NOTRUN -> [SKIP][31] ([i915#8809])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-twl-2: NOTRUN -> [SKIP][32] ([i915#10212] / [i915#3708])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- bat-twl-2: NOTRUN -> [SKIP][33] ([i915#10214] / [i915#3708])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-twl-2: NOTRUN -> [SKIP][34] ([i915#10216] / [i915#3708])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-twl-2/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- bat-adls-6: [ABORT][35] ([i915#13571]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-adls-6/igt@core_hotunplug@unbind-rebind.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-adls-6/igt@core_hotunplug@unbind-rebind.html
* igt@i915_selftest@live:
- bat-mtlp-8: [DMESG-FAIL][37] ([i915#12061]) -> [PASS][38] +1 other test pass
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-8/igt@i915_selftest@live.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-8/igt@i915_selftest@live.html
- fi-bsw-n3050: [DMESG-FAIL][39] ([i915#12435]) -> [PASS][40] +1 other test pass
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/fi-bsw-n3050/igt@i915_selftest@live.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/fi-bsw-n3050/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-9: [DMESG-FAIL][41] ([i915#12061]) -> [PASS][42] +1 other test pass
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
* igt@vgem_basic@unload:
- bat-apl-1: [ABORT][43] ([i915#13898]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16265/bat-apl-1/igt@vgem_basic@unload.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/bat-apl-1/igt@vgem_basic@unload.html
[i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
[i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
[i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
[i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
[i915#11030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11030
[i915#11031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11031
[i915#11032]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11032
[i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11731]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11731
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
[i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
[i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
[i915#13898]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13898
[i915#13901]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13901
[i915#13903]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13903
[i915#13904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13904
[i915#13905]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13905
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_16265 -> Patchwork_144748v2
CI-20190529: 20190529
CI_DRM_16265: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8270: 49751c5c11723262ec66e564c76503f74a9fa831 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_144748v2: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v2/index.html
[-- Attachment #2: Type: text/html, Size: 14448 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversions to struct intel_display (rev3)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (13 preceding siblings ...)
2025-03-12 9:54 ` ✓ i915.CI.BAT: success " Patchwork
@ 2025-03-13 14:50 ` Patchwork
2025-03-13 14:50 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
18 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2025-03-13 14:50 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev3)
URL : https://patchwork.freedesktop.org/series/144748/
State : warning
== Summary ==
Error: dim checkpatch failed
17fd035c4408 drm/i915/color: prefer display->platform.<platform> checks
e7724aa2207f drm/i915/connector: convert intel_connector.c to struct intel_display
a31f349088c6 drm/i915/hotplug: convert intel_hotplug.[ch] to struct intel_display
456011e0d5a4 drm/i915/hotplug: convert hotplug debugfs to struct intel_display
e1931fd12293 drm/i915/hotplug: convert hotplug irq handling to intel_de_*()
b7307572fe75 drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct intel_display
c915913fcdde drm/i915/irq: convert intel_display_irq.[ch] interfaces to struct intel_display
-:857: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#857: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:74:
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-:858: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#858: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:75:
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
total: 0 errors, 2 warnings, 0 checks, 1501 lines checked
c62905c8a99d drm/i915/irq: convert rest of intel_display_irq.[ch] to struct intel_display
d0c338aa0fa3 drm/i915/display: rename I915_HAS_HOTPLUG() to HAS_HOTPLUG
^ permalink raw reply [flat|nested] 34+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915/display: conversions to struct intel_display (rev3)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (14 preceding siblings ...)
2025-03-13 14:50 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversions to struct intel_display (rev3) Patchwork
@ 2025-03-13 14:50 ` Patchwork
2025-03-13 15:14 ` ✓ i915.CI.BAT: success " Patchwork
` (2 subsequent siblings)
18 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2025-03-13 14:50 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev3)
URL : https://patchwork.freedesktop.org/series/144748/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 34+ messages in thread* ✓ i915.CI.BAT: success for drm/i915/display: conversions to struct intel_display (rev3)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (15 preceding siblings ...)
2025-03-13 14:50 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2025-03-13 15:14 ` Patchwork
2025-03-14 21:40 ` ✗ i915.CI.Full: failure " Patchwork
2025-03-19 14:45 ` Patchwork
18 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2025-03-13 15:14 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev3)
URL : https://patchwork.freedesktop.org/series/144748/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16280 -> Patchwork_144748v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/index.html
Participating hosts (43 -> 42)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_144748v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@info:
- fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#1849])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/fi-kbl-8809g/igt@fbdev@info.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-6600u: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html
* igt@i915_pm_rpm@module-reload:
- bat-dg1-7: [PASS][6] -> [FAIL][7] ([i915#13901])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@workarounds:
- bat-arls-5: [PASS][8] -> [DMESG-FAIL][9] ([i915#12061]) +1 other test dmesg-fail
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/bat-arls-5/igt@i915_selftest@live@workarounds.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/bat-arls-5/igt@i915_selftest@live@workarounds.html
- bat-arls-6: [PASS][10] -> [DMESG-FAIL][11] ([i915#12061]) +1 other test dmesg-fail
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/bat-arls-6/igt@i915_selftest@live@workarounds.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/bat-arls-6/igt@i915_selftest@live@workarounds.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][12] +34 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
- fi-skl-6600u: NOTRUN -> [SKIP][13] +9 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/fi-skl-6600u/igt@kms_dsc@dsc-basic.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][14] -> [SKIP][15] ([i915#9197]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#13901]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13901
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
Build changes
-------------
* Linux: CI_DRM_16280 -> Patchwork_144748v3
CI-20190529: 20190529
CI_DRM_16280: 9fe68375ef4ccae6bc9ba01bd5cbdfb047fd8402 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8273: 5d806121f1cfb38fe7cc4d528d81feb1c11274b1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_144748v3: 9fe68375ef4ccae6bc9ba01bd5cbdfb047fd8402 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/index.html
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^ permalink raw reply [flat|nested] 34+ messages in thread* ✗ i915.CI.Full: failure for drm/i915/display: conversions to struct intel_display (rev3)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (16 preceding siblings ...)
2025-03-13 15:14 ` ✓ i915.CI.BAT: success " Patchwork
@ 2025-03-14 21:40 ` Patchwork
2025-03-19 14:45 ` Patchwork
18 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2025-03-14 21:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev3)
URL : https://patchwork.freedesktop.org/series/144748/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16280_full -> Patchwork_144748v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_144748v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_144748v3_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 10)
------------------------------
Missing (1): shard-snb-0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_144748v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp4:
- shard-dg2: [PASS][1] -> [FAIL][2] +1 other test fail
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp4.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp4.html
#### Warnings ####
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [FAIL][3] ([i915#5138]) -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
New tests
---------
New tests have been introduced between CI_DRM_16280_full and Patchwork_144748v3_full:
### New IGT tests (25) ###
* igt@i915_pm_rps@basic-wc-cpu-active:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@basic-write-cpu-read-gtt:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@ctm-signed:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@cursor-sliding-512x170:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@dp-mst-type-1:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@fork-simple-once:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@host-signal-ordered:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@intel-max-src-size:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@invalid-bsd1-flag-on-blt:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@invalid-buffer:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@multi-wait-all-for-submit-signaled:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@multi-wait-for-submit-available-submitted:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@noreloc:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@plane-all-transition-fencing:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@plane-properties-atomic:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@planes-upscale-20x20-downscale-factor-0-5:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@psr-1p-primscrn-indfb-pgflip-blt:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@psr-2p-scndscrn-cur-indfb-onoff:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@rs-invalid:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@test_reprime:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@tiling-x:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@verify-pxp-key-change-after-suspend-resume:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@x-tiled:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in Patchwork_144748v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8411])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-tglu: NOTRUN -> [SKIP][6] ([i915#11078])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@device_reset@unbind-cold-reset-rebind.html
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#11078])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@device_reset@unbind-cold-reset-rebind.html
* igt@device_reset@unbind-reset-rebind:
- shard-tglu: [PASS][8] -> [ABORT][9] ([i915#12817] / [i915#5507])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-7/igt@device_reset@unbind-reset-rebind.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-4/igt@device_reset@unbind-reset-rebind.html
* igt@drm_fdinfo@busy-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8414]) +6 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@drm_fdinfo@busy-check-all@ccs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg2-9: NOTRUN -> [SKIP][11] ([i915#8414])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@drm_fdinfo@virtual-busy-all.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-dg2: NOTRUN -> [SKIP][12] ([i915#8414])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@gem_busy@semaphore:
- shard-dg2-9: NOTRUN -> [SKIP][13] ([i915#3936])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_busy@semaphore.html
* igt@gem_caching@reads:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#4873])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_caching@reads.html
* igt@gem_ccs@block-copy-compressed:
- shard-tglu-1: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#9323])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-tglu: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#9323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu: NOTRUN -> [SKIP][17] ([i915#9323])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ccs@suspend-resume:
- shard-dg2: [PASS][18] -> [INCOMPLETE][19] ([i915#13356])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@gem_ccs@suspend-resume.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_ccs@suspend-resume.html
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#9323])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_ccs@suspend-resume.html
- shard-tglu-1: NOTRUN -> [SKIP][21] ([i915#9323])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_ccs@suspend-resume.html
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
- shard-dg2: [PASS][22] -> [INCOMPLETE][23] ([i915#12392] / [i915#13356])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#7697])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#8555]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@legacy-engines-cleanup:
- shard-snb: NOTRUN -> [SKIP][26] ([i915#1099]) +2 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@gem_ctx_persistence@legacy-engines-cleanup.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs1:
- shard-dg2-9: NOTRUN -> [SKIP][27] ([i915#5882]) +7 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs1.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg2-9: NOTRUN -> [SKIP][28] ([i915#280])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_ctx_sseu@invalid-sseu.html
- shard-tglu: NOTRUN -> [SKIP][29] ([i915#280])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglu-1: NOTRUN -> [SKIP][30] ([i915#280])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@reset-stress:
- shard-snb: NOTRUN -> [FAIL][31] ([i915#8898])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg2-9: NOTRUN -> [SKIP][32] ([i915#4771])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-rkl: NOTRUN -> [SKIP][33] ([i915#4525]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-tglu-1: NOTRUN -> [SKIP][34] ([i915#4525])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-tglu: NOTRUN -> [SKIP][35] ([i915#4525])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@sliced:
- shard-dg2-9: NOTRUN -> [SKIP][36] ([i915#4812])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_capture@capture-invisible:
- shard-dg2-9: NOTRUN -> [SKIP][37] ([i915#6334]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_capture@capture-recoverable:
- shard-rkl: NOTRUN -> [SKIP][38] ([i915#6344])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#3539] / [i915#4852])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2-9: NOTRUN -> [SKIP][40] ([i915#3539] / [i915#4852]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_reloc@basic-gtt-cpu:
- shard-dg2-9: NOTRUN -> [SKIP][41] ([i915#3281]) +1 other test skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_reloc@basic-gtt-cpu.html
* igt@gem_exec_reloc@basic-range-active:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#3281]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_exec_reloc@basic-range-active.html
* igt@gem_exec_reloc@basic-softpin:
- shard-rkl: NOTRUN -> [SKIP][43] ([i915#3281]) +8 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_exec_reloc@basic-softpin.html
* igt@gem_exec_reloc@basic-wc:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#3281]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain:
- shard-dg2-9: NOTRUN -> [SKIP][45] ([i915#4537] / [i915#4812])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_schedule@preempt-queue-contexts-chain.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4537] / [i915#4812])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#7276])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s3-devices:
- shard-dg1: [PASS][48] -> [DMESG-WARN][49] ([i915#4423]) +2 other tests dmesg-warn
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-17/igt@gem_exec_suspend@basic-s3-devices.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-14/igt@gem_exec_suspend@basic-s3-devices.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4860])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][51] ([i915#2190])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-tglu: NOTRUN -> [SKIP][52] ([i915#4613] / [i915#7582])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-tglu: NOTRUN -> [SKIP][53] ([i915#4613]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#4613]) +2 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglu-1: NOTRUN -> [SKIP][55] ([i915#4613]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_lmem_swapping@parallel-random.html
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#4613])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][57] -> [TIMEOUT][58] ([i915#5493]) +1 other test timeout
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_media_fill@media-fill:
- shard-dg2-9: NOTRUN -> [SKIP][59] ([i915#8289])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_media_fill@media-fill.html
* igt@gem_mmap@bad-size:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#4083]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@gem_mmap@bad-size.html
* igt@gem_mmap_gtt@basic-copy:
- shard-dg2-9: NOTRUN -> [SKIP][61] ([i915#4077]) +4 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_mmap_gtt@basic-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-mtlp: NOTRUN -> [SKIP][62] ([i915#4077]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#4077]) +2 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@gem_mmap_gtt@medium-copy-odd:
- shard-rkl: [PASS][64] -> [DMESG-WARN][65] ([i915#12917] / [i915#12964])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_mmap_gtt@medium-copy-odd.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@gem_mmap_gtt@medium-copy-odd.html
* igt@gem_mmap_wc@read-write-distinct:
- shard-dg2-9: NOTRUN -> [SKIP][66] ([i915#4083]) +3 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_mmap_wc@read-write-distinct.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg2-9: NOTRUN -> [SKIP][67] ([i915#3282]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_pwrite@basic-exhaustion:
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#3282]) +4 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-regular-context-1:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#4270])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@create-regular-context-2:
- shard-dg2-9: NOTRUN -> [SKIP][70] ([i915#4270])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_pxp@create-regular-context-2.html
* igt@gem_pxp@create-valid-protected-context:
- shard-rkl: [PASS][71] -> [TIMEOUT][72] ([i915#12964])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_pxp@create-valid-protected-context.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-mtlp: [PASS][73] -> [ABORT][74] ([i915#13193])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-7/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-rkl: [PASS][75] -> [TIMEOUT][76] ([i915#12917] / [i915#12964]) +1 other test timeout
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_pxp@verify-pxp-stale-buf-execution.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_readwrite@beyond-eob:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#3282]) +2 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@gem_readwrite@beyond-eob.html
* igt@gem_render_copy@y-tiled-ccs-to-linear:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#5190] / [i915#8428]) +5 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_render_copy@y-tiled-ccs-to-linear.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][79] ([i915#5190] / [i915#8428]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: NOTRUN -> [SKIP][80] ([i915#8411]) +1 other test skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#4079])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2-9: NOTRUN -> [SKIP][82] ([i915#4885])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_swapping@non-threaded:
- shard-rkl: [PASS][83] -> [FAIL][84] ([i915#12941])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_tiled_swapping@non-threaded.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_unfence_active_buffers:
- shard-dg2-9: NOTRUN -> [SKIP][85] ([i915#4879])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@coherency-sync:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#3297])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: NOTRUN -> [SKIP][87] ([i915#3297]) +2 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-rkl: NOTRUN -> [SKIP][88] ([i915#3282] / [i915#3297])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@relocations:
- shard-dg2-9: NOTRUN -> [SKIP][89] ([i915#3281] / [i915#3297])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_userptr_blits@relocations.html
* igt@gem_userptr_blits@sd-probe:
- shard-dg2-9: NOTRUN -> [SKIP][90] ([i915#3297] / [i915#4958])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_userptr_blits@sd-probe.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-mtlp: NOTRUN -> [SKIP][91] ([i915#3297]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_userptr_blits@unsync-overlap.html
- shard-tglu-1: NOTRUN -> [SKIP][92] ([i915#3297])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_userptr_blits@unsync-overlap.html
* igt@gen3_render_tiledx_blits:
- shard-dg2: NOTRUN -> [SKIP][93] +4 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gen3_render_tiledx_blits.html
* igt@gen7_exec_parse@cmd-crossing-page:
- shard-dg2-9: NOTRUN -> [SKIP][94] +1 other test skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gen7_exec_parse@cmd-crossing-page.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-snb: NOTRUN -> [SKIP][95] +109 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-single:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#2527]) +1 other test skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-param:
- shard-dg2-9: NOTRUN -> [SKIP][97] ([i915#2856]) +1 other test skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gen9_exec_parse@bb-start-param.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#2856]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gen9_exec_parse@shadow-peek.html
* igt@gen9_exec_parse@unaligned-access:
- shard-tglu: NOTRUN -> [SKIP][99] ([i915#2527] / [i915#2856]) +2 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@gen9_exec_parse@unaligned-access.html
* igt@gen9_exec_parse@valid-registers:
- shard-tglu-1: NOTRUN -> [SKIP][100] ([i915#2527] / [i915#2856]) +1 other test skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gen9_exec_parse@valid-registers.html
- shard-mtlp: NOTRUN -> [SKIP][101] ([i915#2856])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@load:
- shard-glk: ([PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124]) -> ([PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [DMESG-WARN][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145]) ([i915#118])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk5/igt@i915_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk9/igt@i915_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk7/igt@i915_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk4/igt@i915_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk4/igt@i915_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@i915_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk1/igt@i915_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk9/igt@i915_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk5/igt@i915_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk3/igt@i915_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@i915_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk7/igt@i915_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk6/igt@i915_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk8/igt@i915_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk1/igt@i915_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk8/igt@i915_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk6/igt@i915_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk8/igt@i915_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk7/igt@i915_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@i915_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk1/igt@i915_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk5/igt@i915_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk3/igt@i915_module_load@load.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk5/igt@i915_module_load@load.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk5/igt@i915_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@i915_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk6/igt@i915_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk3/igt@i915_module_load@load.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk2/igt@i915_module_load@load.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@i915_module_load@load.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk3/igt@i915_module_load@load.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk6/igt@i915_module_load@load.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk3/igt@i915_module_load@load.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk6/igt@i915_module_load@load.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk2/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [PASS][146] -> [ABORT][147] ([i915#9820])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
- shard-snb: [PASS][148] -> [ABORT][149] ([i915#9820])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_module_load@resize-bar:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#6412])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#8399])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_freq_api@freq-reset:
- shard-tglu-1: NOTRUN -> [SKIP][152] ([i915#8399])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@i915_pm_freq_api@freq-reset.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-rkl: [PASS][153] -> [SKIP][154] ([i915#13328]) +1 other test skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@i915_pm_rpm@debugfs-forcewake-user.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@i915_pm_rps@engine-order:
- shard-glk: [PASS][155] -> [FAIL][156] ([i915#13547])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk4/igt@i915_pm_rps@engine-order.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk5/igt@i915_pm_rps@engine-order.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][157] -> [INCOMPLETE][158] ([i915#13729] / [i915#13821])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb7/igt@i915_pm_rps@reset.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb7/igt@i915_pm_rps@reset.html
* igt@i915_power@sanity:
- shard-mtlp: [PASS][159] -> [SKIP][160] ([i915#7984])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-8/igt@i915_power@sanity.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-6/igt@i915_power@sanity.html
* igt@i915_selftest@mock@memory_region:
- shard-dg2: NOTRUN -> [DMESG-WARN][161] ([i915#9311]) +1 other test dmesg-warn
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@i915_selftest@mock@memory_region.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][162] ([i915#8709]) +1 other test skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-tglu: NOTRUN -> [SKIP][163] ([i915#8709]) +3 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@invalid-async-flip:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#12967] / [i915#6228])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-dg1: [PASS][165] -> [FAIL][166] ([i915#5956])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-13/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-16/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][167] ([i915#5956])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-16/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-tglu-1: NOTRUN -> [SKIP][168] ([i915#5286]) +3 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][169] ([i915#5286]) +6 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-tglu: NOTRUN -> [SKIP][170] ([i915#5286]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][171] ([i915#3638]) +3 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][172] +3 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-dg2-9: NOTRUN -> [SKIP][173] ([i915#4538] / [i915#5190]) +5 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#4538] / [i915#5190]) +4 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#5190]) +1 other test skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#6187])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-c-dp-3:
- shard-dg2: NOTRUN -> [SKIP][177] ([i915#10307] / [i915#6095]) +132 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-c-dp-3.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][178] ([i915#6095]) +49 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][179] ([i915#10307] / [i915#6095]) +39 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][180] ([i915#12313])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][181] ([i915#12313])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][182] ([i915#6095]) +92 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
- shard-glk: NOTRUN -> [SKIP][183] +26 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][184] ([i915#6095]) +4 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#12805])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][186] ([i915#6095]) +44 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#6095]) +20 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#12313])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#12313])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#6095]) +83 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-12/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3.html
* igt@kms_cdclk@mode-transition:
- shard-tglu-1: NOTRUN -> [SKIP][192] ([i915#3742])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#3742]) +1 other test skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#13783]) +3 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_audio@dp-audio:
- shard-tglu: NOTRUN -> [SKIP][195] ([i915#11151] / [i915#7828]) +5 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2-9: NOTRUN -> [SKIP][196] ([i915#11151] / [i915#7828]) +4 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#11151] / [i915#7828]) +3 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#11151] / [i915#7828]) +8 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-tglu-1: NOTRUN -> [SKIP][199] ([i915#11151] / [i915#7828]) +4 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@vga-hpd-after-suspend:
- shard-mtlp: NOTRUN -> [SKIP][200] ([i915#11151] / [i915#7828])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-tglu: NOTRUN -> [SKIP][201] ([i915#3116] / [i915#3299])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#3116])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-tglu-1: NOTRUN -> [SKIP][203] ([i915#3116] / [i915#3299])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-dg2-9: NOTRUN -> [SKIP][204] ([i915#7118] / [i915#9424])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0:
- shard-tglu: NOTRUN -> [SKIP][205] ([i915#6944] / [i915#9424]) +1 other test skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_content_protection@lic-type-0.html
- shard-dg2-9: NOTRUN -> [SKIP][206] ([i915#9424])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#9424]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#7118])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-rkl: NOTRUN -> [SKIP][209] ([i915#13049])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-tglu-1: NOTRUN -> [SKIP][210] ([i915#3555]) +4 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-dg2-9: NOTRUN -> [SKIP][211] ([i915#3555]) +1 other test skip
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-tglu: NOTRUN -> [SKIP][212] ([i915#3555]) +2 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-tglu-1: NOTRUN -> [SKIP][213] ([i915#13049]) +1 other test skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-mtlp: NOTRUN -> [SKIP][214] ([i915#3555] / [i915#8814])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-dg2-9: NOTRUN -> [SKIP][215] ([i915#13046] / [i915#5354]) +2 other tests skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][216] +19 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-dg2: NOTRUN -> [SKIP][217] ([i915#13046] / [i915#5354]) +2 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-tglu: NOTRUN -> [SKIP][218] +41 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-rkl: NOTRUN -> [SKIP][219] ([i915#9067])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][220] ([i915#9723])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@extended-mode-basic:
- shard-rkl: NOTRUN -> [SKIP][221] ([i915#13691])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-rkl: NOTRUN -> [SKIP][222] ([i915#3555] / [i915#3804])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][223] ([i915#3804])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_aux_dev:
- shard-dg2-9: NOTRUN -> [SKIP][224] ([i915#1257])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_dp_aux_dev.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-tglu-1: NOTRUN -> [SKIP][225] ([i915#13749])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-dg2: NOTRUN -> [SKIP][226] ([i915#13748])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_dp_link_training@uhbr-mst.html
- shard-tglu: NOTRUN -> [SKIP][227] ([i915#13748])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dp_link_training@uhbr-sst:
- shard-tglu-1: NOTRUN -> [SKIP][228] ([i915#13748])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_dp_link_training@uhbr-sst.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-rkl: NOTRUN -> [SKIP][229] ([i915#13707])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_dp_linktrain_fallback@dp-fallback.html
- shard-tglu-1: NOTRUN -> [SKIP][230] ([i915#13707])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_draw_crc@draw-method-render@xrgb2101010-untiled:
- shard-rkl: [PASS][231] -> [DMESG-WARN][232] ([i915#12964]) +7 other tests dmesg-warn
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-5/igt@kms_draw_crc@draw-method-render@xrgb2101010-untiled.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_draw_crc@draw-method-render@xrgb2101010-untiled.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg2: NOTRUN -> [SKIP][233] ([i915#3840] / [i915#9688])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2-9: NOTRUN -> [SKIP][234] ([i915#3840])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
- shard-tglu: NOTRUN -> [SKIP][235] ([i915#3840])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-tglu: NOTRUN -> [SKIP][236] ([i915#3840] / [i915#9053])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-dg2: NOTRUN -> [SKIP][237] ([i915#13798])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: NOTRUN -> [SKIP][238] ([i915#3955])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@dp-mst:
- shard-rkl: NOTRUN -> [SKIP][239] ([i915#9337])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-dg2: NOTRUN -> [SKIP][240] ([i915#658])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_feature_discovery@psr1.html
* igt@kms_feature_discovery@psr2:
- shard-tglu-1: NOTRUN -> [SKIP][241] ([i915#658])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_feature_discovery@psr2.html
- shard-rkl: NOTRUN -> [SKIP][242] ([i915#658])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [PASS][243] -> [FAIL][244] ([i915#11832]) +1 other test fail
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-rkl: NOTRUN -> [SKIP][245] ([i915#9934]) +7 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][246] ([i915#3637]) +1 other test skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-dg2-9: NOTRUN -> [SKIP][247] ([i915#9934]) +3 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@2x-plain-flip:
- shard-tglu: NOTRUN -> [SKIP][248] ([i915#3637]) +2 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
- shard-dg2: NOTRUN -> [SKIP][249] ([i915#9934]) +3 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-tglu-1: NOTRUN -> [SKIP][250] ([i915#3637]) +3 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][251] ([i915#2672] / [i915#3555] / [i915#8813]) +2 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][252] ([i915#2672] / [i915#8813])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][253] ([i915#2672]) +2 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][254] ([i915#2672]) +1 other test skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][255] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
- shard-tglu: NOTRUN -> [SKIP][256] ([i915#2672] / [i915#3555])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][257] ([i915#2587] / [i915#2672])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-rkl: NOTRUN -> [SKIP][258] ([i915#2672] / [i915#3555]) +2 other tests skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][259] ([i915#3555] / [i915#8810] / [i915#8813])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][260] ([i915#3555] / [i915#8810])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][261] ([i915#2672] / [i915#3555]) +2 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][262] ([i915#2587] / [i915#2672]) +2 other tests skip
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-dg2-9: NOTRUN -> [SKIP][263] ([i915#2672] / [i915#3555] / [i915#5190])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][264] ([i915#2672])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][265] ([i915#8708])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-dg2-9: NOTRUN -> [SKIP][266] ([i915#8708]) +5 other tests skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][267] ([i915#8708]) +13 other tests skip
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][268] ([i915#1825]) +3 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-rkl: NOTRUN -> [SKIP][269] ([i915#3023]) +23 other tests skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-dg2-9: NOTRUN -> [SKIP][270] ([i915#3458]) +7 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-tglu-1: NOTRUN -> [SKIP][271] +62 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt:
- shard-dg2-9: NOTRUN -> [SKIP][272] ([i915#5354]) +14 other tests skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-tglu-1: NOTRUN -> [SKIP][273] ([i915#9766])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][274] ([i915#3458]) +8 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][275] ([i915#10433] / [i915#3458])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][276] ([i915#1825]) +33 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][277] ([i915#5354]) +12 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch:
- shard-tglu-1: NOTRUN -> [SKIP][278] ([i915#3555] / [i915#8228]) +1 other test skip
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_hdr@bpc-switch.html
- shard-dg2: [PASS][279] -> [SKIP][280] ([i915#3555] / [i915#8228])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-11/igt@kms_hdr@bpc-switch.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-dg2: NOTRUN -> [SKIP][281] ([i915#3555] / [i915#8228])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-swap:
- shard-dg2-9: NOTRUN -> [SKIP][282] ([i915#3555] / [i915#8228])
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle-dpms:
- shard-rkl: NOTRUN -> [SKIP][283] ([i915#3555] / [i915#8228])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][284] ([i915#12388])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][285] ([i915#12394])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
- shard-mtlp: NOTRUN -> [SKIP][286] ([i915#10656])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-tglu: NOTRUN -> [SKIP][287] ([i915#12339])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-dg2-9: NOTRUN -> [SKIP][288] ([i915#12339])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][289] ([i915#4816])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_multiple@tiling-y:
- shard-dg2-9: NOTRUN -> [SKIP][290] ([i915#8806])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][291] ([i915#3555]) +8 other tests skip
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][292] ([i915#12247]) +13 other tests skip
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20:
- shard-dg2-9: NOTRUN -> [SKIP][293] ([i915#12247] / [i915#9423])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a:
- shard-dg2-9: NOTRUN -> [SKIP][294] ([i915#12247]) +3 other tests skip
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d:
- shard-tglu: NOTRUN -> [SKIP][295] ([i915#12247]) +17 other tests skip
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-tglu-1: NOTRUN -> [SKIP][296] ([i915#12247] / [i915#6953])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c:
- shard-tglu-1: NOTRUN -> [SKIP][297] ([i915#12247]) +8 other tests skip
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-tglu: NOTRUN -> [SKIP][298] ([i915#12247] / [i915#3555])
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_pm_backlight@bad-brightness:
- shard-rkl: NOTRUN -> [SKIP][299] ([i915#5354]) +1 other test skip
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-tglu: NOTRUN -> [SKIP][300] ([i915#9812])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-tglu-1: NOTRUN -> [SKIP][301] ([i915#9812])
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2: NOTRUN -> [SKIP][302] ([i915#9685])
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-rkl: NOTRUN -> [SKIP][303] ([i915#3828])
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: NOTRUN -> [SKIP][304] ([i915#9340])
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-tglu-1: NOTRUN -> [SKIP][305] ([i915#9519])
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][306] -> [SKIP][307] ([i915#9519]) +1 other test skip
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [PASS][308] -> [SKIP][309] ([i915#9519]) +1 other test skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][310] ([i915#9519]) +1 other test skip
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: NOTRUN -> [SKIP][311] ([i915#9519])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg2: NOTRUN -> [SKIP][312] ([i915#6524] / [i915#6805])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
- shard-snb: NOTRUN -> [SKIP][313] ([i915#11520]) +4 other tests skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
- shard-tglu: NOTRUN -> [SKIP][314] ([i915#11520]) +6 other tests skip
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][315] ([i915#11520]) +4 other tests skip
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
- shard-tglu-1: NOTRUN -> [SKIP][316] ([i915#11520]) +5 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][317] ([i915#9808])
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][318] ([i915#12316]) +2 other tests skip
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-dg2-9: NOTRUN -> [SKIP][319] ([i915#11520]) +4 other tests skip
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-rkl: NOTRUN -> [SKIP][320] ([i915#11520]) +6 other tests skip
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][321] ([i915#9683])
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@fbc-psr-no-drrs:
- shard-tglu: NOTRUN -> [SKIP][322] ([i915#9732]) +10 other tests skip
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_psr@fbc-psr-no-drrs.html
* igt@kms_psr@fbc-psr-primary-blt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][323] ([i915#9688]) +4 other tests skip
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_psr@fbc-psr-primary-blt@edp-1.html
* igt@kms_psr@fbc-psr2-suspend:
- shard-rkl: NOTRUN -> [SKIP][324] ([i915#1072] / [i915#9732]) +19 other tests skip
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_psr@fbc-psr2-suspend.html
* igt@kms_psr@pr-cursor-plane-onoff:
- shard-dg2-9: NOTRUN -> [SKIP][325] ([i915#1072] / [i915#9732]) +9 other tests skip
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_psr@pr-cursor-plane-onoff.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][326] ([i915#1072] / [i915#9732]) +9 other tests skip
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][327] ([i915#9732]) +14 other tests skip
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-dg2: NOTRUN -> [SKIP][328] ([i915#12755])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-tglu-1: NOTRUN -> [SKIP][329] ([i915#5289]) +1 other test skip
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
- shard-mtlp: NOTRUN -> [SKIP][330] ([i915#5289])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-tglu: NOTRUN -> [SKIP][331] ([i915#5289])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-dg2: NOTRUN -> [SKIP][332] ([i915#3555]) +3 other tests skip
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_selftest@drm_framebuffer:
- shard-tglu: NOTRUN -> [ABORT][333] ([i915#13179]) +1 other test abort
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_selftest@drm_framebuffer.html
* igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free:
- shard-dg2: NOTRUN -> [ABORT][334] ([i915#13179]) +1 other test abort
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-9: NOTRUN -> [SKIP][335] ([i915#8623])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vblank@wait-forked-busy@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [DMESG-WARN][336] ([i915#12964]) +8 other tests dmesg-warn
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_vblank@wait-forked-busy@pipe-a-hdmi-a-1.html
* igt@kms_vrr@lobf:
- shard-dg2-9: NOTRUN -> [SKIP][337] ([i915#11920])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_vrr@lobf.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-tglu-1: NOTRUN -> [SKIP][338] ([i915#9906])
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-check-output:
- shard-rkl: NOTRUN -> [SKIP][339] ([i915#2437]) +1 other test skip
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_writeback@writeback-check-output.html
- shard-tglu-1: NOTRUN -> [SKIP][340] ([i915#2437])
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][341] ([i915#2437] / [i915#9412]) +1 other test skip
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-tglu-1: NOTRUN -> [SKIP][342] ([i915#2437] / [i915#9412])
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@global-sseu-config:
- shard-dg2-9: NOTRUN -> [SKIP][343] ([i915#7387])
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@perf@global-sseu-config.html
* igt@perf@global-sseu-config-invalid:
- shard-dg2: NOTRUN -> [SKIP][344] ([i915#7387])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@perf@global-sseu-config-invalid.html
* igt@perf@mi-rpc:
- shard-rkl: NOTRUN -> [SKIP][345] ([i915#2434])
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@perf@mi-rpc.html
* igt@perf_pmu@busy-double-start@vecs0:
- shard-mtlp: [PASS][346] -> [FAIL][347] ([i915#4349])
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-6/igt@perf_pmu@busy-double-start@vecs0.html
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@perf_pmu@busy-double-start@vecs0.html
* igt@perf_pmu@enable-race@vecs0:
- shard-dg1: [PASS][348] -> [INCOMPLETE][349] ([i915#13520]) +1 other test incomplete
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-19/igt@perf_pmu@enable-race@vecs0.html
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-13/igt@perf_pmu@enable-race@vecs0.html
* igt@perf_pmu@invalid-init:
- shard-dg2-9: NOTRUN -> [FAIL][350] ([i915#13663])
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@perf_pmu@invalid-init.html
* igt@perf_pmu@rc6-all-gts:
- shard-rkl: NOTRUN -> [SKIP][351] ([i915#8516])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2-9: NOTRUN -> [SKIP][352] ([i915#8516])
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-tglu: NOTRUN -> [SKIP][353] ([i915#8516])
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> [SKIP][354] ([i915#3291] / [i915#3708])
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@prime_vgem@basic-read.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][355] ([i915#3708] / [i915#4077])
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg2-9: NOTRUN -> [SKIP][356] ([i915#3708])
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@prime_vgem@fence-flip-hang.html
* igt@prime_vgem@fence-read-hang:
- shard-dg2: NOTRUN -> [SKIP][357] ([i915#3708])
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@prime_vgem@fence-read-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-rkl: NOTRUN -> [SKIP][358] ([i915#9917])
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-tglu: NOTRUN -> [FAIL][359] ([i915#12910])
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
* igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-2:
- shard-tglu-1: NOTRUN -> [FAIL][360] ([i915#12910]) +8 other tests fail
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-2.html
#### Possible fixes ####
* igt@drm_fdinfo@busy:
- shard-rkl: [DMESG-WARN][361] ([i915#12964]) -> [PASS][362] +8 other tests pass
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-5/igt@drm_fdinfo@busy.html
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@drm_fdinfo@busy.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][363] ([i915#13427]) -> [PASS][364]
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-7/igt@gem_create@create-ext-cpu-access-big.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_persistence@engines-mixed-process:
- shard-mtlp: [ABORT][365] ([i915#13193]) -> [PASS][366] +2 other tests pass
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-7/igt@gem_ctx_persistence@engines-mixed-process.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@gem_ctx_persistence@engines-mixed-process.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-glk: [ABORT][367] ([i915#13592]) -> [PASS][368]
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk5/igt@i915_module_load@reload-with-fault-injection.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-dg1: [FAIL][369] ([i915#12518] / [i915#12766]) -> [PASS][370]
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-4:
- shard-dg1: [FAIL][371] ([i915#12518]) -> [PASS][372]
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-4.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-4.html
* igt@kms_cursor_crc@cursor-random-128x42:
- shard-dg1: [DMESG-WARN][373] ([i915#4423]) -> [PASS][374] +6 other tests pass
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-15/igt@kms_cursor_crc@cursor-random-128x42.html
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-17/igt@kms_cursor_crc@cursor-random-128x42.html
* igt@kms_cursor_crc@cursor-random-64x21:
- shard-rkl: [FAIL][375] ([i915#13566]) -> [PASS][376] +3 other tests pass
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-7/igt@kms_cursor_crc@cursor-random-64x21.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@kms_cursor_crc@cursor-random-64x21.html
* igt@kms_cursor_crc@cursor-sliding-128x42:
- shard-tglu: [FAIL][377] ([i915#13566]) -> [PASS][378] +5 other tests pass
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-3/igt@kms_cursor_crc@cursor-sliding-128x42.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_cursor_crc@cursor-sliding-128x42.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-snb: [SKIP][379] -> [PASS][380] +1 other test pass
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb5/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb5/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-dg2: [SKIP][381] ([i915#13749]) -> [PASS][382]
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-7/igt@kms_dp_link_training@non-uhbr-sst.html
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_flip@flip-vs-absolute-wf_vblank:
- shard-mtlp: [FAIL][383] -> [PASS][384] +5 other tests pass
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-1/igt@kms_flip@flip-vs-absolute-wf_vblank.html
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-6/igt@kms_flip@flip-vs-absolute-wf_vblank.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1:
- shard-tglu: [FAIL][385] -> [PASS][386] +2 other tests pass
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-4/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [FAIL][387] ([i915#13027]) -> [PASS][388] +1 other test pass
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-dg1: [FAIL][389] ([i915#13027]) -> [PASS][390]
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-18/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-12/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg2: [SKIP][391] ([i915#3555] / [i915#8228]) -> [PASS][392]
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@kms_hdr@bpc-switch-dpms.html
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2: [SKIP][393] ([i915#12388]) -> [PASS][394]
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-6/igt@kms_joiner@basic-force-big-joiner.html
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-rkl: [SKIP][395] ([i915#9519]) -> [PASS][396]
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-7/igt@kms_pm_rpm@dpms-non-lpsp.html
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][397] ([i915#9519]) -> [PASS][398]
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@perf_pmu@busy-double-start@vcs1:
- shard-mtlp: [FAIL][399] ([i915#4349]) -> [PASS][400]
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-6/igt@perf_pmu@busy-double-start@vcs1.html
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@perf_pmu@busy-double-start@vcs1.html
* igt@perf_pmu@busy-double-start@vecs0:
- shard-dg1: [FAIL][401] ([i915#4349]) -> [PASS][402]
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-17/igt@perf_pmu@busy-double-start@vecs0.html
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-17/igt@perf_pmu@busy-double-start@vecs0.html
#### Warnings ####
* igt@gem_eio@in-flight-suspend:
- shard-glk: [INCOMPLETE][403] ([i915#13197] / [i915#13390]) -> [INCOMPLETE][404] ([i915#13390])
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk8/igt@gem_eio@in-flight-suspend.html
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-mtlp: [ABORT][405] ([i915#7975]) -> [ABORT][406] ([i915#13193] / [i915#7975]) +1 other test abort
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-4/igt@gem_exec_suspend@basic-s4-devices.html
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_content_protection@srm:
- shard-dg2: [FAIL][407] ([i915#7173]) -> [SKIP][408] ([i915#7118])
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-11/igt@kms_content_protection@srm.html
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_content_protection@srm.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-glk: [INCOMPLETE][409] ([i915#12745] / [i915#4839]) -> [INCOMPLETE][410] ([i915#12314] / [i915#12745] / [i915#4839])
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@kms_flip@2x-flip-vs-suspend.html
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
- shard-glk: [INCOMPLETE][411] ([i915#4839]) -> [INCOMPLETE][412] ([i915#12314] / [i915#4839])
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-dg1: [SKIP][413] ([i915#4423] / [i915#8708]) -> [SKIP][414] ([i915#8708])
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-dg2: [SKIP][415] ([i915#3458]) -> [SKIP][416] ([i915#10433] / [i915#3458]) +1 other test skip
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
- shard-dg1: [SKIP][417] ([i915#3458]) -> [SKIP][418] ([i915#3458] / [i915#4423])
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-dg2: [SKIP][419] ([i915#10433] / [i915#3458]) -> [SKIP][420] ([i915#3458]) +1 other test skip
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-tglu: [SKIP][421] ([i915#1187] / [i915#12713]) -> [SKIP][422] ([i915#12713])
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-2/igt@kms_hdr@brightness-with-hdr.html
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-5/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [SKIP][423] ([i915#3361]) -> [FAIL][424] ([i915#9295])
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][425] ([i915#4281]) -> [SKIP][426] ([i915#3361])
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-rkl: [DMESG-WARN][427] ([i915#12964]) -> [SKIP][428] ([i915#9519])
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_psr@psr-cursor-mmap-gtt:
- shard-dg1: [SKIP][429] ([i915#1072] / [i915#4423] / [i915#9732]) -> [SKIP][430] ([i915#1072] / [i915#9732])
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-19/igt@kms_psr@psr-cursor-mmap-gtt.html
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-13/igt@kms_psr@psr-cursor-mmap-gtt.html
* igt@prime_mmap@test_aperture_limit:
- shard-dg2: [INCOMPLETE][431] ([i915#5493]) -> [WARN][432] ([i915#9351])
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@prime_mmap@test_aperture_limit.html
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@prime_mmap@test_aperture_limit.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][433] ([i915#5493]) -> [CRASH][434] ([i915#9351])
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/118
[i915#11832]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11832
[i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
[i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
[i915#12518]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12518
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
[i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12766
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12817
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12941]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12941
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#12967]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12967
[i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
[i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
[i915#13197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13197
[i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
[i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427
[i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
[i915#13547]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13547
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13592]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13592
[i915#13663]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13663
[i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
[i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
[i915#13729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13729
[i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
[i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
[i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
[i915#13798]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13798
[i915#13821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13821
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#4958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4958
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5507
[i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
[i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
[i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
[i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
[i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
[i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8898]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8898
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_16280 -> Patchwork_144748v3
CI-20190529: 20190529
CI_DRM_16280: 9fe68375ef4ccae6bc9ba01bd5cbdfb047fd8402 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8273: 5d806121f1cfb38fe7cc4d528d81feb1c11274b1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_144748v3: 9fe68375ef4ccae6bc9ba01bd5cbdfb047fd8402 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/index.html
[-- Attachment #2: Type: text/html, Size: 143365 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread* ✗ i915.CI.Full: failure for drm/i915/display: conversions to struct intel_display (rev3)
2025-03-11 18:00 [PATCH 0/9] drm/i915/display: conversions to struct intel_display Jani Nikula
` (17 preceding siblings ...)
2025-03-14 21:40 ` ✗ i915.CI.Full: failure " Patchwork
@ 2025-03-19 14:45 ` Patchwork
18 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2025-03-19 14:45 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 188876 bytes --]
== Series Details ==
Series: drm/i915/display: conversions to struct intel_display (rev3)
URL : https://patchwork.freedesktop.org/series/144748/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16280_full -> Patchwork_144748v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_144748v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_144748v3_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 12)
------------------------------
Additional (1): shard-dg2-set2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_144748v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1:
- shard-snb: [PASS][1] -> ([FAIL][2], [PASS][3]) +1 other test ( 1 fail, 1 pass )
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb7/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb2/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb4/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-dg2: [PASS][4] -> ([FAIL][5], [PASS][6])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_flip@flip-vs-blocking-wf-vblank.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp4:
- shard-dg2: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp4.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp4.html
#### Warnings ####
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [FAIL][9] ([i915#5138]) -> ([DMESG-FAIL][10], [DMESG-FAIL][11])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1:
- shard-tglu: [FAIL][12] -> ([FAIL][13], [PASS][14]) +1 other test ( 1 fail, 1 pass )
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-4/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1.html
New tests
---------
New tests have been introduced between CI_DRM_16280_full and Patchwork_144748v3_full:
### New IGT tests (25) ###
* igt@i915_pm_rps@basic-wc-cpu-active:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@basic-write-cpu-read-gtt:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@ctm-signed:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@cursor-sliding-512x170:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@dp-mst-type-1:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@fork-simple-once:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@host-signal-ordered:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@intel-max-src-size:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@invalid-bsd1-flag-on-blt:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@invalid-buffer:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@multi-wait-all-for-submit-signaled:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@multi-wait-for-submit-available-submitted:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@noreloc:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@plane-all-transition-fencing:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@plane-properties-atomic:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@planes-upscale-20x20-downscale-factor-0-5:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@psr-1p-primscrn-indfb-pgflip-blt:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@psr-2p-scndscrn-cur-indfb-onoff:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@rs-invalid:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@test_reprime:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@tiling-x:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@verify-pxp-key-change-after-suspend-resume:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@x-tiled:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in Patchwork_144748v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg2: NOTRUN -> ([SKIP][15], [SKIP][16]) ([i915#8411])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@api_intel_bb@object-reloc-purge-cache.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@device_reset@cold-reset-bound:
- shard-dg2-9: NOTRUN -> [SKIP][17] ([i915#11078])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@device_reset@cold-reset-bound.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-tglu: NOTRUN -> ([SKIP][18], [SKIP][19]) ([i915#11078])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@device_reset@unbind-cold-reset-rebind.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@device_reset@unbind-cold-reset-rebind.html
- shard-dg2: NOTRUN -> ([SKIP][20], [SKIP][21]) ([i915#11078])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@device_reset@unbind-cold-reset-rebind.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@device_reset@unbind-cold-reset-rebind.html
* igt@device_reset@unbind-reset-rebind:
- shard-tglu: [PASS][22] -> ([ABORT][23], [ABORT][24]) ([i915#12817] / [i915#5507])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-7/igt@device_reset@unbind-reset-rebind.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-4/igt@device_reset@unbind-reset-rebind.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-7/igt@device_reset@unbind-reset-rebind.html
* igt@drm_fdinfo@busy-check-all@ccs0:
- shard-mtlp: NOTRUN -> ([SKIP][25], [SKIP][26]) ([i915#8414]) +6 other tests ( 2 skip )
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@drm_fdinfo@busy-check-all@ccs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@drm_fdinfo@busy-check-all@ccs0.html
- shard-dg2-9: NOTRUN -> [SKIP][27] ([i915#11527] / [i915#8414]) +7 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@drm_fdinfo@busy-check-all@ccs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg2-9: NOTRUN -> [SKIP][28] ([i915#8414]) +2 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@drm_fdinfo@virtual-busy-all.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-dg2: NOTRUN -> ([SKIP][29], [SKIP][30]) ([i915#8414])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@drm_fdinfo@virtual-busy-idle-all.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@gem_basic@multigpu-create-close:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#7697])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_basic@multigpu-create-close.html
* igt@gem_busy@semaphore:
- shard-dg2-9: NOTRUN -> [SKIP][32] ([i915#3936])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_busy@semaphore.html
* igt@gem_caching@reads:
- shard-mtlp: NOTRUN -> ([SKIP][33], [SKIP][34]) ([i915#4873])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_caching@reads.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@gem_caching@reads.html
* igt@gem_ccs@block-copy-compressed:
- shard-tglu-1: NOTRUN -> [SKIP][35] ([i915#3555] / [i915#9323])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-tglu: NOTRUN -> ([SKIP][36], [SKIP][37]) ([i915#3555] / [i915#9323])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@gem_ccs@ctrl-surf-copy.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu: NOTRUN -> ([SKIP][38], [SKIP][39]) ([i915#9323])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ccs@suspend-resume:
- shard-dg2: [PASS][40] -> ([INCOMPLETE][41], [PASS][42]) ([i915#13356])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@gem_ccs@suspend-resume.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_ccs@suspend-resume.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-3/igt@gem_ccs@suspend-resume.html
- shard-rkl: NOTRUN -> [SKIP][43] ([i915#9323]) +1 other test skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_ccs@suspend-resume.html
- shard-tglu-1: NOTRUN -> [SKIP][44] ([i915#9323])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_ccs@suspend-resume.html
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
- shard-dg2: [PASS][45] -> ([INCOMPLETE][46], [PASS][47]) ([i915#12392] / [i915#13356])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-3/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#7697])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-dg2-9: NOTRUN -> [SKIP][49] ([i915#7697])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-tglu-1: NOTRUN -> [SKIP][50] ([i915#6335])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#8562])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-snb: NOTRUN -> [SKIP][52] ([i915#1099]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@gem_ctx_persistence@engines-mixed.html
* igt@gem_ctx_persistence@hang:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#8555])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> ([SKIP][54], [SKIP][55]) ([i915#8555]) +1 other test ( 2 skip )
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@gem_ctx_persistence@heartbeat-hostile.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-dg2-9: NOTRUN -> [SKIP][56] ([i915#8555])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@legacy-engines-cleanup:
- shard-snb: NOTRUN -> ([SKIP][57], [SKIP][58]) ([i915#1099])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@gem_ctx_persistence@legacy-engines-cleanup.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb7/igt@gem_ctx_persistence@legacy-engines-cleanup.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@rcs0:
- shard-dg2-9: NOTRUN -> [SKIP][59] ([i915#5882]) +7 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_ctx_persistence@saturated-hostile-nopreempt@rcs0.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglu: NOTRUN -> ([SKIP][60], [SKIP][61]) ([i915#280])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@gem_ctx_sseu@invalid-sseu.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@gem_ctx_sseu@invalid-sseu.html
- shard-dg2-9: NOTRUN -> [SKIP][62] ([i915#280]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglu-1: NOTRUN -> [SKIP][63] ([i915#280])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@kms:
- shard-dg2: NOTRUN -> ([FAIL][64], [PASS][65]) ([i915#5784])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_eio@kms.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_eio@kms.html
* igt@gem_eio@reset-stress:
- shard-snb: NOTRUN -> [FAIL][66] ([i915#8898])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@gem_eio@reset-stress.html
- shard-dg1: [PASS][67] -> ([FAIL][68], [PASS][69]) ([i915#12543] / [i915#5784])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-17/igt@gem_eio@reset-stress.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-18/igt@gem_eio@reset-stress.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2-9: NOTRUN -> [SKIP][70] ([i915#4771]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@individual:
- shard-rkl: [PASS][71] -> ([DMESG-WARN][72], [DMESG-WARN][73]) ([i915#12964]) +3 other tests ( 2 dmesg-warn )
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_exec_balancer@individual.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@gem_exec_balancer@individual.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_exec_balancer@individual.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-rkl: NOTRUN -> [SKIP][74] ([i915#4525]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-tglu: NOTRUN -> ([SKIP][75], [SKIP][76]) ([i915#4525])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@gem_exec_balancer@parallel-keep-in-fence.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu-1: NOTRUN -> [SKIP][77] ([i915#4525]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_big@single:
- shard-tglu-1: NOTRUN -> [ABORT][78] ([i915#11713])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_exec_big@single.html
* igt@gem_exec_capture@capture-invisible:
- shard-dg2-9: NOTRUN -> [SKIP][79] ([i915#6334]) +2 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_capture@capture-recoverable:
- shard-rkl: NOTRUN -> [SKIP][80] ([i915#6344])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-rkl: [PASS][81] -> ([TIMEOUT][82], [PASS][83]) ([i915#3778]) +1 other test ( 1 pass, 1 timeout )
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-7/igt@gem_exec_endless@dispatch@rcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-6/igt@gem_exec_endless@dispatch@rcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_fence@concurrent:
- shard-dg2-9: NOTRUN -> [SKIP][84] ([i915#4812]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_fence@concurrent.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg2: NOTRUN -> ([SKIP][85], [SKIP][86]) ([i915#3539] / [i915#4852])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2-9: NOTRUN -> [SKIP][87] ([i915#3539] / [i915#4852]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_flush@basic-uc-prw-default:
- shard-dg2-9: NOTRUN -> [SKIP][88] ([i915#3539])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_flush@basic-uc-prw-default.html
* igt@gem_exec_flush@basic-wb-ro-default:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#3539] / [i915#4852])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@gem_exec_flush@basic-wb-ro-default.html
* igt@gem_exec_reloc@basic-cpu-gtt:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#3281]) +6 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_exec_reloc@basic-cpu-gtt.html
* igt@gem_exec_reloc@basic-gtt-read-active:
- shard-dg2-9: NOTRUN -> [SKIP][91] ([i915#3281]) +9 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_reloc@basic-gtt-read-active.html
* igt@gem_exec_reloc@basic-range-active:
- shard-mtlp: NOTRUN -> ([SKIP][92], [SKIP][93]) ([i915#3281]) +1 other test ( 2 skip )
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@gem_exec_reloc@basic-range-active.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_exec_reloc@basic-range-active.html
* igt@gem_exec_reloc@basic-softpin:
- shard-rkl: NOTRUN -> [SKIP][94] ([i915#3281]) +10 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_exec_reloc@basic-softpin.html
* igt@gem_exec_reloc@basic-wc:
- shard-dg2: NOTRUN -> ([SKIP][95], [SKIP][96]) ([i915#3281]) +2 other tests ( 2 skip )
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_exec_reloc@basic-wc.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain:
- shard-dg2-9: NOTRUN -> [SKIP][97] ([i915#4537] / [i915#4812])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_exec_schedule@preempt-queue-contexts-chain.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> ([SKIP][98], [SKIP][99]) ([i915#4537] / [i915#4812])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@gem_exec_schedule@reorder-wide.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#7276])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s3-devices:
- shard-dg1: [PASS][101] -> ([DMESG-WARN][102], [PASS][103]) ([i915#4423]) +7 other tests ( 1 dmesg-warn, 1 pass )
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-17/igt@gem_exec_suspend@basic-s3-devices.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-14/igt@gem_exec_suspend@basic-s3-devices.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-18/igt@gem_exec_suspend@basic-s3-devices.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#4860]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-dg2: NOTRUN -> ([SKIP][105], [SKIP][106]) ([i915#4860])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-dg2-9: NOTRUN -> [SKIP][107] ([i915#4860]) +2 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_fenced_exec_thrash@too-many-fences.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][108] ([i915#2190])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-tglu: NOTRUN -> ([SKIP][109], [SKIP][110]) ([i915#4613] / [i915#7582])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@gem_lmem_evict@dontneed-evict-race.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][111] ([i915#4613]) +3 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-rkl: NOTRUN -> [SKIP][112] ([i915#4613]) +4 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@massive-random:
- shard-tglu: NOTRUN -> ([SKIP][113], [SKIP][114]) ([i915#4613]) +1 other test ( 2 skip )
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@gem_lmem_swapping@massive-random.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@gem_lmem_swapping@massive-random.html
* igt@gem_lmem_swapping@parallel-random:
- shard-mtlp: NOTRUN -> ([SKIP][115], [SKIP][116]) ([i915#4613])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@gem_lmem_swapping@parallel-random.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][117] -> ([TIMEOUT][118], [PASS][119]) ([i915#5493]) +1 other test ( 1 pass, 1 timeout )
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_media_fill@media-fill:
- shard-dg2-9: NOTRUN -> [SKIP][120] ([i915#8289])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_media_fill@media-fill.html
* igt@gem_mmap@bad-size:
- shard-dg2: NOTRUN -> ([SKIP][121], [SKIP][122]) ([i915#4083]) +1 other test ( 2 skip )
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@gem_mmap@bad-size.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_mmap@bad-size.html
* igt@gem_mmap_gtt@basic-read:
- shard-dg2-9: NOTRUN -> [SKIP][123] ([i915#4077]) +16 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_mmap_gtt@basic-read.html
* igt@gem_mmap_gtt@big-copy-odd:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#4077])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_mmap_gtt@big-copy-odd.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-mtlp: NOTRUN -> ([SKIP][125], [SKIP][126]) ([i915#4077]) +2 other tests ( 2 skip )
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-dg2: NOTRUN -> [SKIP][127] ([i915#4077]) +1 other test skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_gtt@medium-copy-odd:
- shard-rkl: [PASS][128] -> ([DMESG-WARN][129], [DMESG-WARN][130]) ([i915#12917] / [i915#12964])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_mmap_gtt@medium-copy-odd.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_mmap_gtt@medium-copy-odd.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@gem_mmap_gtt@medium-copy-odd.html
* igt@gem_mmap_wc@pf-nonblock:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#4083])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@gem_mmap_wc@pf-nonblock.html
* igt@gem_mmap_wc@read-write-distinct:
- shard-dg2-9: NOTRUN -> [SKIP][132] ([i915#4083]) +8 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_mmap_wc@read-write-distinct.html
* igt@gem_partial_pwrite_pread@write-uncached:
- shard-dg2-9: NOTRUN -> [SKIP][133] ([i915#3282]) +3 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_partial_pwrite_pread@write-uncached.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#3282]) +6 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#3282])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@gem_pxp@create-regular-context-1:
- shard-dg2: NOTRUN -> ([SKIP][136], [SKIP][137]) ([i915#4270])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_pxp@create-regular-context-1.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@create-valid-protected-context:
- shard-rkl: [PASS][138] -> ([TIMEOUT][139], [PASS][140]) ([i915#12964])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_pxp@create-valid-protected-context.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@gem_pxp@create-valid-protected-context.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@display-protected-crc:
- shard-rkl: NOTRUN -> [SKIP][141] ([i915#4270])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-rkl: [PASS][142] -> ([TIMEOUT][143], [TIMEOUT][144]) ([i915#12917] / [i915#12964]) +1 other test ( 2 timeout )
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-1.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@gem_pxp@reject-modify-context-protection-off-1.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#4270])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-dg2-9: NOTRUN -> [SKIP][146] ([i915#4270]) +3 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_readwrite@beyond-eob:
- shard-dg2: NOTRUN -> ([SKIP][147], [SKIP][148]) ([i915#3282]) +2 other tests ( 2 skip )
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@gem_readwrite@beyond-eob.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_readwrite@beyond-eob.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-snb: NOTRUN -> [SKIP][149] +32 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_render_copy@linear-to-vebox-yf-tiled:
- shard-dg2-9: NOTRUN -> [SKIP][150] ([i915#5190] / [i915#8428]) +4 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_render_copy@linear-to-vebox-yf-tiled.html
* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#5190] / [i915#8428]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> ([SKIP][152], [SKIP][153]) ([i915#5190] / [i915#8428]) +5 other tests ( 2 skip )
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#8411]) +1 other test skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-dg2: NOTRUN -> ([SKIP][155], [SKIP][156]) ([i915#4079])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2-9: NOTRUN -> [SKIP][157] ([i915#4885])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_swapping@non-threaded:
- shard-dg2: NOTRUN -> ([SKIP][158], [SKIP][159]) ([i915#4077]) +2 other tests ( 2 skip )
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@gem_tiled_swapping@non-threaded.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_tiled_swapping@non-threaded.html
- shard-rkl: [PASS][160] -> ([PASS][161], [FAIL][162]) ([i915#12941])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@gem_tiled_swapping@non-threaded.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_tiled_swapping@non-threaded.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@gem_tiled_swapping@non-threaded.html
- shard-tglu-1: NOTRUN -> [FAIL][163] ([i915#12941])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_tiled_swapping@non-threaded.html
- shard-snb: [PASS][164] -> ([FAIL][165], [PASS][166]) ([i915#12941])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb6/igt@gem_tiled_swapping@non-threaded.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb5/igt@gem_tiled_swapping@non-threaded.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb4/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_unfence_active_buffers:
- shard-dg2-9: NOTRUN -> [SKIP][167] ([i915#4879])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@coherency-sync:
- shard-dg2: NOTRUN -> ([SKIP][168], [SKIP][169]) ([i915#3297])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_userptr_blits@coherency-sync.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_userptr_blits@coherency-sync.html
- shard-tglu-1: NOTRUN -> [SKIP][170] ([i915#3297]) +1 other test skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: NOTRUN -> [SKIP][171] ([i915#3297]) +3 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-rkl: NOTRUN -> [SKIP][172] ([i915#3297] / [i915#3323])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-rkl: NOTRUN -> [SKIP][173] ([i915#3282] / [i915#3297])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-dg2-9: NOTRUN -> [SKIP][174] ([i915#3297] / [i915#4880])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#3297])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@relocations:
- shard-dg2-9: NOTRUN -> [SKIP][176] ([i915#3281] / [i915#3297])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_userptr_blits@relocations.html
* igt@gem_userptr_blits@sd-probe:
- shard-dg2-9: NOTRUN -> [SKIP][177] ([i915#3297] / [i915#4958])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_userptr_blits@sd-probe.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-mtlp: NOTRUN -> ([SKIP][178], [SKIP][179]) ([i915#3297]) +1 other test ( 2 skip )
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_userptr_blits@unsync-overlap.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-dg2-9: NOTRUN -> [SKIP][180] ([i915#3297])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-snb: NOTRUN -> ([SKIP][181], [SKIP][182]) +76 other tests ( 2 skip )
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb7/igt@gen7_exec_parse@oacontrol-tracking.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-single:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#2527]) +2 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-dg2-9: NOTRUN -> [SKIP][184] ([i915#2856]) +4 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@bb-oversize:
- shard-tglu-1: NOTRUN -> [SKIP][185] ([i915#2527] / [i915#2856]) +3 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@bb-start-param:
- shard-tglu: NOTRUN -> ([SKIP][186], [SKIP][187]) ([i915#2527] / [i915#2856]) +2 other tests ( 2 skip )
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@gen9_exec_parse@bb-start-param.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@gen9_exec_parse@bb-start-param.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg2: NOTRUN -> ([SKIP][188], [SKIP][189]) ([i915#2856]) +1 other test ( 2 skip )
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gen9_exec_parse@shadow-peek.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@gen9_exec_parse@shadow-peek.html
* igt@gen9_exec_parse@unaligned-access:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#2856])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@gen9_exec_parse@unaligned-access.html
* igt@gen9_exec_parse@valid-registers:
- shard-mtlp: NOTRUN -> ([SKIP][191], [SKIP][192]) ([i915#2856])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@gen9_exec_parse@valid-registers.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@load:
- shard-glk: ([PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215]) -> ([PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [DMESG-WARN][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250], [PASS][251]) ([i915#118])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk5/igt@i915_module_load@load.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk5/igt@i915_module_load@load.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk5/igt@i915_module_load@load.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk4/igt@i915_module_load@load.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk6/igt@i915_module_load@load.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk4/igt@i915_module_load@load.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk6/igt@i915_module_load@load.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk7/igt@i915_module_load@load.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk3/igt@i915_module_load@load.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk7/igt@i915_module_load@load.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk3/igt@i915_module_load@load.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@i915_module_load@load.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk7/igt@i915_module_load@load.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@i915_module_load@load.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk8/igt@i915_module_load@load.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk8/igt@i915_module_load@load.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@i915_module_load@load.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk8/igt@i915_module_load@load.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk1/igt@i915_module_load@load.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk9/igt@i915_module_load@load.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk1/igt@i915_module_load@load.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk1/igt@i915_module_load@load.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk9/igt@i915_module_load@load.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_module_load@load.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk3/igt@i915_module_load@load.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_module_load@load.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk6/igt@i915_module_load@load.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_module_load@load.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk5/igt@i915_module_load@load.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk2/igt@i915_module_load@load.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk5/igt@i915_module_load@load.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@i915_module_load@load.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk6/igt@i915_module_load@load.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk5/igt@i915_module_load@load.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk2/igt@i915_module_load@load.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk2/igt@i915_module_load@load.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk3/igt@i915_module_load@load.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk5/igt@i915_module_load@load.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk6/igt@i915_module_load@load.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@load.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_module_load@load.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk1/igt@i915_module_load@load.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk6/igt@i915_module_load@load.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_module_load@load.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@i915_module_load@load.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk3/igt@i915_module_load@load.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@i915_module_load@load.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk3/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [PASS][252] -> ([ABORT][253], [ABORT][254]) ([i915#9820])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@i915_module_load@reload-with-fault-injection.html
- shard-snb: [PASS][255] -> ([ABORT][256], [PASS][257]) ([i915#9820])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_module_load@resize-bar:
- shard-rkl: NOTRUN -> [SKIP][258] ([i915#6412])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-tglu: NOTRUN -> ([SKIP][259], [SKIP][260]) ([i915#8399])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@i915_pm_freq_api@freq-basic-api.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-tglu-1: NOTRUN -> [SKIP][261] ([i915#8399]) +1 other test skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [PASS][262] -> ([FAIL][263], [PASS][264]) ([i915#3591]) +1 other test ( 1 fail, 1 pass )
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-rkl: [PASS][265] -> ([SKIP][266], [SKIP][267]) ([i915#13328]) +1 other test ( 2 skip )
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@i915_pm_rpm@debugfs-forcewake-user.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@i915_pm_rpm@debugfs-forcewake-user.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@i915_pm_rps@engine-order:
- shard-glk: [PASS][268] -> ([FAIL][269], [PASS][270]) ([i915#13547])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk4/igt@i915_pm_rps@engine-order.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk5/igt@i915_pm_rps@engine-order.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_pm_rps@engine-order.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][271] -> ([INCOMPLETE][272], [INCOMPLETE][273]) ([i915#13729] / [i915#13821])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb7/igt@i915_pm_rps@reset.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb4/igt@i915_pm_rps@reset.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb7/igt@i915_pm_rps@reset.html
* igt@i915_pm_rps@thresholds-idle:
- shard-dg2-9: NOTRUN -> [SKIP][274] ([i915#11681])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@i915_pm_rps@thresholds-idle.html
* igt@i915_power@sanity:
- shard-mtlp: [PASS][275] -> ([PASS][276], [SKIP][277]) ([i915#7984])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-8/igt@i915_power@sanity.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-2/igt@i915_power@sanity.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-6/igt@i915_power@sanity.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-dg2: NOTRUN -> [SKIP][278] ([i915#6188])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_query@test-query-geometry-subslices:
- shard-tglu-1: NOTRUN -> [SKIP][279] ([i915#5723])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_selftest@mock@memory_region:
- shard-dg2: NOTRUN -> ([DMESG-WARN][280], [DMESG-WARN][281]) ([i915#9311]) +1 other test ( 2 dmesg-warn )
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@i915_selftest@mock@memory_region.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@i915_selftest@mock@memory_region.html
- shard-tglu-1: NOTRUN -> [DMESG-WARN][282] ([i915#9311]) +1 other test dmesg-warn
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@i915_selftest@mock@memory_region.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> ([SKIP][283], [SKIP][284]) ([i915#8709]) +1 other test ( 2 skip )
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-3-y-rc-ccs-cc:
- shard-dg1: NOTRUN -> [SKIP][285] ([i915#8709]) +3 other tests skip
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-3-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-tglu: NOTRUN -> ([SKIP][286], [SKIP][287]) ([i915#8709]) +3 other tests ( 2 skip )
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][288] ([i915#8709]) +7 other tests skip
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_async_flips@invalid-async-flip:
- shard-dg2: NOTRUN -> ([SKIP][289], [SKIP][290]) ([i915#12967] / [i915#6228])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_async_flips@invalid-async-flip.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-dg1: [PASS][291] -> ([FAIL][292], [FAIL][293]) ([i915#5956])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-13/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-16/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-17/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg2-9: NOTRUN -> [SKIP][294] ([i915#1769] / [i915#3555])
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> ([FAIL][295], [FAIL][296]) ([i915#5956])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-17/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-16/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-90:
- shard-dg2: NOTRUN -> ([SKIP][297], [SKIP][298]) +4 other tests ( 2 skip )
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][299] +1 other test skip
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-tglu-1: NOTRUN -> [SKIP][300] ([i915#5286]) +6 other tests skip
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-rkl: NOTRUN -> [SKIP][301] ([i915#5286]) +7 other tests skip
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-tglu: NOTRUN -> ([SKIP][302], [SKIP][303]) ([i915#5286]) +3 other tests ( 2 skip )
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][304] ([i915#3638]) +3 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-dg2-9: NOTRUN -> [SKIP][305] +15 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-dg2: NOTRUN -> ([SKIP][306], [SKIP][307]) ([i915#4538] / [i915#5190]) +4 other tests ( 2 skip )
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> ([SKIP][308], [SKIP][309]) ([i915#5190]) +1 other test ( 2 skip )
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-mtlp: NOTRUN -> ([SKIP][310], [SKIP][311]) ([i915#6187])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
- shard-dg2-9: NOTRUN -> [SKIP][312] ([i915#4538] / [i915#5190]) +13 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][313] ([i915#4538] / [i915#5190]) +2 other tests skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-tglu: NOTRUN -> ([SKIP][314], [SKIP][315]) +41 other tests ( 2 skip )
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][316] ([i915#10307] / [i915#10434] / [i915#6095]) +7 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][317] ([i915#12313]) +3 other tests skip
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> ([SKIP][318], [SKIP][319]) ([i915#10307] / [i915#6095]) +30 other tests ( 2 skip )
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][320] ([i915#4423] / [i915#6095])
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-12/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][321] ([i915#10307] / [i915#6095]) +249 other tests skip
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4.html
* igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> ([SKIP][322], [SKIP][323]) ([i915#6095]) +13 other tests ( 2 skip )
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-a-hdmi-a-1.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
- shard-glk: NOTRUN -> ([SKIP][324], [SKIP][325]) +26 other tests ( 2 skip )
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> ([SKIP][326], [SKIP][327]) ([i915#6095]) +4 other tests ( 2 skip )
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> ([SKIP][328], [SKIP][329]) ([i915#12805])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
- shard-tglu-1: NOTRUN -> [SKIP][330] ([i915#12805])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][331] ([i915#6095]) +74 other tests skip
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> ([SKIP][332], [SKIP][333]) ([i915#6095]) +44 other tests ( 2 skip )
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][334] ([i915#12805])
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][335] ([i915#6095]) +9 other tests skip
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][336] ([i915#6095]) +32 other tests skip
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs:
- shard-dg2: NOTRUN -> ([SKIP][337], [SKIP][338]) ([i915#6095]) +4 other tests ( 2 skip )
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][339] ([i915#6095]) +108 other tests skip
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][340] ([i915#12313])
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> ([SKIP][341], [SKIP][342]) ([i915#6095]) +15 other tests ( 2 skip )
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-17/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-4.html
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-16/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][343] ([i915#12313]) +1 other test skip
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
- shard-dg2: NOTRUN -> ([SKIP][344], [SKIP][345]) ([i915#12313])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][346] ([i915#6095]) +158 other tests skip
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-c-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][347] ([i915#10307] / [i915#6095]) +69 other tests skip
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-c-hdmi-a-2.html
* igt@kms_cdclk@mode-transition:
- shard-rkl: NOTRUN -> [SKIP][348] ([i915#3742]) +1 other test skip
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_cdclk@mode-transition.html
- shard-tglu-1: NOTRUN -> [SKIP][349] ([i915#3742])
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][350] ([i915#13781]) +3 other tests skip
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-3/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> ([SKIP][351], [SKIP][352]) ([i915#13783]) +3 other tests ( 2 skip )
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html
* igt@kms_chamelium_audio@dp-audio:
- shard-tglu: NOTRUN -> ([SKIP][353], [SKIP][354]) ([i915#11151] / [i915#7828]) +5 other tests ( 2 skip )
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_chamelium_audio@dp-audio.html
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_edid@dp-edid-read:
- shard-dg2-9: NOTRUN -> [SKIP][355] ([i915#11151] / [i915#7828]) +10 other tests skip
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_chamelium_edid@dp-edid-read.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-dg2: NOTRUN -> ([SKIP][356], [SKIP][357]) ([i915#11151] / [i915#7828]) +3 other tests ( 2 skip )
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][358] ([i915#11151] / [i915#7828]) +10 other tests skip
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_chamelium_hpd@dp-hpd-storm-disable:
- shard-tglu-1: NOTRUN -> [SKIP][359] ([i915#11151] / [i915#7828]) +7 other tests skip
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm:
- shard-dg2: NOTRUN -> [SKIP][360] ([i915#11151] / [i915#7828]) +1 other test skip
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_chamelium_hpd@hdmi-hpd-storm.html
* igt@kms_chamelium_hpd@vga-hpd-after-suspend:
- shard-mtlp: NOTRUN -> ([SKIP][361], [SKIP][362]) ([i915#11151] / [i915#7828])
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2-9: NOTRUN -> [SKIP][363] ([i915#7118] / [i915#9424]) +1 other test skip
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@content-type-change:
- shard-dg2: NOTRUN -> ([SKIP][364], [SKIP][365]) ([i915#9424]) +1 other test ( 2 skip )
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_content_protection@content-type-change.html
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_content_protection@content-type-change.html
- shard-tglu-1: NOTRUN -> [SKIP][366] ([i915#6944] / [i915#9424])
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-tglu: NOTRUN -> ([SKIP][367], [SKIP][368]) ([i915#3116] / [i915#3299])
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_content_protection@dp-mst-lic-type-0.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_content_protection@dp-mst-lic-type-0.html
- shard-dg2: NOTRUN -> [SKIP][369] ([i915#3299])
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-rkl: NOTRUN -> [SKIP][370] ([i915#3116])
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-tglu-1: NOTRUN -> [SKIP][371] ([i915#3116] / [i915#3299])
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-tglu: NOTRUN -> ([SKIP][372], [SKIP][373]) ([i915#6944] / [i915#9424]) +1 other test ( 2 skip )
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_content_protection@lic-type-0.html
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_content_protection@lic-type-0.html
- shard-dg2-9: NOTRUN -> [SKIP][374] ([i915#9424]) +1 other test skip
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][375] ([i915#7118])
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-rkl: NOTRUN -> [SKIP][376] ([i915#13049])
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: NOTRUN -> [SKIP][377] ([i915#13049])
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg2-9: NOTRUN -> [SKIP][378] ([i915#13049]) +2 other tests skip
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-tglu: NOTRUN -> ([SKIP][379], [SKIP][380]) ([i915#3555]) +2 other tests ( 2 skip )
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_cursor_crc@cursor-sliding-32x32.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-tglu-1: NOTRUN -> [SKIP][381] ([i915#13049]) +1 other test skip
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-mtlp: NOTRUN -> ([SKIP][382], [SKIP][383]) ([i915#3555] / [i915#8814])
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-max-size.html
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-dg2-9: NOTRUN -> [SKIP][384] ([i915#13046] / [i915#5354]) +5 other tests skip
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-rkl: NOTRUN -> [SKIP][385] +25 other tests skip
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-dg2: NOTRUN -> ([SKIP][386], [SKIP][387]) ([i915#13046] / [i915#5354]) +2 other tests ( 2 skip )
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][388] ([i915#13046] / [i915#5354]) +1 other test skip
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-rkl: NOTRUN -> [SKIP][389] ([i915#9067])
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2-9: NOTRUN -> [SKIP][390] ([i915#4103] / [i915#4213])
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][391] ([i915#4103] / [i915#4213])
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][392] ([i915#9723])
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@extended-mode-basic:
- shard-rkl: NOTRUN -> [SKIP][393] ([i915#13691])
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-rkl: NOTRUN -> [SKIP][394] ([i915#3555] / [i915#3804])
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][395] ([i915#3804])
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_aux_dev:
- shard-dg2-9: NOTRUN -> [SKIP][396] ([i915#1257])
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_dp_aux_dev.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-dg2-9: NOTRUN -> [SKIP][397] ([i915#13749])
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_dp_link_training@non-uhbr-sst.html
- shard-tglu-1: NOTRUN -> [SKIP][398] ([i915#13749])
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-dg2: NOTRUN -> ([SKIP][399], [SKIP][400]) ([i915#13748])
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_dp_link_training@uhbr-mst.html
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_dp_link_training@uhbr-mst.html
- shard-tglu: NOTRUN -> ([SKIP][401], [SKIP][402]) ([i915#13748])
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_dp_link_training@uhbr-mst.html
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dp_link_training@uhbr-sst:
- shard-tglu-1: NOTRUN -> [SKIP][403] ([i915#13748])
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_dp_link_training@uhbr-sst.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-rkl: NOTRUN -> [SKIP][404] ([i915#13707])
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_dp_linktrain_fallback@dp-fallback.html
- shard-tglu-1: NOTRUN -> [SKIP][405] ([i915#13707])
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_draw_crc@draw-method-render@xrgb2101010-untiled:
- shard-rkl: [PASS][406] -> [DMESG-WARN][407] ([i915#12964]) +4 other tests dmesg-warn
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-5/igt@kms_draw_crc@draw-method-render@xrgb2101010-untiled.html
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_draw_crc@draw-method-render@xrgb2101010-untiled.html
* igt@kms_dsc@dsc-basic:
- shard-dg2-9: NOTRUN -> [SKIP][408] ([i915#3555] / [i915#3840])
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg2: NOTRUN -> ([SKIP][409], [SKIP][410]) ([i915#3840] / [i915#9688])
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_dsc@dsc-fractional-bpp.html
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_dsc@dsc-fractional-bpp.html
- shard-tglu-1: NOTRUN -> [SKIP][411] ([i915#3840])
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2-9: NOTRUN -> [SKIP][412] ([i915#3840])
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
- shard-tglu: NOTRUN -> ([SKIP][413], [SKIP][414]) ([i915#3840])
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-tglu-1: NOTRUN -> [SKIP][415] ([i915#3555] / [i915#3840])
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-rkl: NOTRUN -> [SKIP][416] ([i915#3555] / [i915#3840])
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][417] ([i915#3840] / [i915#9053])
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
- shard-tglu: NOTRUN -> ([SKIP][418], [SKIP][419]) ([i915#3840] / [i915#9053])
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-dg2: NOTRUN -> ([SKIP][420], [SKIP][421]) ([i915#13798])
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
- shard-tglu-1: NOTRUN -> [SKIP][422] ([i915#2575])
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][423] ([i915#3955]) +1 other test skip
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@dp-mst:
- shard-rkl: NOTRUN -> [SKIP][424] ([i915#9337])
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-dg2: NOTRUN -> ([SKIP][425], [SKIP][426]) ([i915#658])
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_feature_discovery@psr1.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_feature_discovery@psr1.html
* igt@kms_feature_discovery@psr2:
- shard-tglu-1: NOTRUN -> [SKIP][427] ([i915#658]) +1 other test skip
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_feature_discovery@psr2.html
- shard-rkl: NOTRUN -> [SKIP][428] ([i915#658])
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-dg2: NOTRUN -> [SKIP][429] ([i915#9934]) +1 other test skip
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-blocking-wf_vblank:
- shard-dg2: NOTRUN -> ([SKIP][430], [SKIP][431]) ([i915#9934]) +3 other tests ( 2 skip )
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_flip@2x-blocking-wf_vblank.html
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_flip@2x-blocking-wf_vblank.html
- shard-tglu-1: NOTRUN -> [SKIP][432] ([i915#3637]) +8 other tests skip
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_flip@2x-blocking-wf_vblank.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [PASS][433] -> [FAIL][434] ([i915#11832]) +1 other test fail
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-mtlp: NOTRUN -> [SKIP][435] ([i915#3637])
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> ([SKIP][436], [SKIP][437]) ([i915#3637]) +1 other test ( 2 skip )
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_flip@2x-flip-vs-rmfb.html
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_flip@2x-flip-vs-rmfb.html
- shard-dg2-9: NOTRUN -> [SKIP][438] ([i915#9934]) +9 other tests skip
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-plain-flip:
- shard-tglu: NOTRUN -> ([SKIP][439], [SKIP][440]) ([i915#3637]) +2 other tests ( 2 skip )
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_flip@2x-plain-flip.html
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-rkl: NOTRUN -> [SKIP][441] ([i915#9934]) +8 other tests skip
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg2-9: NOTRUN -> [SKIP][442] ([i915#8381])
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a4:
- shard-dg1: [PASS][443] -> [DMESG-WARN][444] ([i915#4423]) +1 other test dmesg-warn
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-19/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a4.html
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a4.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible@b-hdmi-a1:
- shard-rkl: NOTRUN -> ([DMESG-WARN][445], [DMESG-WARN][446]) ([i915#12964]) +1 other test ( 2 dmesg-warn )
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_flip@modeset-vs-vblank-race-interruptible@b-hdmi-a1.html
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_flip@modeset-vs-vblank-race-interruptible@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> ([SKIP][447], [SKIP][448]) ([i915#2672] / [i915#8813])
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][449] ([i915#2672] / [i915#3555])
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][450] ([i915#2672])
[450]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][451] ([i915#2672]) +3 other tests skip
[451]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-dg2-9: NOTRUN -> [SKIP][452] ([i915#2672] / [i915#3555] / [i915#5190]) +2 other tests skip
[452]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> ([SKIP][453], [SKIP][454]) ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test ( 2 skip )
[453]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[454]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> ([SKIP][455], [SKIP][456]) ([i915#2672]) +1 other test ( 2 skip )
[455]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
[456]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
- shard-tglu: NOTRUN -> ([SKIP][457], [SKIP][458]) ([i915#2672] / [i915#3555])
[457]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
[458]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> ([SKIP][459], [SKIP][460]) ([i915#2587] / [i915#2672])
[459]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
[460]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-rkl: NOTRUN -> [SKIP][461] ([i915#2672] / [i915#3555]) +3 other tests skip
[461]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
- shard-mtlp: NOTRUN -> ([SKIP][462], [SKIP][463]) ([i915#3555] / [i915#8810] / [i915#8813])
[462]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
[463]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> ([SKIP][464], [SKIP][465]) ([i915#3555] / [i915#8810])
[464]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
[465]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][466] ([i915#2672] / [i915#3555]) +2 other tests skip
[466]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
- shard-dg2-9: NOTRUN -> [SKIP][467] ([i915#2672] / [i915#3555])
[467]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][468] ([i915#2587] / [i915#2672]) +2 other tests skip
[468]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-mtlp: NOTRUN -> [SKIP][469] ([i915#2672] / [i915#3555] / [i915#8813])
[469]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][470] ([i915#2672] / [i915#8813])
[470]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> ([SKIP][471], [SKIP][472]) ([i915#2672] / [i915#3555] / [i915#8813]) +2 other tests ( 2 skip )
[471]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode.html
[472]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][473] ([i915#2672]) +3 other tests skip
[473]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> ([SKIP][474], [SKIP][475]) ([i915#8708])
[474]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[475]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-dg2-9: NOTRUN -> [SKIP][476] ([i915#5354]) +33 other tests skip
[476]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> ([SKIP][477], [SKIP][478]) ([i915#8708]) +13 other tests ( 2 skip )
[477]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
[478]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-dg2: NOTRUN -> ([SKIP][479], [SKIP][480]) ([i915#5354]) +12 other tests ( 2 skip )
[479]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html
[480]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> ([SKIP][481], [SKIP][482]) ([i915#1825]) +3 other tests ( 2 skip )
[481]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu.html
[482]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-rkl: NOTRUN -> [SKIP][483] ([i915#3023]) +30 other tests skip
[483]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-dg2-9: NOTRUN -> [SKIP][484] ([i915#3458]) +19 other tests skip
[484]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
- shard-dg2: NOTRUN -> [SKIP][485] ([i915#3458]) +4 other tests skip
[485]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
- shard-tglu-1: NOTRUN -> [SKIP][486] +100 other tests skip
[486]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-dg2-9: NOTRUN -> [SKIP][487] ([i915#8708]) +14 other tests skip
[487]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][488] ([i915#8708]) +9 other tests skip
[488]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-mtlp: NOTRUN -> [SKIP][489] ([i915#1825]) +1 other test skip
[489]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-tglu-1: NOTRUN -> [SKIP][490] ([i915#5439])
[490]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-tglu-1: NOTRUN -> [SKIP][491] ([i915#9766])
[491]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-dg2-9: NOTRUN -> [SKIP][492] ([i915#9766])
[492]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> ([SKIP][493], [SKIP][494]) ([i915#3458]) +8 other tests ( 2 skip )
[493]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
[494]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> ([SKIP][495], [SKIP][496]) ([i915#10433] / [i915#3458])
[495]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
[496]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
- shard-dg2: NOTRUN -> [SKIP][497] ([i915#5354]) +6 other tests skip
[497]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][498] ([i915#1825]) +39 other tests skip
[498]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_getfb@getfb2-handle-protection:
- shard-rkl: [PASS][499] -> ([DMESG-WARN][500], [PASS][501]) ([i915#12964]) +2 other tests ( 1 dmesg-warn, 1 pass )
[499]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@kms_getfb@getfb2-handle-protection.html
[500]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_getfb@getfb2-handle-protection.html
[501]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_getfb@getfb2-handle-protection.html
* igt@kms_hdr@bpc-switch:
- shard-dg2: [PASS][502] -> ([SKIP][503], [SKIP][504]) ([i915#3555] / [i915#8228])
[502]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-11/igt@kms_hdr@bpc-switch.html
[503]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_hdr@bpc-switch.html
[504]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@kms_hdr@bpc-switch.html
- shard-tglu-1: NOTRUN -> [SKIP][505] ([i915#3555] / [i915#8228]) +2 other tests skip
[505]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-dg2: NOTRUN -> ([SKIP][506], [SKIP][507]) ([i915#3555] / [i915#8228])
[506]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_hdr@bpc-switch-suspend.html
[507]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-toggle:
- shard-dg2-9: NOTRUN -> [SKIP][508] ([i915#3555] / [i915#8228]) +2 other tests skip
[508]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-dpms:
- shard-rkl: NOTRUN -> [SKIP][509] ([i915#3555] / [i915#8228]) +1 other test skip
[509]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][510] ([i915#12388])
[510]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][511] ([i915#12394])
[511]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
- shard-mtlp: NOTRUN -> ([SKIP][512], [SKIP][513]) ([i915#10656])
[512]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
[513]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
- shard-dg2-9: NOTRUN -> [SKIP][514] ([i915#10656])
[514]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-tglu: NOTRUN -> ([SKIP][515], [SKIP][516]) ([i915#12339])
[515]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_joiner@invalid-modeset-ultra-joiner.html
[516]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-dg2-9: NOTRUN -> [SKIP][517] ([i915#12339]) +1 other test skip
[517]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][518] ([i915#4816])
[518]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-dg2-9: NOTRUN -> [SKIP][519] ([i915#6301])
[519]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- shard-mtlp: [PASS][520] -> ([PASS][521], [ABORT][522]) ([i915#13193]) +4 other tests ( 1 abort, 1 pass )
[520]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-6/igt@kms_pipe_crc_basic@hang-read-crc.html
[521]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@kms_pipe_crc_basic@hang-read-crc.html
[522]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pipe_stress@stress-xrgb8888-ytiled:
- shard-dg2-9: NOTRUN -> [SKIP][523] ([i915#13705])
[523]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_plane_multiple@tiling-y:
- shard-dg2-9: NOTRUN -> [SKIP][524] ([i915#8806])
[524]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][525] ([i915#3555]) +9 other tests skip
[525]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: [PASS][526] -> ([SKIP][527], [PASS][528]) ([i915#6953] / [i915#9423])
[526]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@kms_plane_scaling@intel-max-src-size.html
[527]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_plane_scaling@intel-max-src-size.html
[528]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers:
- shard-dg2: NOTRUN -> [SKIP][529] ([i915#12247] / [i915#9423])
[529]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b:
- shard-dg2: NOTRUN -> [SKIP][530] ([i915#12247]) +11 other tests skip
[530]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c:
- shard-tglu: NOTRUN -> ([SKIP][531], [SKIP][532]) ([i915#12247]) +17 other tests ( 2 skip )
[531]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c.html
[532]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
- shard-tglu-1: NOTRUN -> [SKIP][533] ([i915#12247]) +18 other tests skip
[533]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][534] ([i915#12247]) +14 other tests skip
[534]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20:
- shard-dg2-9: NOTRUN -> [SKIP][535] ([i915#12247] / [i915#9423])
[535]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a:
- shard-dg2-9: NOTRUN -> [SKIP][536] ([i915#12247]) +3 other tests skip
[536]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-tglu-1: NOTRUN -> [SKIP][537] ([i915#12247] / [i915#6953])
[537]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][538] ([i915#12247] / [i915#3555] / [i915#9423])
[538]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
- shard-tglu: NOTRUN -> ([SKIP][539], [SKIP][540]) ([i915#12247] / [i915#3555])
[539]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
[540]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][541] ([i915#12247] / [i915#6953] / [i915#9423])
[541]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-tglu: NOTRUN -> ([SKIP][542], [SKIP][543]) ([i915#9812])
[542]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_pm_backlight@fade-with-dpms.html
[543]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-rkl: NOTRUN -> [SKIP][544] ([i915#5354]) +2 other tests skip
[544]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_pm_backlight@fade-with-suspend.html
- shard-tglu-1: NOTRUN -> [SKIP][545] ([i915#9812])
[545]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2: NOTRUN -> ([SKIP][546], [SKIP][547]) ([i915#9685])
[546]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_pm_dc@dc3co-vpb-simulation.html
[547]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_pm_dc@dc3co-vpb-simulation.html
- shard-tglu-1: NOTRUN -> [SKIP][548] ([i915#9685])
[548]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-rkl: NOTRUN -> [SKIP][549] ([i915#3828])
[549]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg2-9: NOTRUN -> [SKIP][550] ([i915#5978])
[550]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-mtlp: [PASS][551] -> ([FAIL][552], [PASS][553]) ([i915#12912])
[551]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-7/igt@kms_pm_dc@dc6-psr.html
[552]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_pm_dc@dc6-psr.html
[553]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [PASS][554] -> ([PASS][555], [SKIP][556]) ([i915#4281])
[554]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-10/igt@kms_pm_dc@dc9-dpms.html
[555]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@kms_pm_dc@dc9-dpms.html
[556]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-3/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: NOTRUN -> [SKIP][557] ([i915#9340])
[557]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2-9: NOTRUN -> [SKIP][558] ([i915#9519])
[558]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: [PASS][559] -> ([SKIP][560], [PASS][561]) ([i915#9519])
[559]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-7/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[560]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[561]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
- shard-tglu-1: NOTRUN -> [SKIP][562] ([i915#9519]) +1 other test skip
[562]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][563] -> ([SKIP][564], [SKIP][565]) ([i915#9519])
[563]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp.html
[564]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_pm_rpm@modeset-lpsp.html
[565]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [PASS][566] -> ([PASS][567], [SKIP][568]) ([i915#9519]) +1 other test ( 1 pass, 1 skip )
[566]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
[567]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
[568]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-tglu: NOTRUN -> ([SKIP][569], [SKIP][570]) ([i915#9519]) +1 other test ( 2 skip )
[569]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_pm_rpm@modeset-non-lpsp.html
[570]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: NOTRUN -> [SKIP][571] ([i915#9519])
[571]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg2: NOTRUN -> ([SKIP][572], [SKIP][573]) ([i915#6524] / [i915#6805])
[572]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_prime@basic-modeset-hybrid.html
[573]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_prime@basic-modeset-hybrid.html
- shard-tglu-1: NOTRUN -> [SKIP][574] ([i915#6524])
[574]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_prime@d3hot:
- shard-rkl: NOTRUN -> [SKIP][575] ([i915#6524])
[575]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
- shard-snb: NOTRUN -> [SKIP][576] ([i915#11520]) +2 other tests skip
[576]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
- shard-tglu: NOTRUN -> ([SKIP][577], [SKIP][578]) ([i915#11520]) +6 other tests ( 2 skip )
[577]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
[578]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-snb: NOTRUN -> ([SKIP][579], [SKIP][580]) ([i915#11520]) +1 other test ( 2 skip )
[579]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html
[580]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> ([SKIP][581], [SKIP][582]) ([i915#11520]) +4 other tests ( 2 skip )
[581]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
[582]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> ([SKIP][583], [SKIP][584]) ([i915#9808])
[583]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1.html
[584]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> ([SKIP][585], [SKIP][586]) ([i915#12316]) +2 other tests ( 2 skip )
[585]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1.html
[586]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-dg2-9: NOTRUN -> [SKIP][587] ([i915#11520]) +9 other tests skip
[587]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-rkl: NOTRUN -> [SKIP][588] ([i915#11520]) +8 other tests skip
[588]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-tglu-1: NOTRUN -> [SKIP][589] ([i915#11520]) +8 other tests skip
[589]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
- shard-dg2: NOTRUN -> [SKIP][590] ([i915#11520]) +2 other tests skip
[590]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][591] ([i915#9683])
[591]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-dg2-9: NOTRUN -> [SKIP][592] ([i915#9683])
[592]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-primary-render:
- shard-dg2-9: NOTRUN -> [SKIP][593] ([i915#1072] / [i915#9732]) +24 other tests skip
[593]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_psr@fbc-pr-primary-render.html
* igt@kms_psr@fbc-pr-sprite-plane-onoff:
- shard-rkl: NOTRUN -> [SKIP][594] ([i915#1072] / [i915#9732]) +24 other tests skip
[594]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
* igt@kms_psr@fbc-psr-no-drrs:
- shard-tglu: NOTRUN -> ([SKIP][595], [SKIP][596]) ([i915#9732]) +10 other tests ( 2 skip )
[595]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_psr@fbc-psr-no-drrs.html
[596]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_psr@fbc-psr-no-drrs.html
* igt@kms_psr@fbc-psr-primary-blt@edp-1:
- shard-mtlp: NOTRUN -> ([SKIP][597], [SKIP][598]) ([i915#9688]) +4 other tests ( 2 skip )
[597]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@kms_psr@fbc-psr-primary-blt@edp-1.html
[598]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@kms_psr@fbc-psr-primary-blt@edp-1.html
* igt@kms_psr@pr-cursor-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][599] ([i915#1072] / [i915#9732]) +6 other tests skip
[599]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_psr@pr-cursor-mmap-cpu.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: NOTRUN -> ([SKIP][600], [SKIP][601]) ([i915#1072] / [i915#9732]) +9 other tests ( 2 skip )
[600]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_psr@psr2-primary-mmap-gtt.html
[601]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][602] ([i915#9732]) +23 other tests skip
[602]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2: NOTRUN -> [SKIP][603] ([i915#9685])
[603]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-dg2: NOTRUN -> ([SKIP][604], [SKIP][605]) ([i915#12755])
[604]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_rotation_crc@primary-rotation-270.html
[605]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2-9: NOTRUN -> [SKIP][606] ([i915#12755])
[606]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-tglu-1: NOTRUN -> [SKIP][607] ([i915#5289]) +1 other test skip
[607]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
- shard-mtlp: NOTRUN -> ([SKIP][608], [SKIP][609]) ([i915#5289])
[608]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
[609]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
- shard-dg2-9: NOTRUN -> [SKIP][610] ([i915#5190]) +1 other test skip
[610]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: NOTRUN -> [SKIP][611] ([i915#5289])
[611]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][612] ([i915#12755] / [i915#5190])
[612]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
- shard-tglu: NOTRUN -> ([SKIP][613], [SKIP][614]) ([i915#5289])
[613]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
[614]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2: NOTRUN -> [SKIP][615] ([i915#12755])
[615]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-dg2: NOTRUN -> ([SKIP][616], [SKIP][617]) ([i915#3555]) +3 other tests ( 2 skip )
[616]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_scaling_modes@scaling-mode-none.html
[617]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_scaling_modes@scaling-mode-none.html
- shard-tglu-1: NOTRUN -> [SKIP][618] ([i915#3555]) +7 other tests skip
[618]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_selftest@drm_framebuffer:
- shard-tglu: NOTRUN -> ([ABORT][619], [ABORT][620]) ([i915#13179]) +1 other test ( 2 abort )
[619]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@kms_selftest@drm_framebuffer.html
[620]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@kms_selftest@drm_framebuffer.html
* igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free:
- shard-dg2: NOTRUN -> ([ABORT][621], [ABORT][622]) ([i915#13179]) +1 other test ( 2 abort )
[621]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html
[622]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-dg2-9: NOTRUN -> [SKIP][623] ([i915#3555]) +6 other tests skip
[623]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-9: NOTRUN -> [SKIP][624] ([i915#8623])
[624]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vblank@wait-forked-busy@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [DMESG-WARN][625] ([i915#12964]) +7 other tests dmesg-warn
[625]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_vblank@wait-forked-busy@pipe-a-hdmi-a-1.html
* igt@kms_vrr@lobf:
- shard-dg2-9: NOTRUN -> [SKIP][626] ([i915#11920])
[626]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_vrr@lobf.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-dg2-9: NOTRUN -> [SKIP][627] ([i915#9906]) +1 other test skip
[627]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@kms_vrr@seamless-rr-switch-virtual.html
- shard-tglu-1: NOTRUN -> [SKIP][628] ([i915#9906])
[628]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-check-output:
- shard-tglu-1: NOTRUN -> [SKIP][629] ([i915#2437])
[629]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-rkl: NOTRUN -> [SKIP][630] ([i915#2437]) +1 other test skip
[630]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2: NOTRUN -> ([SKIP][631], [SKIP][632]) ([i915#2437] / [i915#9412]) +1 other test ( 2 skip )
[631]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
[632]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-tglu-1: NOTRUN -> [SKIP][633] ([i915#2437] / [i915#9412]) +1 other test skip
[633]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-mtlp: NOTRUN -> ([SKIP][634], [SKIP][635]) +3 other tests ( 2 skip )
[634]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
[635]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@perf@gen8-unprivileged-single-ctx-counters.html
- shard-dg2-9: NOTRUN -> [SKIP][636] ([i915#2436])
[636]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@global-sseu-config:
- shard-dg2-9: NOTRUN -> [SKIP][637] ([i915#7387])
[637]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@perf@global-sseu-config.html
* igt@perf@global-sseu-config-invalid:
- shard-dg2: NOTRUN -> ([SKIP][638], [SKIP][639]) ([i915#7387])
[638]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@perf@global-sseu-config-invalid.html
[639]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@perf@global-sseu-config-invalid.html
* igt@perf@mi-rpc:
- shard-rkl: NOTRUN -> [SKIP][640] ([i915#2434])
[640]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@perf@mi-rpc.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][641] ([i915#2435])
[641]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@busy-double-start@vecs0:
- shard-mtlp: [PASS][642] -> ([FAIL][643], [PASS][644]) ([i915#4349])
[642]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-6/igt@perf_pmu@busy-double-start@vecs0.html
[643]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@perf_pmu@busy-double-start@vecs0.html
[644]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@perf_pmu@busy-double-start@vecs0.html
* igt@perf_pmu@enable-race@vecs0:
- shard-dg1: [PASS][645] -> ([PASS][646], [INCOMPLETE][647]) ([i915#13520]) +1 other test ( 1 incomplete, 1 pass )
[645]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-19/igt@perf_pmu@enable-race@vecs0.html
[646]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@perf_pmu@enable-race@vecs0.html
[647]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-13/igt@perf_pmu@enable-race@vecs0.html
* igt@perf_pmu@invalid-init:
- shard-dg2-9: NOTRUN -> [FAIL][648] ([i915#13663])
[648]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@perf_pmu@invalid-init.html
* igt@perf_pmu@module-unload:
- shard-rkl: [PASS][649] -> [INCOMPLETE][650] ([i915#13520])
[649]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-6/igt@perf_pmu@module-unload.html
[650]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6-all-gts:
- shard-rkl: NOTRUN -> [SKIP][651] ([i915#8516])
[651]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2-9: NOTRUN -> [SKIP][652] ([i915#8516])
[652]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-tglu: NOTRUN -> ([SKIP][653], [SKIP][654]) ([i915#8516])
[653]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-2/igt@perf_pmu@rc6@other-idle-gt0.html
[654]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][655] ([i915#3291] / [i915#3708])
[655]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> ([SKIP][656], [SKIP][657]) ([i915#3291] / [i915#3708])
[656]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@prime_vgem@basic-read.html
[657]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@prime_vgem@basic-read.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> ([SKIP][658], [SKIP][659]) ([i915#3708] / [i915#4077])
[658]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@prime_vgem@coherency-gtt.html
[659]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg2-9: NOTRUN -> [SKIP][660] ([i915#3708])
[660]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-9/igt@prime_vgem@fence-flip-hang.html
* igt@prime_vgem@fence-read-hang:
- shard-dg2: NOTRUN -> ([SKIP][661], [SKIP][662]) ([i915#3708])
[661]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@prime_vgem@fence-read-hang.html
[662]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@prime_vgem@fence-read-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-rkl: NOTRUN -> [SKIP][663] ([i915#9917])
[663]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-3/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-tglu: NOTRUN -> ([FAIL][664], [FAIL][665]) ([i915#12910])
[664]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
[665]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-8/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
- shard-dg2: NOTRUN -> [SKIP][666] ([i915#9917])
[666]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
* igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-2:
- shard-tglu-1: NOTRUN -> [FAIL][667] ([i915#12910]) +8 other tests fail
[667]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-2.html
#### Possible fixes ####
* igt@drm_fdinfo@busy:
- shard-rkl: [DMESG-WARN][668] ([i915#12964]) -> [PASS][669] +3 other tests pass
[668]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-5/igt@drm_fdinfo@busy.html
[669]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@drm_fdinfo@busy.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][670] ([i915#13427]) -> ([PASS][671], [PASS][672])
[670]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-7/igt@gem_create@create-ext-cpu-access-big.html
[671]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-5/igt@gem_create@create-ext-cpu-access-big.html
[672]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_persistence@engines-mixed-process@vcs0:
- shard-mtlp: [ABORT][673] ([i915#13193]) -> ([PASS][674], [PASS][675]) +2 other tests ( 2 pass )
[673]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-7/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html
[674]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-4/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html
[675]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html
* igt@gem_eio@wait-wedge-10ms:
- shard-mtlp: [ABORT][676] ([i915#13193]) -> [PASS][677]
[676]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-7/igt@gem_eio@wait-wedge-10ms.html
[677]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-3/igt@gem_eio@wait-wedge-10ms.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-glk: [ABORT][678] ([i915#13592]) -> ([PASS][679], [PASS][680])
[678]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk5/igt@i915_module_load@reload-with-fault-injection.html
[679]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk9/igt@i915_module_load@reload-with-fault-injection.html
[680]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk7/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-dg1: [FAIL][681] ([i915#12518] / [i915#12766]) -> ([PASS][682], [PASS][683])
[681]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip.html
[682]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip.html
[683]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-4:
- shard-dg1: [FAIL][684] ([i915#12518]) -> ([PASS][685], [PASS][686])
[684]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-4.html
[685]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-4.html
[686]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-4.html
* igt@kms_cursor_crc@cursor-onscreen-256x85:
- shard-tglu: [FAIL][687] ([i915#13566]) -> ([PASS][688], [PASS][689]) +3 other tests ( 2 pass )
[687]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html
[688]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-5/igt@kms_cursor_crc@cursor-onscreen-256x85.html
[689]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-6/igt@kms_cursor_crc@cursor-onscreen-256x85.html
* igt@kms_cursor_crc@cursor-random-128x42:
- shard-rkl: [FAIL][690] ([i915#13566]) -> [PASS][691] +2 other tests pass
[690]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@kms_cursor_crc@cursor-random-128x42.html
[691]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_cursor_crc@cursor-random-128x42.html
* igt@kms_cursor_crc@cursor-sliding-128x42:
- shard-rkl: [FAIL][692] ([i915#13566]) -> ([PASS][693], [PASS][694])
[692]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-128x42.html
[693]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-128x42.html
[694]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-128x42.html
* igt@kms_cursor_crc@cursor-sliding-256x85:
- shard-tglu: [FAIL][695] ([i915#13566]) -> [PASS][696] +1 other test pass
[695]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-3/igt@kms_cursor_crc@cursor-sliding-256x85.html
[696]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-7/igt@kms_cursor_crc@cursor-sliding-256x85.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-snb: [SKIP][697] -> [PASS][698] +1 other test pass
[697]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb5/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
[698]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb5/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-dg2: [SKIP][699] ([i915#13749]) -> [PASS][700]
[699]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-7/igt@kms_dp_link_training@non-uhbr-sst.html
[700]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1:
- shard-mtlp: [FAIL][701] -> ([PASS][702], [PASS][703]) +5 other tests ( 2 pass )
[701]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-1/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
[702]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-6/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
[703]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-5/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1:
- shard-tglu: [FAIL][704] -> ([PASS][705], [PASS][706])
[704]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-4/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html
[705]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-9/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html
[706]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-3/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [FAIL][707] ([i915#13027]) -> ([PASS][708], [PASS][709]) +1 other test ( 2 pass )
[707]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
[708]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@kms_flip@flip-vs-expired-vblank.html
[709]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-dg1: [FAIL][710] ([i915#13027]) -> ([PASS][711], [PASS][712])
[710]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-18/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[711]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-16/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[712]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-12/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a4:
- shard-dg1: [FAIL][713] ([i915#13027]) -> [PASS][714]
[713]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-18/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a4.html
[714]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-16/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a4.html
* igt@kms_flip@flip-vs-suspend:
- shard-dg1: [DMESG-WARN][715] ([i915#4423]) -> ([PASS][716], [PASS][717]) +6 other tests ( 2 pass )
[715]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-17/igt@kms_flip@flip-vs-suspend.html
[716]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-18/igt@kms_flip@flip-vs-suspend.html
[717]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_flip@flip-vs-suspend.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers:
- shard-rkl: [DMESG-WARN][718] ([i915#12964]) -> ([PASS][719], [PASS][720]) +3 other tests ( 2 pass )
[718]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-5/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers.html
[719]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers.html
[720]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-rkl: [SKIP][721] ([i915#9519]) -> [PASS][722]
[721]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-7/igt@kms_pm_rpm@dpms-non-lpsp.html
[722]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@perf_pmu@busy-double-start@vcs1:
- shard-mtlp: [FAIL][723] ([i915#4349]) -> ([PASS][724], [PASS][725])
[723]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-6/igt@perf_pmu@busy-double-start@vcs1.html
[724]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@perf_pmu@busy-double-start@vcs1.html
[725]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@perf_pmu@busy-double-start@vcs1.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s4-devices:
- shard-mtlp: [ABORT][726] ([i915#7975]) -> ([ABORT][727], [ABORT][728]) ([i915#13193] / [i915#7975]) +1 other test ( 2 abort )
[726]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-4/igt@gem_exec_suspend@basic-s4-devices.html
[727]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@gem_exec_suspend@basic-s4-devices.html
[728]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_pxp@hw-rejects-pxp-context:
- shard-rkl: [FAIL][729] ([i915#13811]) -> ([SKIP][730], [FAIL][731]) ([i915#13717] / [i915#13811])
[729]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-1/igt@gem_pxp@hw-rejects-pxp-context.html
[730]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_pxp@hw-rejects-pxp-context.html
[731]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@gem_pxp@hw-rejects-pxp-context.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-rkl: [TIMEOUT][732] ([i915#12917] / [i915#12964]) -> ([PASS][733], [TIMEOUT][734]) ([i915#12917] / [i915#12964])
[732]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-1/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
[733]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
[734]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][735] ([i915#10131] / [i915#10887] / [i915#9820]) -> ([ABORT][736], [ABORT][737]) ([i915#10131] / [i915#10887] / [i915#13592] / [i915#9820])
[735]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-mtlp-8/igt@i915_module_load@reload-with-fault-injection.html
[736]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
[737]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-mtlp-8/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-suspend@gt0:
- shard-dg2: [INCOMPLETE][738] ([i915#12455] / [i915#13820]) -> ([PASS][739], [INCOMPLETE][740]) ([i915#12455] / [i915#13820]) +1 other test ( 1 incomplete, 1 pass )
[738]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-2/igt@i915_pm_freq_api@freq-suspend@gt0.html
[739]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@i915_pm_freq_api@freq-suspend@gt0.html
[740]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@i915_pm_freq_api@freq-suspend@gt0.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs:
- shard-dg1: [SKIP][741] ([i915#6095]) -> ([SKIP][742], [SKIP][743]) ([i915#4423] / [i915#6095]) +2 other tests ( 2 skip )
[741]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-14/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html
[742]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-18/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html
[743]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-15/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html
* igt@kms_content_protection@srm:
- shard-dg2: [FAIL][744] ([i915#7173]) -> ([SKIP][745], [SKIP][746]) ([i915#7118])
[744]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-11/igt@kms_content_protection@srm.html
[745]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@kms_content_protection@srm.html
[746]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@kms_content_protection@srm.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-dg2: [SKIP][747] ([i915#3555]) -> ([SKIP][748], [PASS][749]) ([i915#3555])
[747]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[748]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[749]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-glk: [INCOMPLETE][750] ([i915#12745] / [i915#4839]) -> ([INCOMPLETE][751], [INCOMPLETE][752]) ([i915#12314] / [i915#12745] / [i915#4839])
[750]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@kms_flip@2x-flip-vs-suspend.html
[751]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk2/igt@kms_flip@2x-flip-vs-suspend.html
[752]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
- shard-glk: [INCOMPLETE][753] ([i915#4839]) -> ([INCOMPLETE][754], [INCOMPLETE][755]) ([i915#12314] / [i915#4839])
[753]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-glk2/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
[754]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk2/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
[755]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-glk8/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-dg1: [SKIP][756] ([i915#2587] / [i915#2672] / [i915#3555]) -> ([SKIP][757], [SKIP][758]) ([i915#2587] / [i915#2672] / [i915#3555] / [i915#4423])
[756]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
[757]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-18/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
[758]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
- shard-dg1: [SKIP][759] ([i915#2587] / [i915#2672]) -> ([SKIP][760], [SKIP][761]) ([i915#2587] / [i915#2672] / [i915#4423])
[759]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
[760]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-18/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
[761]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-rkl: [DMESG-WARN][762] ([i915#12964]) -> ([PASS][763], [DMESG-WARN][764]) ([i915#12964]) +5 other tests ( 1 dmesg-warn, 1 pass )
[762]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[763]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[764]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-snb: [SKIP][765] -> ([PASS][766], [SKIP][767]) +6 other tests ( 1 pass, 1 skip )
[765]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[766]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[767]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-dg2: [SKIP][768] ([i915#3458]) -> ([SKIP][769], [SKIP][770]) ([i915#10433] / [i915#3458]) +2 other tests ( 2 skip )
[768]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
[769]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
[770]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- shard-dg2: [SKIP][771] ([i915#3458]) -> [SKIP][772] ([i915#10433] / [i915#3458])
[771]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
[772]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
- shard-dg2: [SKIP][773] ([i915#10433] / [i915#3458]) -> ([SKIP][774], [SKIP][775]) ([i915#3458])
[773]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html
[774]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html
[775]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
- shard-dg1: [SKIP][776] ([i915#3458]) -> ([SKIP][777], [SKIP][778]) ([i915#3458] / [i915#4423])
[776]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
[777]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
[778]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-dg2: [SKIP][779] ([i915#10433] / [i915#3458]) -> [SKIP][780] ([i915#3458])
[779]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[780]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg2: [SKIP][781] ([i915#3555] / [i915#8228]) -> ([PASS][782], [SKIP][783]) ([i915#3555] / [i915#8228])
[781]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-8/igt@kms_hdr@bpc-switch-dpms.html
[782]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_hdr@bpc-switch-dpms.html
[783]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2: [SKIP][784] ([i915#13331]) -> ([SKIP][785], [SKIP][786]) ([i915#12713] / [i915#13331])
[784]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@kms_hdr@brightness-with-hdr.html
[785]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-11/igt@kms_hdr@brightness-with-hdr.html
[786]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-2/igt@kms_hdr@brightness-with-hdr.html
- shard-tglu: [SKIP][787] ([i915#1187] / [i915#12713]) -> ([SKIP][788], [SKIP][789]) ([i915#12713])
[787]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-tglu-2/igt@kms_hdr@brightness-with-hdr.html
[788]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-5/igt@kms_hdr@brightness-with-hdr.html
[789]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-tglu-10/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-dg2: [SKIP][790] ([i915#12388]) -> ([PASS][791], [SKIP][792]) ([i915#12388]) +1 other test ( 1 pass, 1 skip )
[790]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[791]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[792]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [SKIP][793] ([i915#3361]) -> ([FAIL][794], [SKIP][795]) ([i915#3361] / [i915#9295])
[793]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html
[794]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
[795]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][796] ([i915#4281]) -> [SKIP][797] ([i915#3361])
[796]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
[797]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][798] ([i915#9519]) -> ([PASS][799], [SKIP][800]) ([i915#9519])
[798]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-7/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[799]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[800]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-rkl: [DMESG-WARN][801] ([i915#12964]) -> ([DMESG-WARN][802], [SKIP][803]) ([i915#12964] / [i915#9519])
[801]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
[802]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp.html
[803]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][804] ([i915#9519]) -> ([PASS][805], [SKIP][806]) ([i915#9519])
[804]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[805]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[806]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_psr2_sf@psr2-cursor-plane-update-sf:
- shard-dg1: [SKIP][807] ([i915#11520]) -> ([SKIP][808], [SKIP][809]) ([i915#11520] / [i915#4423])
[807]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-16/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html
[808]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-18/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html
[809]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html
* igt@kms_psr@psr-cursor-mmap-gtt:
- shard-dg1: [SKIP][810] ([i915#1072] / [i915#4423] / [i915#9732]) -> ([SKIP][811], [SKIP][812]) ([i915#1072] / [i915#9732])
[810]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-19/igt@kms_psr@psr-cursor-mmap-gtt.html
[811]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-13/igt@kms_psr@psr-cursor-mmap-gtt.html
[812]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-19/igt@kms_psr@psr-cursor-mmap-gtt.html
* igt@perf_pmu@busy-double-start@vecs0:
- shard-dg1: [FAIL][813] ([i915#4349]) -> ([PASS][814], [FAIL][815]) ([i915#4349])
[813]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg1-17/igt@perf_pmu@busy-double-start@vecs0.html
[814]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-17/igt@perf_pmu@busy-double-start@vecs0.html
[815]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg1-13/igt@perf_pmu@busy-double-start@vecs0.html
* igt@prime_mmap@test_aperture_limit:
- shard-dg2: [INCOMPLETE][816] ([i915#5493]) -> ([WARN][817], [INCOMPLETE][818]) ([i915#5493] / [i915#9351])
[816]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@prime_mmap@test_aperture_limit.html
[817]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@prime_mmap@test_aperture_limit.html
[818]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@prime_mmap@test_aperture_limit.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][819] ([i915#5493]) -> ([INCOMPLETE][820], [CRASH][821]) ([i915#5493] / [i915#9351])
[819]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16280/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[820]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-7/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[821]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11713
[i915#118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/118
[i915#11832]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11832
[i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
[i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
[i915#12455]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12455
[i915#12518]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12518
[i915#12543]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12543
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
[i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12766
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12817
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#12912]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12912
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12941]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12941
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#12967]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12967
[i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
[i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
[i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
[i915#13331]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13331
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427
[i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
[i915#13547]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13547
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13592]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13592
[i915#13663]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13663
[i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
[i915#13705]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13705
[i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
[i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
[i915#13729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13729
[i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
[i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
[i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
[i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
[i915#13798]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13798
[i915#13811]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13811
[i915#13820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13820
[i915#13821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13821
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#4958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4958
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5507
[i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#5978]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5978
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
[i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
[i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
[i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
[i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
[i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
[i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8898]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8898
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_16280 -> Patchwork_144748v3
CI-20190529: 20190529
CI_DRM_16280: 9fe68375ef4ccae6bc9ba01bd5cbdfb047fd8402 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8273: 5d806121f1cfb38fe7cc4d528d81feb1c11274b1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_144748v3: 9fe68375ef4ccae6bc9ba01bd5cbdfb047fd8402 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v3/index.html
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