From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C52FCCA0FE6 for ; Fri, 1 Sep 2023 10:28:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 31D4910E770; Fri, 1 Sep 2023 10:28:20 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D6DE10E770 for ; Fri, 1 Sep 2023 10:28:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693564098; x=1725100098; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=hSp0GA0FZzXZFR+3sfGaeM0d7rin4QkG3xpjsZYuYh8=; b=Hk/0Y/4FoJuScltllnwMlGnAzYhcHm7nr7BUOtQUqZYY7FLf3DxjYeRS 4ub5YXQqUU+w4UB6dgEIO2c5P4F80lonFl0bwPFz5a1uciH+JWzs76cHY q0QSa/QLFrSOKVLnw4kuuEe8W8tizmt5dOfMojzDlBwR9Xg5vsouPhqjH qbi02Rade+9S/RPx2S9IRRhmZjMjnSYPstuSd6TxY2z+pEow7PPvVHUvB 3VTexE6LBqojSQygwRPpQ+1SaBXkihsq31ulNI0THrTtTiGGWHlVMzKSV 7b+vMxFS+93iqcotRERwbQsDfc2BXuObVikELXoInstpw0lunAnQjjx8u A==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356501173" X-IronPort-AV: E=Sophos;i="6.02,219,1688454000"; d="scan'208";a="356501173" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2023 03:28:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="805400187" X-IronPort-AV: E=Sophos;i="6.02,219,1688454000"; d="scan'208";a="805400187" Received: from epronina-mobl.ccr.corp.intel.com (HELO localhost) ([10.252.34.21]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2023 03:28:15 -0700 From: Jani Nikula To: William Tseng , intel-gfx@lists.freedesktop.org In-Reply-To: <20230901095100.3771188-1-william.tseng@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20230901095100.3771188-1-william.tseng@intel.com> Date: Fri, 01 Sep 2023 13:28:09 +0300 Message-ID: <87ttsei3wm.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: William Tseng Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 01 Sep 2023, William Tseng wrote: > This change is to adjust TEOT timing and TCLK-POST timing so DSI > signaling can meet CTS specification. > > For clock lane, the measured TEOT may be changed from 142.64 ns to > 107.36 ns, which is less than (105 ns+12*UI) and is conformed to > mipi D-PHY v1.2 CTS v1.0. > > As to TCLK-POST, it may be changed from 133.44 ns to 178.72 ns, which > is greater than (60 ns+52*UI) and is conformed to the CTS standard. > > The computed UI is around 1.47 ns. The question is, why does the VBT define all this stuff, and when should it be used and when ignored? Also, this won't build. BR, Jani. > > Cc: Ville Syrjala > Cc: Jani Nikula > Cc: Vandita Kulkarni > Cc: Suraj Kandpal > Cc: Lee Shawn C > Signed-off-by: William Tseng > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 31 ++++---------------------- > 1 file changed, 4 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index ad6488e9c2b2..4a13f467ca46 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1819,10 +1819,10 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > struct intel_connector *connector = intel_dsi->attached_connector; > struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; > u32 tlpx_ns; > - u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; > - u32 ths_prepare_ns, tclk_trail_ns; > + u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt; > + u32 ths_prepare_ns; > u32 hs_zero_cnt; > - u32 tclk_pre_cnt, tclk_post_cnt; > + u32 tclk_pre_cnt; > > tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); > > @@ -1853,14 +1853,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; > } > > - /* trail cnt in escape clocks*/ > - trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); > - if (trail_cnt > ICL_TRAIL_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", > - trail_cnt); > - trail_cnt = ICL_TRAIL_CNT_MAX; > - } > - > /* tclk pre count in escape clocks */ > tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); > if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { > @@ -1869,15 +1861,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; > } > > - /* tclk post count in escape clocks */ > - tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); > - if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, > - "tclk_post_cnt out of range (%d)\n", > - tclk_post_cnt); > - tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; > - } > - > /* hs zero cnt in escape clocks */ > hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - > ths_prepare_ns, tlpx_ns); > @@ -1902,19 +1885,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > CLK_ZERO_OVERRIDE | > CLK_ZERO(clk_zero_cnt) | > CLK_PRE_OVERRIDE | > - CLK_PRE(tclk_pre_cnt) | > - CLK_POST_OVERRIDE | > - CLK_POST(tclk_post_cnt) | > - CLK_TRAIL_OVERRIDE | > - CLK_TRAIL(trail_cnt)); > + CLK_PRE(tclk_pre_cnt)); > > /* data lanes dphy timings */ > intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | > HS_PREPARE(prepare_cnt) | > HS_ZERO_OVERRIDE | > HS_ZERO(hs_zero_cnt) | > - HS_TRAIL_OVERRIDE | > - HS_TRAIL(trail_cnt) | > HS_EXIT_OVERRIDE | > HS_EXIT(exit_zero_cnt)); -- Jani Nikula, Intel Open Source Graphics Center