From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0D80C4332F for ; Wed, 19 Oct 2022 23:42:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94B6910E1F3; Wed, 19 Oct 2022 23:42:51 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id F14FF10E170; Wed, 19 Oct 2022 23:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666222953; x=1697758953; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=m2LhorODYDEYn+lI7JgeKqTUFzhOcVOcHZbElf03kgo=; b=IP/ICfYtxVVSPlotnCJDvqa2kirgQfntXtRQ67NG7W7/oBKrtwc15BXX oeIcUjjIJVmR37cLh877+MEp2fNZurj8JbRpuDL5HH7/UwI/u+j1wpyKG M6kv2h60KEe/loV5ASEZwUZTD0wmb8XvQgcpIeXLriHMWoT3YIuiMRO4M VBLtQ9WIDSdyEJnJv6LvCVOmw0H0dzVdpaDrQw4v4bjFw/iGrCZkT08hG dRjIkLeFfpMulzz8TPMfsGfj0yRMjfQGB8Ij9NvBUsx28/KGy13TX2afM TLLmbYhS3BVxGp6/kvz7wbLz+EkVIgnZvImWsitVTbveva5qmgKxlGjCB g==; X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="307658538" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="307658538" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 16:42:19 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="692638221" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="692638221" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.69.147]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 16:42:18 -0700 Date: Wed, 19 Oct 2022 16:42:03 -0700 Message-ID: <87tu3zido4.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Rodrigo Vivi In-Reply-To: References: <20221019052043.3193842-1-ashutosh.dixit@intel.com> <20221019052043.3193842-2-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 19 Oct 2022 08:06:26 -0700, Rodrigo Vivi wrote: > Hi Rodrigo, > On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 36d95b79022c0..a7a0129d0e3fc 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -1543,6 +1543,8 @@ > > > > #define GEN12_RPSTAT1 _MMIO(0x1381b4) > > #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) > > +#define GEN12_CAGF_SHIFT 11 > > we don't need to define the shift if we use the REG_FIELD_GET Yes I was also suggesting this but then went ahead with the mask/shift based code to match previous style in the function. In any case based on your suggestions I have added a new patch is series version v8 which converts all previous branches in intel_rps_get_cagf to REG_FIELD_GET so that the new code can also consistently use REG_FIELD_GET. > > > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) > > ah, cool, this is already right and in place > (ignore my comment about this in the other patch) > > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > > { > > struct drm_i915_private *i915 = rps_to_i915(rps); > > u32 cagf; > > > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > + if (GRAPHICS_VER(i915) >= 12) > > + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; > > cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > > > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > cagf = (rpstat >> 8) & 0xff; > > else if (GRAPHICS_VER(i915) >= 9) > > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; Thanks. -- Ashutosh