[PATCH] drm/915/glk: Enable pooled EUs for Geminilake

[PATCH] drm/915/glk: Enable pooled EUs for Geminilake

[Ander Conselvan de Oliveira]

Geminilake also supports pooled EUs. Enable it.

It is unclear if the recommendation to disable it for 2x6 configurations
from commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6")
should also apply to GLK, but the only userspace that uses this only
cares about the 3x6 configuration. See Beignet's commit 6901899ec90a
("Runtime: set the sub slice according to kernel pooled EU configure.").

Cc: Arun Siluvery <arun.siluvery@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Yang Rong <rong.r.yang@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 2e1fd85..198752d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -195,8 +195,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
 	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
 
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
+		info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
+
 		/*
 		 * There is a HW issue in 2x6 fused down parts that requires
 		 * Pooled EU to be enabled as a WA. The pool configuration
@@ -204,9 +206,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 		 * doesn't affect if the device has all 3 subslices enabled.
 		 */
 		/* WaEnablePooledEuFor2x6:bxt */
-		info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) ||
-				       (hweight8(sseu->subslice_mask) == 2 &&
-					INTEL_REVID(dev_priv) < BXT_REVID_C0));
+		info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
+					IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
 
 		sseu->min_eu_in_pool = 0;
 		if (info->has_pooled_eu) {
-- 
2.9.3

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✓ Fi.CI.BAT: success for drm/915/glk: Enable pooled EUs for Geminilake

[Patchwork]

== Series Details ==

Series: drm/915/glk: Enable pooled EUs for Geminilake
URL   : https://patchwork.freedesktop.org/series/20212/
State : success

== Summary ==

Series 20212v1 drm/915/glk: Enable pooled EUs for Geminilake
https://patchwork.freedesktop.org/api/1.0/series/20212/revisions/1/mbox/

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700     total:108  pass:95   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29 

01167ae51701c05da0671c30d3695ed98f62abbf drm-tip: 2017y-02m-24d-12h-48m-26s UTC integration manifest
ffdb1cb drm/915/glk: Enable pooled EUs for Geminilake

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3959/
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Re: [PATCH] drm/915/glk: Enable pooled EUs for Geminilake

[Yang, Rong R]

We suggest GLK could disable pooled EUs for 2x6 configurations too.
As I understand, 2x6 a pool must consist of a complete subslice, 12EUs, right?
If so, only 64K SLM are valid, I am afraid it may affect some case's performance.

> -----Original Message-----
> From: Conselvan De Oliveira, Ander
> Sent: Friday, February 24, 2017 21:13
> To: intel-gfx@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> Arun Siluvery <arun.siluvery@intel.com>; Kuoppala, Mika
> <mika.kuoppala@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
> Yang, Rong R <rong.r.yang@intel.com>
> Subject: [PATCH] drm/915/glk: Enable pooled EUs for Geminilake
> 
> Geminilake also supports pooled EUs. Enable it.
> 
> It is unclear if the recommendation to disable it for 2x6 configurations from
> commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6")
> should also apply to GLK, but the only userspace that uses this only cares
> about the 3x6 configuration. See Beignet's commit 6901899ec90a
> ("Runtime: set the sub slice according to kernel pooled EU configure.").
> 
> Cc: Arun Siluvery <arun.siluvery@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Yang Rong <rong.r.yang@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira
> <ander.conselvan.de.oliveira@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 2e1fd85..198752d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -195,8 +195,10 @@ static void gen9_sseu_info_init(struct
> drm_i915_private *dev_priv)
>  		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
>  	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
> 
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
> +		info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
> +
>  		/*
>  		 * There is a HW issue in 2x6 fused down parts that requires
>  		 * Pooled EU to be enabled as a WA. The pool configuration
> @@ -204,9 +206,8 @@ static void gen9_sseu_info_init(struct
> drm_i915_private *dev_priv)
>  		 * doesn't affect if the device has all 3 subslices enabled.
>  		 */
>  		/* WaEnablePooledEuFor2x6:bxt */
> -		info->has_pooled_eu = ((hweight8(sseu->subslice_mask) ==
> 3) ||
> -				       (hweight8(sseu->subslice_mask) == 2 &&
> -					INTEL_REVID(dev_priv) <
> BXT_REVID_C0));
> +		info->has_pooled_eu |= (hweight8(sseu->subslice_mask) ==
> 2 &&
> +					IS_BXT_REVID(dev_priv, 0,
> BXT_REVID_B_LAST));
> 
>  		sseu->min_eu_in_pool = 0;
>  		if (info->has_pooled_eu) {
> --
> 2.9.3

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Re: [PATCH] drm/915/glk: Enable pooled EUs for Geminilake

[Ander Conselvan De Oliveira]

On Tue, 2017-02-28 at 06:25 +0000, Yang, Rong R wrote:
> We suggest GLK could disable pooled EUs for 2x6 configurations too.

This patch does that. I tried to say that in the commit message but now that I
re-read I see it doesn't really say it.

> As I understand, 2x6 a pool must consist of a complete subslice, 12EUs, right?

That's my understanding too.

Ander

> If so, only 64K SLM are valid, I am afraid it may affect some case's performance.
> 
> > -----Original Message-----
> > From: Conselvan De Oliveira, Ander
> > Sent: Friday, February 24, 2017 21:13
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> > Arun Siluvery <arun.siluvery@intel.com>; Kuoppala, Mika
> > <mika.kuoppala@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
> > Yang, Rong R <rong.r.yang@intel.com>
> > Subject: [PATCH] drm/915/glk: Enable pooled EUs for Geminilake
> > 
> > Geminilake also supports pooled EUs. Enable it.
> > 
> > It is unclear if the recommendation to disable it for 2x6 configurations from
> > commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6")
> > should also apply to GLK, but the only userspace that uses this only cares
> > about the 3x6 configuration. See Beignet's commit 6901899ec90a
> > ("Runtime: set the sub slice according to kernel pooled EU configure.").
> > 
> > Cc: Arun Siluvery <arun.siluvery@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Yang Rong <rong.r.yang@intel.com>
> > Signed-off-by: Ander Conselvan de Oliveira
> > <ander.conselvan.de.oliveira@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 2e1fd85..198752d 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -195,8 +195,10 @@ static void gen9_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
> >  	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
> > 
> > -	if (IS_BROXTON(dev_priv)) {
> > +	if (IS_GEN9_LP(dev_priv)) {
> >  #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
> > +		info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
> > +
> >  		/*
> >  		 * There is a HW issue in 2x6 fused down parts that requires
> >  		 * Pooled EU to be enabled as a WA. The pool configuration
> > @@ -204,9 +206,8 @@ static void gen9_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  		 * doesn't affect if the device has all 3 subslices enabled.
> >  		 */
> >  		/* WaEnablePooledEuFor2x6:bxt */
> > -		info->has_pooled_eu = ((hweight8(sseu->subslice_mask) ==
> > 3) ||
> > -				       (hweight8(sseu->subslice_mask) == 2 &&
> > -					INTEL_REVID(dev_priv) <
> > BXT_REVID_C0));
> > +		info->has_pooled_eu |= (hweight8(sseu->subslice_mask) ==
> > 2 &&
> > +					IS_BXT_REVID(dev_priv, 0,
> > BXT_REVID_B_LAST));
> > 
> >  		sseu->min_eu_in_pool = 0;
> >  		if (info->has_pooled_eu) {
> > --
> > 2.9.3
> 
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Re: [PATCH] drm/915/glk: Enable pooled EUs for Geminilake

[Mika Kuoppala]

Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
writes:

> Geminilake also supports pooled EUs. Enable it.
>
> It is unclear if the recommendation to disable it for 2x6 configurations
> from commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6")
> should also apply to GLK, but the only userspace that uses this only
> cares about the 3x6 configuration. See Beignet's commit 6901899ec90a
> ("Runtime: set the sub slice according to kernel pooled EU configure.").
>

In patch subject s/915/i915.

Also could you add explicitly that with glk, we dont tell userspace
that pooling is supported if configuration is 2x6. Apparently
to be on the safe side and that we can later lift this restriction
if it doesn't affect the performance.

-Mika


> Cc: Arun Siluvery <arun.siluvery@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Yang Rong <rong.r.yang@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 2e1fd85..198752d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -195,8 +195,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
>  	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>  
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
> +		info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
> +
>  		/*
>  		 * There is a HW issue in 2x6 fused down parts that requires
>  		 * Pooled EU to be enabled as a WA. The pool configuration
> @@ -204,9 +206,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  		 * doesn't affect if the device has all 3 subslices enabled.
>  		 */
>  		/* WaEnablePooledEuFor2x6:bxt */
> -		info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) ||
> -				       (hweight8(sseu->subslice_mask) == 2 &&
> -					INTEL_REVID(dev_priv) < BXT_REVID_C0));
> +		info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
> +					IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
>  
>  		sseu->min_eu_in_pool = 0;
>  		if (info->has_pooled_eu) {
> -- 
> 2.9.3
>
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[PATCH v2] drm/i915/glk: Enable pooled EUs for Geminilake

[Ander Conselvan de Oliveira]

Geminilake also supports pooled EUs. Enable it.

It is unclear if the recommendation to disable it for 2x6 configurations
from commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6")
should also apply to GLK, but it is applied anyway to be on the safe
side. That restriction can be lifted later if determined not to impact
performance.

The extra restriction should not impact user space either. The only user
space that uses this feature is Beignet, and it only does so for 3x6
devices. See See Beignet's commit 6901899ec90a ("Runtime: set the sub
slice according to kernel pooled EU configure.").

v2: Improve commit message. (Mika, Roy)

Cc: Arun Siluvery <arun.siluvery@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Yang Rong <rong.r.yang@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9fc6ab7..7d01dfe 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -197,8 +197,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
 	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
 
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
+		info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
+
 		/*
 		 * There is a HW issue in 2x6 fused down parts that requires
 		 * Pooled EU to be enabled as a WA. The pool configuration
@@ -206,9 +208,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 		 * doesn't affect if the device has all 3 subslices enabled.
 		 */
 		/* WaEnablePooledEuFor2x6:bxt */
-		info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) ||
-				       (hweight8(sseu->subslice_mask) == 2 &&
-					INTEL_REVID(dev_priv) < BXT_REVID_C0));
+		info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
+					IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
 
 		sseu->min_eu_in_pool = 0;
 		if (info->has_pooled_eu) {
-- 
2.9.3

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Re: [PATCH v2] drm/i915/glk: Enable pooled EUs for Geminilake

[Mika Kuoppala]

Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
writes:

> Geminilake also supports pooled EUs. Enable it.
>
> It is unclear if the recommendation to disable it for 2x6 configurations
> from commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6")
> should also apply to GLK, but it is applied anyway to be on the safe
> side. That restriction can be lifted later if determined not to impact
> performance.
>
> The extra restriction should not impact user space either. The only user
> space that uses this feature is Beignet, and it only does so for 3x6
> devices. See See Beignet's commit 6901899ec90a ("Runtime: set the sub
> slice according to kernel pooled EU configure.").
>
> v2: Improve commit message. (Mika, Roy)
>
> Cc: Arun Siluvery <arun.siluvery@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Yang Rong <rong.r.yang@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 9fc6ab7..7d01dfe 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -197,8 +197,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
>  	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>  
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
> +		info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
> +
>  		/*
>  		 * There is a HW issue in 2x6 fused down parts that requires
>  		 * Pooled EU to be enabled as a WA. The pool configuration
> @@ -206,9 +208,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  		 * doesn't affect if the device has all 3 subslices enabled.
>  		 */
>  		/* WaEnablePooledEuFor2x6:bxt */
> -		info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) ||
> -				       (hweight8(sseu->subslice_mask) == 2 &&
> -					INTEL_REVID(dev_priv) < BXT_REVID_C0));
> +		info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
> +					IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
>  
>  		sseu->min_eu_in_pool = 0;
>  		if (info->has_pooled_eu) {
> -- 
> 2.9.3
>
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Re: [PATCH v2] drm/i915/glk: Enable pooled EUs for Geminilake

[Mika Kuoppala]

Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
writes:

> Geminilake also supports pooled EUs. Enable it.
>
> It is unclear if the recommendation to disable it for 2x6 configurations
> from commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6")
> should also apply to GLK, but it is applied anyway to be on the safe
> side. That restriction can be lifted later if determined not to impact
> performance.
>
> The extra restriction should not impact user space either. The only user
> space that uses this feature is Beignet, and it only does so for 3x6
> devices. See See Beignet's commit 6901899ec90a ("Runtime: set the sub
> slice according to kernel pooled EU configure.").
>
> v2: Improve commit message. (Mika, Roy)
>
> Cc: Arun Siluvery <arun.siluvery@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Yang Rong <rong.r.yang@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Pushed, thanks for patch and review.
-Mika

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✓ Fi.CI.BAT: success for drm/915/glk: Enable pooled EUs for Geminilake (rev2)

[Patchwork]

== Series Details ==

Series: drm/915/glk: Enable pooled EUs for Geminilake (rev2)
URL   : https://patchwork.freedesktop.org/series/20212/
State : success

== Summary ==

Series 20212v2 drm/915/glk: Enable pooled EUs for Geminilake
https://patchwork.freedesktop.org/api/1.0/series/20212/revisions/2/mbox/

Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-a:
                dmesg-warn -> PASS       (fi-byt-n2820) fdo#100094

fdo#100094 https://bugs.freedesktop.org/show_bug.cgi?id=100094

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 460s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 573s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 532s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 562s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 502s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 497s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 437s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 428s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 439s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 510s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 488s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 487s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 480s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 599s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 478s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 515s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 542s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 423s

a201103b5beed97d7ee2f86624d83b1fd7f1c117 drm-tip: 2017y-03m-17d-13h-05m-28s UTC integration manifest
b54f395 drm/i915/glk: Enable pooled EUs for Geminilake

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4218/
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