* [PATCH 1/2] drm : adds Y-coordinate and Colorimetry Format
@ 2016-12-21 16:02 vathsala nagaraju
2016-12-21 16:02 ` [PATCH 2/2] drm/i915/psr: program vsc header for psr2 vathsala nagaraju
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: vathsala nagaraju @ 2016-12-21 16:02 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Rodrigo Vivi
PSR2 vsc revision number hb2( as per table 6-11)is updated to
4 or 5 based on Y cordinate and Colorimetry Format as below
04h = 3D stereo + PSR/PSR2 + Y-coordinate.
05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
Format indication. A DP Source device is allowed to indicate the pixel
encoding/colorimetry format to the DP Sink device with VSC SDP only when
the DP Sink device supports it (
i.e.,VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the
DPRX_FEATURE_ENUMERATION_LIST register (DPCD Address 02210h, bit 3;
is set to 1).
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
include/drm/drm_dp_helper.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 55bbeb0..b3d2858 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -194,6 +194,7 @@
# define DP_PSR_SETUP_TIME_0 (6 << 1)
# define DP_PSR_SETUP_TIME_MASK (7 << 1)
# define DP_PSR_SETUP_TIME_SHIFT 1
+# define DP_PSR_Y_COORDINATE (1 << 4) /* eDP 1.4 */
/*
* 0x80-0x8f describe downstream port capabilities, but there are two layouts
@@ -568,6 +569,9 @@
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
+#define DPRX_FEATURE_ENUMERATION_LIST 0x2210
+# define VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3)
+
/* DP 1.2 Sideband message defines */
/* peer device type - DP 1.2a Table 2-92 */
#define DP_PEER_DEVICE_NONE 0x0
--
1.9.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] drm/i915/psr: program vsc header for psr2
2016-12-21 16:02 [PATCH 1/2] drm : adds Y-coordinate and Colorimetry Format vathsala nagaraju
@ 2016-12-21 16:02 ` vathsala nagaraju
2016-12-22 11:13 ` Jani Nikula
2016-12-21 17:22 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm : adds Y-coordinate and Colorimetry Format Patchwork
2016-12-22 11:05 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
2 siblings, 1 reply; 6+ messages in thread
From: vathsala nagaraju @ 2016-12-21 16:02 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Rodrigo Vivi
Function hsw_psr_setup handles vsc header setup for psr1 and
skl_psr_setup_vsc handles vsc header setup for psr2.
Setup VSC header in function skl_psr_setup_vsc for psr2 support,
as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
operation.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++++++--
3 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 77d7a07..95ff959 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1232,6 +1232,8 @@ struct i915_psr {
bool psr2_support;
bool aux_frame_sync;
bool link_standby;
+ bool y_cord_support;
+ bool colorimetry_support;
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 66b5bc8..0c9bb66 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3041,6 +3041,22 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
}
+bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
+{
+ uint8_t psr_caps;
+
+ drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
+ return (psr_caps & DP_PSR_Y_COORDINATE);
+}
+
+bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
+{
+ uint8_t dprx;
+
+ drm_dp_dpcd_readb(&intel_dp->aux, DPRX_FEATURE_ENUMERATION_LIST, &dprx);
+ return (dprx & VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
+}
+
/* These are source-specific values. */
uint8_t
intel_dp_voltage_max(struct intel_dp *intel_dp)
@@ -3619,6 +3635,14 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not supported");
+
+ if (dev_priv->psr.psr2_support) {
+ dev_priv->psr.y_cord_support =
+ intel_dp_get_y_cord_status(intel_dp);
+ dev_priv->psr.colorimetry_support =
+ intel_dp_get_colorimetry_status(intel_dp);
+ }
+
}
/* Read the eDP Display control capabilities registers */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6aca8ff..c3aa649 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -122,13 +122,26 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
{
struct edp_vsc_psr psr_vsc;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
memset(&psr_vsc, 0, sizeof(psr_vsc));
psr_vsc.sdp_header.HB0 = 0;
psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x3;
- psr_vsc.sdp_header.HB3 = 0xb;
+ if (dev_priv->psr.colorimetry_support &&
+ dev_priv->psr.y_cord_support) {
+ psr_vsc.sdp_header.HB2 = 0x5;
+ psr_vsc.sdp_header.HB3 = 0x13;
+ } else if (dev_priv->psr.y_cord_support) {
+ psr_vsc.sdp_header.HB2 = 0x4;
+ psr_vsc.sdp_header.HB3 = 0xe;
+ } else {
+ psr_vsc.sdp_header.HB2 = 0x3;
+ psr_vsc.sdp_header.HB3 = 0xc;
+ }
+
intel_psr_write_vsc(intel_dp, &psr_vsc);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] drm/i915/psr: program vsc header for psr2
2016-12-21 16:02 ` [PATCH 2/2] drm/i915/psr: program vsc header for psr2 vathsala nagaraju
@ 2016-12-22 11:13 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2016-12-22 11:13 UTC (permalink / raw)
To: vathsala nagaraju, dri-devel, intel-gfx; +Cc: Rodrigo Vivi
On Wed, 21 Dec 2016, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> Function hsw_psr_setup handles vsc header setup for psr1 and
> skl_psr_setup_vsc handles vsc header setup for psr2.
>
> Setup VSC header in function skl_psr_setup_vsc for psr2 support,
> as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
> operation.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++++++--
> 3 files changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 77d7a07..95ff959 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1232,6 +1232,8 @@ struct i915_psr {
> bool psr2_support;
> bool aux_frame_sync;
> bool link_standby;
> + bool y_cord_support;
> + bool colorimetry_support;
> };
>
> enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 66b5bc8..0c9bb66 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3041,6 +3041,22 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
> DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
> }
>
> +bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
static. Sparse would have told you about this.
> +{
> + uint8_t psr_caps;
Please initialize psr_caps = 0 to default to false in case aux fails. If
the compiler is smart enough, it might even warn you about this.
> +
> + drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
> + return (psr_caps & DP_PSR_Y_COORDINATE);
Unnecessary braces.
> +}
> +
> +bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> +{
> + uint8_t dprx;
> +
> + drm_dp_dpcd_readb(&intel_dp->aux, DPRX_FEATURE_ENUMERATION_LIST, &dprx);
> + return (dprx & VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
Same things here as in intel_dp_get_y_cord_status.
> +}
> +
> /* These are source-specific values. */
> uint8_t
> intel_dp_voltage_max(struct intel_dp *intel_dp)
> @@ -3619,6 +3635,14 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
> DRM_DEBUG_KMS("PSR2 %s on sink",
> dev_priv->psr.psr2_support ? "supported" : "not supported");
> +
> + if (dev_priv->psr.psr2_support) {
> + dev_priv->psr.y_cord_support =
> + intel_dp_get_y_cord_status(intel_dp);
> + dev_priv->psr.colorimetry_support =
> + intel_dp_get_colorimetry_status(intel_dp);
The indentation doesn't seem to be right for the continuation lines.
> + }
> +
> }
>
> /* Read the eDP Display control capabilities registers */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6aca8ff..c3aa649 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -122,13 +122,26 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
> static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
> {
> struct edp_vsc_psr psr_vsc;
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
>
> /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
> memset(&psr_vsc, 0, sizeof(psr_vsc));
> psr_vsc.sdp_header.HB0 = 0;
> psr_vsc.sdp_header.HB1 = 0x7;
> - psr_vsc.sdp_header.HB2 = 0x3;
> - psr_vsc.sdp_header.HB3 = 0xb;
> + if (dev_priv->psr.colorimetry_support &&
> + dev_priv->psr.y_cord_support) {
> + psr_vsc.sdp_header.HB2 = 0x5;
> + psr_vsc.sdp_header.HB3 = 0x13;
> + } else if (dev_priv->psr.y_cord_support) {
> + psr_vsc.sdp_header.HB2 = 0x4;
> + psr_vsc.sdp_header.HB3 = 0xe;
> + } else {
> + psr_vsc.sdp_header.HB2 = 0x3;
> + psr_vsc.sdp_header.HB3 = 0xc;
> + }
Rodrigo, I'm leaving the review of these to you. ;)
BR,
Jani.
> +
> intel_psr_write_vsc(intel_dp, &psr_vsc);
> }
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm : adds Y-coordinate and Colorimetry Format
2016-12-21 16:02 [PATCH 1/2] drm : adds Y-coordinate and Colorimetry Format vathsala nagaraju
2016-12-21 16:02 ` [PATCH 2/2] drm/i915/psr: program vsc header for psr2 vathsala nagaraju
@ 2016-12-21 17:22 ` Patchwork
2016-12-22 11:05 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2016-12-21 17:22 UTC (permalink / raw)
To: Nagaraju, Vathsala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm : adds Y-coordinate and Colorimetry Format
URL : https://patchwork.freedesktop.org/series/17100/
State : failure
== Summary ==
Series 17100v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/17100/revisions/1/mbox/
Test gem_ringfill:
Subgroup basic-default-hang:
pass -> INCOMPLETE (fi-hsw-4770r)
Test kms_force_connector_basic:
Subgroup force-connector-state:
dmesg-warn -> PASS (fi-ivb-3770)
fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14
fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:247 pass:225 dwarn:1 dfail:0 fail:0 skip:21
fi-bxt-t5700 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19
fi-hsw-4770r total:118 pass:109 dwarn:0 dfail:0 fail:0 skip:8
fi-ilk-650 total:247 pass:195 dwarn:0 dfail:0 fail:0 skip:52
fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-kbl-7500u total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13
fi-skl-6700hq total:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:247 pass:224 dwarn:3 dfail:0 fail:0 skip:20
fi-skl-6770hq total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13
fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31
fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32
f45701ec502e5ee9682561be7578bd39741ad4bb drm-tip: 2016y-12m-21d-11h-52m-22s UTC integration manifest
a78c66e drm/i915/psr: program vsc header for psr2
a6df9a0 drm : adds Y-coordinate and Colorimetry Format
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3359/
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [Intel-gfx] [PATCH 1/2] drm : adds Y-coordinate and Colorimetry Format
2016-12-21 16:02 [PATCH 1/2] drm : adds Y-coordinate and Colorimetry Format vathsala nagaraju
2016-12-21 16:02 ` [PATCH 2/2] drm/i915/psr: program vsc header for psr2 vathsala nagaraju
2016-12-21 17:22 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm : adds Y-coordinate and Colorimetry Format Patchwork
@ 2016-12-22 11:05 ` Jani Nikula
2 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2016-12-22 11:05 UTC (permalink / raw)
To: vathsala nagaraju, dri-devel, intel-gfx; +Cc: Rodrigo Vivi
On Wed, 21 Dec 2016, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> PSR2 vsc revision number hb2( as per table 6-11)is updated to
> 4 or 5 based on Y cordinate and Colorimetry Format as below
> 04h = 3D stereo + PSR/PSR2 + Y-coordinate.
> 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
> Format indication. A DP Source device is allowed to indicate the pixel
> encoding/colorimetry format to the DP Sink device with VSC SDP only when
> the DP Sink device supports it (
> i.e.,VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the
> DPRX_FEATURE_ENUMERATION_LIST register (DPCD Address 02210h, bit 3;
> is set to 1).
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> include/drm/drm_dp_helper.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 55bbeb0..b3d2858 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -194,6 +194,7 @@
> # define DP_PSR_SETUP_TIME_0 (6 << 1)
> # define DP_PSR_SETUP_TIME_MASK (7 << 1)
> # define DP_PSR_SETUP_TIME_SHIFT 1
> +# define DP_PSR_Y_COORDINATE (1 << 4) /* eDP 1.4 */
Do you think DP_PSR2_SU_Y_COORDINATE_REQUIRED would be too long? It was
introduced in eDP 1.4a to be specific.
While adding stuff here, please also add DP_PSR2_SU_GRANULARITY_REQUIRED
from eDP v1.4b.
>
> /*
> * 0x80-0x8f describe downstream port capabilities, but there are two layouts
> @@ -568,6 +569,9 @@
> #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
> # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
>
> +#define DPRX_FEATURE_ENUMERATION_LIST 0x2210
> +# define VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3)
> +
All DPCD register and bit defs in this file are prefixed with
DP_. Please add that.
If you're going through the trouble of adding the bits from the spec,
you might as well add all of the bits in this register, and I could
review them at no extra trouble, instead of everyone adding bits and
pieces a little bit at a time. Saves everyone some trouble.
BR,
Jani.
> /* DP 1.2 Sideband message defines */
> /* peer device type - DP 1.2a Table 2-92 */
> #define DP_PEER_DEVICE_NONE 0x0
--
Jani Nikula, Intel Open Source Technology Center
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915/psr: program vsc header for psr2
@ 2016-12-23 5:57 vathsala nagaraju
0 siblings, 0 replies; 6+ messages in thread
From: vathsala nagaraju @ 2016-12-23 5:57 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Rodrigo Vivi
Function hsw_psr_setup handles vsc header setup for psr1 and
skl_psr_setup_vsc handles vsc header setup for psr2.
Setup VSC header in function skl_psr_setup_vsc for psr2 support,
as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
operation.
v2: (Jani)
- Initialize variables to 0
- intel_dp_get_y_cord_status and intel_dp_get_y_cord_status made static
- Correct indentation for continuation lines
- Change DP_PSR_Y_COORDINATE to DP_PSR2_SU_Y_COORDINATE_REQUIRED
- Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX_*
- Change VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED to DP_VSC_*
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 26 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++++++--
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1a91409..855dcba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1232,6 +1232,8 @@ struct i915_psr {
bool psr2_support;
bool aux_frame_sync;
bool link_standby;
+ bool y_cord_support;
+ bool colorimetry_support;
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fb12896..da577c9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3042,6 +3042,24 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
}
+static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
+{
+ uint8_t psr_caps = 0;
+
+ drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
+ return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
+}
+
+static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
+{
+ uint8_t dprx = 0;
+
+ drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_DPRX_FEATURE_ENUMERATION_LIST,
+ &dprx);
+ return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
+}
+
/* These are source-specific values. */
uint8_t
intel_dp_voltage_max(struct intel_dp *intel_dp)
@@ -3620,6 +3638,14 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not supported");
+
+ if (dev_priv->psr.psr2_support) {
+ dev_priv->psr.y_cord_support =
+ intel_dp_get_y_cord_status(intel_dp);
+ dev_priv->psr.colorimetry_support =
+ intel_dp_get_colorimetry_status(intel_dp);
+ }
+
}
/* Read the eDP Display control capabilities registers */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6aca8ff..c3aa649 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -122,13 +122,26 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
{
struct edp_vsc_psr psr_vsc;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
memset(&psr_vsc, 0, sizeof(psr_vsc));
psr_vsc.sdp_header.HB0 = 0;
psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x3;
- psr_vsc.sdp_header.HB3 = 0xb;
+ if (dev_priv->psr.colorimetry_support &&
+ dev_priv->psr.y_cord_support) {
+ psr_vsc.sdp_header.HB2 = 0x5;
+ psr_vsc.sdp_header.HB3 = 0x13;
+ } else if (dev_priv->psr.y_cord_support) {
+ psr_vsc.sdp_header.HB2 = 0x4;
+ psr_vsc.sdp_header.HB3 = 0xe;
+ } else {
+ psr_vsc.sdp_header.HB2 = 0x3;
+ psr_vsc.sdp_header.HB3 = 0xc;
+ }
+
intel_psr_write_vsc(intel_dp, &psr_vsc);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-12-23 5:57 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-12-21 16:02 [PATCH 1/2] drm : adds Y-coordinate and Colorimetry Format vathsala nagaraju
2016-12-21 16:02 ` [PATCH 2/2] drm/i915/psr: program vsc header for psr2 vathsala nagaraju
2016-12-22 11:13 ` Jani Nikula
2016-12-21 17:22 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm : adds Y-coordinate and Colorimetry Format Patchwork
2016-12-22 11:05 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
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2016-12-23 5:57 [PATCH 2/2] drm/i915/psr: program vsc header for psr2 vathsala nagaraju
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