[PATCH v2 3/4] drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround

Arun Siluvery
2015-07-06T16:12:52Z

In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:bdw

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 152b4f6..c4cac4d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1282,6 +1282,11 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
(IS_BROXTON(dev) && (INTEL_REVID(dev) == SKL_REVID_A0)))
wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE);

+ /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
+ index = gen8_emit_flush_coherentl3_wa(ring, batch, index);
+ if (index < 0)
+ return index;
+
/* Pad to end of cacheline */
while (index % CACHELINE_DWORDS)
wa_ctx_emit(batch, MI_NOOP);
--
1.9.1