From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB798ECAAD8 for ; Fri, 16 Sep 2022 21:41:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D643310E35F; Fri, 16 Sep 2022 21:41:07 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3DB2B10E35F for ; Fri, 16 Sep 2022 21:41:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663364463; x=1694900463; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=lQNV1lc8in89BPcx2f7kKjEjxZuLlQxdDR5zL7+RYdA=; b=AWwyI3bgXw9YKLO6CqLP4ktFmQNEI149mRvtKEyB2g+HQavKd3/wUWCg RLGG6b1X6wwitzm3O4UlpfYwi4omr3sIvmF2DGgnFkEALrDYLh7f2vmdl VvuAKb2YNByX3dePQN1Y0JVSgZgXlI0kMadRbkwSgMtjoUABBj7HM0qqn Ba+dytJZgjL6/CPSOoU5iJyoA1AIWkzkUuf+arlVqVu8XQ5+Ml6raumsZ SO3H3MnuXSM1KCe6YXIuciHPnPlceyN7TehF7741c6hOxSW/YZBp5UbJ4 xOECE2CUVUM+otb7gDjwcuHty4EANwapRvuiFT46tJzP4XVIQ8h1M3+Ym A==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="360824603" X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="360824603" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 14:41:02 -0700 X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="617817721" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.227.117]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 14:41:02 -0700 Date: Fri, 16 Sep 2022 14:41:01 -0700 Message-ID: <87v8pnuhea.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20220823204155.8178-19-umesh.nerlige.ramappa@intel.com> References: <20220823204155.8178-1-umesh.nerlige.ramappa@intel.com> <20220823204155.8178-19-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 18/19] drm/i915/guc: Support OA when Wa_16011777198 is enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 23 Aug 2022 13:41:54 -0700, Umesh Nerlige Ramappa wrote: > > From: Vinay Belgaumkar > > There is a w/a to reset RCS/CCS before it goes into RC6. This breaks > OA. Fix it by disabling RC6. Need to mention DG2 in the commit message? > Signed-off-by: Vinay Belgaumkar > --- > .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 9 ++++ > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 45 +++++++++++++++++++ > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 + > drivers/gpu/drm/i915/i915_perf.c | 29 ++++++++++++ > 4 files changed, 85 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h > index 4c840a2639dc..811add10c30d 100644 > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h > @@ -128,6 +128,15 @@ enum slpc_media_ratio_mode { > SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2, > }; > > +enum slpc_gucrc_mode { > + SLPC_GUCRC_MODE_HW = 0, > + SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1, > + SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2, > + SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3, > + > + SLPC_GUCRC_MODE_MAX, > +}; > + > enum slpc_event_id { > SLPC_EVENT_RESET = 0, > SLPC_EVENT_SHUTDOWN = 1, > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > index e1fa1f32f29e..23989f5452a7 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > @@ -642,6 +642,51 @@ static void slpc_get_rp_values(struct intel_guc_slpc *slpc) > slpc->boost_freq = slpc->rp0_freq; > } > > +/** > + * intel_guc_slpc_override_gucrc_mode() - override GUCRC mode > + * @slpc: pointer to intel_guc_slpc. > + * @mode: new value of the mode. > + * > + * This function will override the GUCRC mode. > + * > + * Return: 0 on success, non-zero error code on failure. > + */ > +int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode) > +{ > + int ret; > + struct drm_i915_private *i915 = slpc_to_i915(slpc); > + intel_wakeref_t wakeref; > + > + if (mode >= SLPC_GUCRC_MODE_MAX) > + return -EINVAL; > + > + wakeref = intel_runtime_pm_get(&i915->runtime_pm); > + > + ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode); > + if (ret) > + drm_err(&i915->drm, > + "Override gucrc mode %d failed %d\n", > + mode, ret); > + > + intel_runtime_pm_put(&i915->runtime_pm, wakeref); nit but I think let's switch to with_intel_runtime_pm() since all other slpc functions use that. > + > + return ret; > +} > + > +int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc) > +{ > + struct drm_i915_private *i915 = slpc_to_i915(slpc); > + int ret = 0; > + > + ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE); Looks like slpc_unset_param() is not present so that needs to be added to the patch too, otherwise probably doesn't even compile. > + if (ret) > + drm_err(&i915->drm, > + "Unsetting gucrc mode failed %d\n", > + ret); > + > + return ret; > +} > + > /* > * intel_guc_slpc_enable() - Start SLPC > * @slpc: pointer to intel_guc_slpc. > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h > index 82a98f78f96c..ccf483730d9d 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h > @@ -42,5 +42,7 @@ int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val); > void intel_guc_pm_intrmsk_enable(struct intel_gt *gt); > void intel_guc_slpc_boost(struct intel_guc_slpc *slpc); > void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc); > +int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc); > +int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode); > > #endif > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 132c2ce8b33b..ce1b6ad4d107 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -208,6 +208,7 @@ > #include "gt/intel_lrc.h" > #include "gt/intel_lrc_reg.h" > #include "gt/intel_ring.h" > +#include "gt/uc/intel_guc_slpc.h" > > #include "i915_drv.h" > #include "i915_file_private.h" > @@ -1651,6 +1652,16 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) > > free_oa_buffer(stream); > > + /* > + * Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6. > + */ > + if (intel_guc_slpc_is_used(>->uc.guc) && > + intel_uc_uses_guc_rc(>->uc) && > + (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || > + IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) Do these steppings need to be tweaked, otherwise ok as is too.