From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [Intel-gfx] [PATCH 1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered Date: Thu, 26 Oct 2017 10:59:19 +0300 Message-ID: <87vaj2gx0o.fsf@intel.com> References: <1502414206-21989-1-git-send-email-dhinakaran.pandiyan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1502414206-21989-1-git-send-email-dhinakaran.pandiyan@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Dhinakaran Pandiyan , intel-gfx@lists.freedesktop.org Cc: Dhinakaran Pandiyan , dri-devel@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org T24gVGh1LCAxMCBBdWcgMjAxNywgRGhpbmFrYXJhbiBQYW5kaXlhbiA8ZGhua3JuQGdtYWlsLmNv bT4gd3JvdGU6Cj4gRFBDRCA2MDBoIC0gU0VUX1BPV0VSICYgU0VUX0RQX1BXUl9WT0xUQUdFIGRl ZmluZXMgcG93ZXIgc3RhdGUKPgo+IDEwMSA9IFNldCBNYWluLUxpbmsgZm9yIGxvY2FsIFNpbmsg ZGV2aWNlIGFuZCBhbGwgZG93bnN0cmVhbSBTaW5rCj4gZGV2aWNlcyB0byBEMyAocG93ZXItZG93 biBtb2RlKSwga2VlcCBBVVggYmxvY2sgZnVsbHkgcG93ZXJlZCwgcmVhZHkgdG8KPiByZXBseSB3 aXRoaW4gYSBSZXNwb25zZSBUaW1lb3V0IHBlcmlvZCBvZiAzMDB1cy4KPgo+IFRoaXMgc3RhdGUg aXMgdXNlZnVsIGluIGEgTVNUIGRvY2sgKyBNU1QgbW9uaXRvciBjb25maWd1cmF0aW9uIHRoYXQK PiBkb2Vzbid0IHdha2UgdXAgZnJvbSBEMyBzdGF0ZS4KCkRoaW5ha2FyYW4sIHRoZXNlIHR3byBz ZWVtIHRvIGhhdmUgZmFsbGVuIHRocm91Z2ggdGhlIGNyYWNrcywgcGxlYXNlCnJlc2VuZC4KClNv cnJ5ICYgdGhhbmtzLApKYW5pLgoKCj4KPiBTaWduZWQtb2ZmLWJ5OiBEaGluYWthcmFuIFBhbmRp eWFuIDxkaGluYWthcmFuLnBhbmRpeWFuQGludGVsLmNvbT4KPiAtLS0KPiAgaW5jbHVkZS9kcm0v ZHJtX2RwX2hlbHBlci5oIHwgOSArKysrKy0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDUgaW5zZXJ0 aW9ucygrKSwgNCBkZWxldGlvbnMoLSkKPgo+IGRpZmYgLS1naXQgYS9pbmNsdWRlL2RybS9kcm1f ZHBfaGVscGVyLmggYi9pbmNsdWRlL2RybS9kcm1fZHBfaGVscGVyLmgKPiBpbmRleCBiMTc0NzZh Li5kNzdlMGY1IDEwMDY0NAo+IC0tLSBhL2luY2x1ZGUvZHJtL2RybV9kcF9oZWxwZXIuaAo+ICsr KyBiL2luY2x1ZGUvZHJtL2RybV9kcF9oZWxwZXIuaAo+IEBAIC02MTQsMTAgKzYxNCwxMSBAQAo+ ICAjZGVmaW5lIERQX0JSQU5DSF9IV19SRVYgICAgICAgICAgICAgICAgICAgIDB4NTA5Cj4gICNk ZWZpbmUgRFBfQlJBTkNIX1NXX1JFViAgICAgICAgICAgICAgICAgICAgMHg1MEEKPiAgCj4gLSNk ZWZpbmUgRFBfU0VUX1BPV0VSICAgICAgICAgICAgICAgICAgICAgICAgMHg2MDAKPiAtIyBkZWZp bmUgRFBfU0VUX1BPV0VSX0QwICAgICAgICAgICAgICAgICAgICAweDEKPiAtIyBkZWZpbmUgRFBf U0VUX1BPV0VSX0QzICAgICAgICAgICAgICAgICAgICAweDIKPiAtIyBkZWZpbmUgRFBfU0VUX1BP V0VSX01BU0sgICAgICAgICAgICAgICAgICAweDMKPiArI2RlZmluZSBEUF9TRVRfUE9XRVIJCQkw eDYwMAo+ICsjIGRlZmluZSBEUF9TRVRfUE9XRVJfRDAJCTB4MQo+ICsjIGRlZmluZSBEUF9TRVRf UE9XRVJfRDMJCTB4Mgo+ICsjIGRlZmluZSBEUF9TRVRfUE9XRVJfTUFTSwkJMHgzCj4gKyMgZGVm aW5lIERQX1NFVF9QT1dFUl9EM19BVVhfT04JCTB4NQo+ICAKPiAgI2RlZmluZSBEUF9FRFBfRFBD RF9SRVYJCQkgICAgMHg3MDAgICAgLyogZURQIDEuMiAqLwo+ICAjIGRlZmluZSBEUF9FRFBfMTEJ CQkgICAgMHgwMAoKLS0gCkphbmkgTmlrdWxhLCBJbnRlbCBPcGVuIFNvdXJjZSBUZWNobm9sb2d5 IENlbnRlcgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpk cmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0 cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK