* [PATCH 0/5] reorg for future
@ 2014-12-03 12:55 Rodrigo Vivi
2014-12-03 12:55 ` [PATCH 1/5] drm/i915: Organize Fence registers for future enablement Rodrigo Vivi
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2014-12-03 12:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
This entire series has no functional change on current supported platforms and it isn't based on any spec.
This is just a reorg that will help on future.
It is true that removing BUG() for unsupported platforms we miss the warn when enabling new platforms.
But most of the time we just do what these patches are doing now and check for changes later anyway.
So this aims to make life easier.
Rodrigo Vivi (5):
drm/i915: Organize Fence registers for future enablement.
drm/i915: Organize PPGTT init
drm/i915: Organize PDP regs report for future.
drm/i915: Organize INSTDONE report for future.
drm/i915: Organize bind_vma funcs
drivers/gpu/drm/i915/i915_gem.c | 17 +++-----
drivers/gpu/drm/i915/i915_gem_gtt.c | 19 ++-------
drivers/gpu/drm/i915/i915_gpu_error.c | 74 +++++++++++------------------------
3 files changed, 32 insertions(+), 78 deletions(-)
--
1.9.3
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 1/5] drm/i915: Organize Fence registers for future enablement. 2014-12-03 12:55 [PATCH 0/5] reorg for future Rodrigo Vivi @ 2014-12-03 12:55 ` Rodrigo Vivi 2014-12-04 7:47 ` Jani Nikula 2014-12-03 12:55 ` [PATCH 2/5] drm/i915: Organize PPGTT init Rodrigo Vivi ` (4 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Rodrigo Vivi @ 2014-12-03 12:55 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Let's be optimistic that for future platforms this will remain the same and reorg a bit. This reorg in if blocks instead of switch make life easier for future platform support addition. Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 17 ++++++---------- drivers/gpu/drm/i915/i915_gpu_error.c | 37 ++++++++++++----------------------- 2 files changed, 19 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9d362d3..1b320bd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3271,17 +3271,12 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, "bogus fence setup with stride: 0x%x, tiling mode: %i\n", obj->stride, obj->tiling_mode); - switch (INTEL_INFO(dev)->gen) { - case 9: - case 8: - case 7: - case 6: - case 5: - case 4: i965_write_fence_reg(dev, reg, obj); break; - case 3: i915_write_fence_reg(dev, reg, obj); break; - case 2: i830_write_fence_reg(dev, reg, obj); break; - default: BUG(); - } + if (IS_GEN2(dev)) + i830_write_fence_reg(dev, reg, obj); + else if (IS_GEN3(dev)) + i915_write_fence_reg(dev, reg, obj); + else if (INTEL_INFO(dev)->gen >= 4) + i965_write_fence_reg(dev, reg, obj); /* And similarly be paranoid that no direct access to this region * is reordered to before the fence is installed. diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index c4536e1..f117a1d 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -766,32 +766,21 @@ static void i915_gem_record_fences(struct drm_device *dev, struct drm_i915_private *dev_priv = dev->dev_private; int i; - /* Fences */ - switch (INTEL_INFO(dev)->gen) { - case 9: - case 8: - case 7: - case 6: - for (i = 0; i < dev_priv->num_fence_regs; i++) - error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); - break; - case 5: - case 4: - for (i = 0; i < 16; i++) - error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); - break; - case 3: - if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) - for (i = 0; i < 8; i++) - error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); - case 2: + if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) + for (i = 0; i < 8; i++) + error->fence[i+8] = I915_READ(FENCE_REG_945_8 + + (i * 4)); + else if (IS_GEN3(dev) || IS_GEN2(dev)) for (i = 0; i < 8; i++) error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); - break; - - default: - BUG(); - } + else if (IS_GEN5(dev) || IS_GEN4(dev)) + for (i = 0; i < 16; i++) + error->fence[i] = I915_READ64(FENCE_REG_965_0 + + (i * 8)); + else if (INTEL_INFO(dev)->gen >= 6) + for (i = 0; i < dev_priv->num_fence_regs; i++) + error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + + (i * 8)); } -- 1.9.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] drm/i915: Organize Fence registers for future enablement. 2014-12-03 12:55 ` [PATCH 1/5] drm/i915: Organize Fence registers for future enablement Rodrigo Vivi @ 2014-12-04 7:47 ` Jani Nikula 2014-12-04 14:48 ` [PATCH] " Rodrigo Vivi 0 siblings, 1 reply; 13+ messages in thread From: Jani Nikula @ 2014-12-04 7:47 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi On Wed, 03 Dec 2014, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > Let's be optimistic that for future platforms this will remain the same > and reorg a bit. > This reorg in if blocks instead of switch make life easier for future > platform support addition. > > Cc: Damien Lespiau <damien.lespiau@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_gem.c | 17 ++++++---------- > drivers/gpu/drm/i915/i915_gpu_error.c | 37 ++++++++++++----------------------- > 2 files changed, 19 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 9d362d3..1b320bd 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3271,17 +3271,12 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, > "bogus fence setup with stride: 0x%x, tiling mode: %i\n", > obj->stride, obj->tiling_mode); > > - switch (INTEL_INFO(dev)->gen) { > - case 9: > - case 8: > - case 7: > - case 6: > - case 5: > - case 4: i965_write_fence_reg(dev, reg, obj); break; > - case 3: i915_write_fence_reg(dev, reg, obj); break; > - case 2: i830_write_fence_reg(dev, reg, obj); break; > - default: BUG(); > - } > + if (IS_GEN2(dev)) > + i830_write_fence_reg(dev, reg, obj); > + else if (IS_GEN3(dev)) > + i915_write_fence_reg(dev, reg, obj); > + else if (INTEL_INFO(dev)->gen >= 4) > + i965_write_fence_reg(dev, reg, obj); > > /* And similarly be paranoid that no direct access to this region > * is reordered to before the fence is installed. > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index c4536e1..f117a1d 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -766,32 +766,21 @@ static void i915_gem_record_fences(struct drm_device *dev, > struct drm_i915_private *dev_priv = dev->dev_private; > int i; > > - /* Fences */ > - switch (INTEL_INFO(dev)->gen) { > - case 9: > - case 8: > - case 7: > - case 6: > - for (i = 0; i < dev_priv->num_fence_regs; i++) > - error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); > - break; > - case 5: > - case 4: > - for (i = 0; i < 16; i++) > - error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); > - break; > - case 3: > - if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) > - for (i = 0; i < 8; i++) > - error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); > - case 2: > + if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) > + for (i = 0; i < 8; i++) > + error->fence[i+8] = I915_READ(FENCE_REG_945_8 + > + (i * 4)); Do note the fallthrough from case 3 to case 2 in the original. For these platforms you'll also need the ones below. Maybe add two loops or loop to 16 and add an if (i < 8) inside? BR, Jani. > + else if (IS_GEN3(dev) || IS_GEN2(dev)) > for (i = 0; i < 8; i++) > error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); > - break; > - > - default: > - BUG(); > - } > + else if (IS_GEN5(dev) || IS_GEN4(dev)) > + for (i = 0; i < 16; i++) > + error->fence[i] = I915_READ64(FENCE_REG_965_0 + > + (i * 8)); > + else if (INTEL_INFO(dev)->gen >= 6) > + for (i = 0; i < dev_priv->num_fence_regs; i++) > + error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + > + (i * 8)); > } > > > -- > 1.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/i915: Organize Fence registers for future enablement. 2014-12-04 7:47 ` Jani Nikula @ 2014-12-04 14:48 ` Rodrigo Vivi 2014-12-05 5:33 ` shuang.he 2014-12-16 19:55 ` Paulo Zanoni 0 siblings, 2 replies; 13+ messages in thread From: Rodrigo Vivi @ 2014-12-04 14:48 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi Let's be optimistic that for future platforms this will remain the same and reorg a bit. This reorg in if blocks instead of switch make life easier for future platform support addition. v2: Jani pointed out I was missing reg_830 for some gen3 platforms. So let's make this platforms subcases of Gen checks. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 17 ++++++---------- drivers/gpu/drm/i915/i915_gpu_error.c | 37 ++++++++++++----------------------- 2 files changed, 19 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9d362d3..1b320bd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3271,17 +3271,12 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, "bogus fence setup with stride: 0x%x, tiling mode: %i\n", obj->stride, obj->tiling_mode); - switch (INTEL_INFO(dev)->gen) { - case 9: - case 8: - case 7: - case 6: - case 5: - case 4: i965_write_fence_reg(dev, reg, obj); break; - case 3: i915_write_fence_reg(dev, reg, obj); break; - case 2: i830_write_fence_reg(dev, reg, obj); break; - default: BUG(); - } + if (IS_GEN2(dev)) + i830_write_fence_reg(dev, reg, obj); + else if (IS_GEN3(dev)) + i915_write_fence_reg(dev, reg, obj); + else if (INTEL_INFO(dev)->gen >= 4) + i965_write_fence_reg(dev, reg, obj); /* And similarly be paranoid that no direct access to this region * is reordered to before the fence is installed. diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index c4536e1..7f44835 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -766,32 +766,21 @@ static void i915_gem_record_fences(struct drm_device *dev, struct drm_i915_private *dev_priv = dev->dev_private; int i; - /* Fences */ - switch (INTEL_INFO(dev)->gen) { - case 9: - case 8: - case 7: - case 6: - for (i = 0; i < dev_priv->num_fence_regs; i++) - error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); - break; - case 5: - case 4: - for (i = 0; i < 16; i++) - error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); - break; - case 3: - if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) - for (i = 0; i < 8; i++) - error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); - case 2: + if (IS_GEN3(dev) || IS_GEN2(dev)) { for (i = 0; i < 8; i++) error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); - break; - - default: - BUG(); - } + if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) + for (i = 0; i < 8; i++) + error->fence[i+8] = I915_READ(FENCE_REG_945_8 + + (i * 4)); + } else if (IS_GEN5(dev) || IS_GEN4(dev)) + for (i = 0; i < 16; i++) + error->fence[i] = I915_READ64(FENCE_REG_965_0 + + (i * 8)); + else if (INTEL_INFO(dev)->gen >= 6) + for (i = 0; i < dev_priv->num_fence_regs; i++) + error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + + (i * 8)); } -- 1.9.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915: Organize Fence registers for future enablement. 2014-12-04 14:48 ` [PATCH] " Rodrigo Vivi @ 2014-12-05 5:33 ` shuang.he 2014-12-16 19:55 ` Paulo Zanoni 1 sibling, 0 replies; 13+ messages in thread From: shuang.he @ 2014-12-05 5:33 UTC (permalink / raw) To: shuang.he, intel-gfx, rodrigo.vivi Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied PNV 364/364 364/364 ILK -1 366/366 365/366 SNB 450/450 450/450 IVB +16 481/498 497/498 BYT 289/289 289/289 HSW 564/564 564/564 BDW 417/417 417/417 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied ILK igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible DMESG_WARN(1, M26)PASS(2, M37M26) DMESG_WARN(1, M26) IVB igt_kms_3d DMESG_WARN(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-128x128-onscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-128x128-random NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-128x128-sliding NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) *IVB igt_kms_cursor_crc_cursor-256x256-offscreen NSPT(1, M34)PASS(10, M4M34M21) DMESG_WARN(1, M21) IVB igt_kms_cursor_crc_cursor-256x256-onscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-256x256-sliding NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-64x64-offscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-64x64-onscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-64x64-random NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-64x64-sliding NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_cursor_crc_cursor-size-change NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_fence_pin_leak NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_rotation_crc_primary-rotation NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) IVB igt_kms_rotation_crc_sprite-rotation NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21) Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915: Organize Fence registers for future enablement. 2014-12-04 14:48 ` [PATCH] " Rodrigo Vivi 2014-12-05 5:33 ` shuang.he @ 2014-12-16 19:55 ` Paulo Zanoni 1 sibling, 0 replies; 13+ messages in thread From: Paulo Zanoni @ 2014-12-16 19:55 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Jani Nikula, Intel Graphics Development 2014-12-04 12:48 GMT-02:00 Rodrigo Vivi <rodrigo.vivi@intel.com>: > Let's be optimistic that for future platforms this will remain the same > and reorg a bit. > This reorg in if blocks instead of switch make life easier for future > platform support addition. > > v2: Jani pointed out I was missing reg_830 for some gen3 platforms. So let's make > this platforms subcases of Gen checks. > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (but I would personally have kept the switch statements and just inverted their order and the default case) > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Damien Lespiau <damien.lespiau@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_gem.c | 17 ++++++---------- > drivers/gpu/drm/i915/i915_gpu_error.c | 37 ++++++++++++----------------------- > 2 files changed, 19 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 9d362d3..1b320bd 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3271,17 +3271,12 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, > "bogus fence setup with stride: 0x%x, tiling mode: %i\n", > obj->stride, obj->tiling_mode); > > - switch (INTEL_INFO(dev)->gen) { > - case 9: > - case 8: > - case 7: > - case 6: > - case 5: > - case 4: i965_write_fence_reg(dev, reg, obj); break; > - case 3: i915_write_fence_reg(dev, reg, obj); break; > - case 2: i830_write_fence_reg(dev, reg, obj); break; > - default: BUG(); > - } > + if (IS_GEN2(dev)) > + i830_write_fence_reg(dev, reg, obj); > + else if (IS_GEN3(dev)) > + i915_write_fence_reg(dev, reg, obj); > + else if (INTEL_INFO(dev)->gen >= 4) > + i965_write_fence_reg(dev, reg, obj); > > /* And similarly be paranoid that no direct access to this region > * is reordered to before the fence is installed. > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index c4536e1..7f44835 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -766,32 +766,21 @@ static void i915_gem_record_fences(struct drm_device *dev, > struct drm_i915_private *dev_priv = dev->dev_private; > int i; > > - /* Fences */ > - switch (INTEL_INFO(dev)->gen) { > - case 9: > - case 8: > - case 7: > - case 6: > - for (i = 0; i < dev_priv->num_fence_regs; i++) > - error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); > - break; > - case 5: > - case 4: > - for (i = 0; i < 16; i++) > - error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); > - break; > - case 3: > - if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) > - for (i = 0; i < 8; i++) > - error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); > - case 2: > + if (IS_GEN3(dev) || IS_GEN2(dev)) { > for (i = 0; i < 8; i++) > error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); > - break; > - > - default: > - BUG(); > - } > + if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) > + for (i = 0; i < 8; i++) > + error->fence[i+8] = I915_READ(FENCE_REG_945_8 + > + (i * 4)); > + } else if (IS_GEN5(dev) || IS_GEN4(dev)) > + for (i = 0; i < 16; i++) > + error->fence[i] = I915_READ64(FENCE_REG_965_0 + > + (i * 8)); > + else if (INTEL_INFO(dev)->gen >= 6) > + for (i = 0; i < dev_priv->num_fence_regs; i++) > + error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + > + (i * 8)); > } > > > -- > 1.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/5] drm/i915: Organize PPGTT init 2014-12-03 12:55 [PATCH 0/5] reorg for future Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 1/5] drm/i915: Organize Fence registers for future enablement Rodrigo Vivi @ 2014-12-03 12:55 ` Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 3/5] drm/i915: Organize PDP regs report for future Rodrigo Vivi ` (3 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: Rodrigo Vivi @ 2014-12-03 12:55 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Let's be optimistic that for future platforms memory management doesn't change that much and reuse gen8 function for PPGTT init. Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 171f6ea..fb28bd7 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1102,10 +1102,8 @@ static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) if (INTEL_INFO(dev)->gen < 8) return gen6_ppgtt_init(ppgtt); - else if (IS_GEN8(dev) || IS_GEN9(dev)) - return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); else - BUG(); + return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); } int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) { -- 1.9.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/5] drm/i915: Organize PDP regs report for future. 2014-12-03 12:55 [PATCH 0/5] reorg for future Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 1/5] drm/i915: Organize Fence registers for future enablement Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 2/5] drm/i915: Organize PPGTT init Rodrigo Vivi @ 2014-12-03 12:55 ` Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 4/5] drm/i915: Organize INSTDONE " Rodrigo Vivi ` (2 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: Rodrigo Vivi @ 2014-12-03 12:55 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Let's be optimistic that for future platforms this will remain the same and reorg a bit. This reorg in if blocks instead of switch make life easier for future platform support addition. Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_gpu_error.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index f117a1d..e8edafe 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -914,9 +914,13 @@ static void i915_record_ring_state(struct drm_device *dev, ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); - switch (INTEL_INFO(dev)->gen) { - case 9: - case 8: + if (IS_GEN6(dev)) + ering->vm_info.pp_dir_base = + I915_READ(RING_PP_DIR_BASE_READ(ring)); + else if (IS_GEN7(dev)) + ering->vm_info.pp_dir_base = + I915_READ(RING_PP_DIR_BASE(ring)); + else if (INTEL_INFO(dev)->gen >= 8) for (i = 0; i < 4; i++) { ering->vm_info.pdp[i] = I915_READ(GEN8_RING_PDP_UDW(ring, i)); @@ -924,16 +928,6 @@ static void i915_record_ring_state(struct drm_device *dev, ering->vm_info.pdp[i] |= I915_READ(GEN8_RING_PDP_LDW(ring, i)); } - break; - case 7: - ering->vm_info.pp_dir_base = - I915_READ(RING_PP_DIR_BASE(ring)); - break; - case 6: - ering->vm_info.pp_dir_base = - I915_READ(RING_PP_DIR_BASE_READ(ring)); - break; - } } } -- 1.9.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/5] drm/i915: Organize INSTDONE report for future. 2014-12-03 12:55 [PATCH 0/5] reorg for future Rodrigo Vivi ` (2 preceding siblings ...) 2014-12-03 12:55 ` [PATCH 3/5] drm/i915: Organize PDP regs report for future Rodrigo Vivi @ 2014-12-03 12:55 ` Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 5/5] drm/i915: Organize bind_vma funcs Rodrigo Vivi 2014-12-16 20:12 ` [PATCH 0/5] reorg for future Paulo Zanoni 5 siblings, 0 replies; 13+ messages in thread From: Rodrigo Vivi @ 2014-12-03 12:55 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Let's be optimistic that for future platforms this will remain the same and reorg a bit. This reorg in if blocks instead of switch make life easier for future platform support addition. Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_gpu_error.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index e8edafe..ee1fa67 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1360,26 +1360,15 @@ void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) struct drm_i915_private *dev_priv = dev->dev_private; memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); - switch (INTEL_INFO(dev)->gen) { - case 2: - case 3: + if (IS_GEN2(dev) || IS_GEN3(dev)) instdone[0] = I915_READ(INSTDONE); - break; - case 4: - case 5: - case 6: + else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { instdone[0] = I915_READ(INSTDONE_I965); instdone[1] = I915_READ(INSTDONE1); - break; - default: - WARN_ONCE(1, "Unsupported platform\n"); - case 7: - case 8: - case 9: + } else if (INTEL_INFO(dev)->gen >= 7) { instdone[0] = I915_READ(GEN7_INSTDONE_1); instdone[1] = I915_READ(GEN7_SC_INSTDONE); instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); instdone[3] = I915_READ(GEN7_ROW_INSTDONE); - break; } } -- 1.9.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/5] drm/i915: Organize bind_vma funcs 2014-12-03 12:55 [PATCH 0/5] reorg for future Rodrigo Vivi ` (3 preceding siblings ...) 2014-12-03 12:55 ` [PATCH 4/5] drm/i915: Organize INSTDONE " Rodrigo Vivi @ 2014-12-03 12:55 ` Rodrigo Vivi 2014-12-04 13:51 ` shuang.he 2014-12-16 20:12 ` [PATCH 0/5] reorg for future Paulo Zanoni 5 siblings, 1 reply; 13+ messages in thread From: Rodrigo Vivi @ 2014-12-03 12:55 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Let's be optimistic that for future platforms this will remain the same and reorg a bit. This reorg in if blocks instead of switch make life easier for future platform support addition. Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index fb28bd7..5d56cc9 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2175,11 +2175,7 @@ static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, vma->vm = vm; vma->obj = obj; - switch (INTEL_INFO(vm->dev)->gen) { - case 9: - case 8: - case 7: - case 6: + if (INTEL_INFO(vm->dev)->gen >= 6) { if (i915_is_ggtt(vm)) { vma->unbind_vma = ggtt_unbind_vma; vma->bind_vma = ggtt_bind_vma; @@ -2187,17 +2183,10 @@ static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, vma->unbind_vma = ppgtt_unbind_vma; vma->bind_vma = ppgtt_bind_vma; } - break; - case 5: - case 4: - case 3: - case 2: + } else { BUG_ON(!i915_is_ggtt(vm)); vma->unbind_vma = i915_ggtt_unbind_vma; vma->bind_vma = i915_ggtt_bind_vma; - break; - default: - BUG(); } /* Keep GGTT vmas first to make debug easier */ -- 1.9.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] drm/i915: Organize bind_vma funcs 2014-12-03 12:55 ` [PATCH 5/5] drm/i915: Organize bind_vma funcs Rodrigo Vivi @ 2014-12-04 13:51 ` shuang.he 0 siblings, 0 replies; 13+ messages in thread From: shuang.he @ 2014-12-04 13:51 UTC (permalink / raw) To: shuang.he, intel-gfx, rodrigo.vivi Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied PNV -1 364/364 363/364 ILK +1-1 365/366 365/366 SNB 450/450 450/450 IVB -1 498/498 497/498 BYT 289/289 289/289 HSW 564/564 564/564 BDW 417/417 417/417 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied *PNV igt_gem_tiled_partial_pwrite_pread_writes PASS(2, M25M23) NO_RESULT(1, M23) *ILK igt_kms_flip_rcs-flip-vs-panning PASS(2, M26) DMESG_WARN(1, M26) ILK igt_kms_flip_wf_vblank-ts-check DMESG_WARN(2, M26)PASS(18, M26M37) PASS(1, M26) *IVB igt_kms_cursor_crc_cursor-64x64-sliding FAIL(1, M21)NSPT(4, M34)PASS(2, M34M21) DMESG_WARN(1, M21) Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 0/5] reorg for future 2014-12-03 12:55 [PATCH 0/5] reorg for future Rodrigo Vivi ` (4 preceding siblings ...) 2014-12-03 12:55 ` [PATCH 5/5] drm/i915: Organize bind_vma funcs Rodrigo Vivi @ 2014-12-16 20:12 ` Paulo Zanoni 2014-12-17 17:19 ` Daniel Vetter 5 siblings, 1 reply; 13+ messages in thread From: Paulo Zanoni @ 2014-12-16 20:12 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Intel Graphics Development 2014-12-03 10:55 GMT-02:00 Rodrigo Vivi <rodrigo.vivi@intel.com>: > This entire series has no functional change on current supported platforms and it isn't based on any spec. > > This is just a reorg that will help on future. > > It is true that removing BUG() for unsupported platforms we miss the warn when enabling new platforms. > But most of the time we just do what these patches are doing now and check for changes later anyway. > So this aims to make life easier. > > Rodrigo Vivi (5): > drm/i915: Organize Fence registers for future enablement. > drm/i915: Organize PPGTT init > drm/i915: Organize PDP regs report for future. > drm/i915: Organize INSTDONE report for future. > drm/i915: Organize bind_vma funcs For all the patches (which includes v2 of p1): Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > drivers/gpu/drm/i915/i915_gem.c | 17 +++----- > drivers/gpu/drm/i915/i915_gem_gtt.c | 19 ++------- > drivers/gpu/drm/i915/i915_gpu_error.c | 74 +++++++++++------------------------ > 3 files changed, 32 insertions(+), 78 deletions(-) > > -- > 1.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 0/5] reorg for future 2014-12-16 20:12 ` [PATCH 0/5] reorg for future Paulo Zanoni @ 2014-12-17 17:19 ` Daniel Vetter 0 siblings, 0 replies; 13+ messages in thread From: Daniel Vetter @ 2014-12-17 17:19 UTC (permalink / raw) To: Paulo Zanoni; +Cc: Intel Graphics Development, Rodrigo Vivi On Tue, Dec 16, 2014 at 06:12:27PM -0200, Paulo Zanoni wrote: > 2014-12-03 10:55 GMT-02:00 Rodrigo Vivi <rodrigo.vivi@intel.com>: > > This entire series has no functional change on current supported platforms and it isn't based on any spec. > > > > This is just a reorg that will help on future. > > > > It is true that removing BUG() for unsupported platforms we miss the warn when enabling new platforms. > > But most of the time we just do what these patches are doing now and check for changes later anyway. > > So this aims to make life easier. > > > > Rodrigo Vivi (5): > > drm/i915: Organize Fence registers for future enablement. > > drm/i915: Organize PPGTT init > > drm/i915: Organize PDP regs report for future. > > drm/i915: Organize INSTDONE report for future. > > drm/i915: Organize bind_vma funcs > > For all the patches (which includes v2 of p1): Reviewed-by: Paulo > Zanoni <paulo.r.zanoni@intel.com> All merged, thanks for patches&review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2014-12-17 17:19 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-12-03 12:55 [PATCH 0/5] reorg for future Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 1/5] drm/i915: Organize Fence registers for future enablement Rodrigo Vivi 2014-12-04 7:47 ` Jani Nikula 2014-12-04 14:48 ` [PATCH] " Rodrigo Vivi 2014-12-05 5:33 ` shuang.he 2014-12-16 19:55 ` Paulo Zanoni 2014-12-03 12:55 ` [PATCH 2/5] drm/i915: Organize PPGTT init Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 3/5] drm/i915: Organize PDP regs report for future Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 4/5] drm/i915: Organize INSTDONE " Rodrigo Vivi 2014-12-03 12:55 ` [PATCH 5/5] drm/i915: Organize bind_vma funcs Rodrigo Vivi 2014-12-04 13:51 ` shuang.he 2014-12-16 20:12 ` [PATCH 0/5] reorg for future Paulo Zanoni 2014-12-17 17:19 ` Daniel Vetter
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