[PATCH v1 0/8] Enable/Disable DC balance along with VRR DSB

[PATCH v1 0/8] Enable/Disable DC balance along with VRR DSB

[Mitul Golani]

Control DC Balance Adjustment bit to accomodate changes along
with VRR DSB implementation.

Mitul Golani (8):
  drm/i915/vrr: Add DC balance registers
  drm/i915/dmc: Add pipe DMC DC balance registers
  drm/i915/vrr: Refactor vmin/vmax stuff
  drm/i915/vrr: Add functions to read out vmin/vmax stuff
  drm/i915: Extract vrr_vblank_start()
  drm/i915/vrr: Implement vblank evasion with DC balancing
  drm/i915/dsb: Add pipedmc dc balance enable/disable
  drm/i915/vrr: Pause DC balancing for DSB commits

 drivers/gpu/drm/i915/display/intel_display.c  |  13 ++
 .../drm/i915/display/intel_display_types.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      |  16 ++
 drivers/gpu/drm/i915/display/intel_dmc.h      |   5 +
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |  37 +++++
 drivers/gpu/drm/i915/display/intel_dsb.c      |  31 +++-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  33 ++++-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 138 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_vrr.h      |   5 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  43 ++++++
 10 files changed, 284 insertions(+), 39 deletions(-)

-- 
2.48.1

[PATCH v1 1/8] drm/i915/vrr: Add DC balance registers

[Mitul Golani]

Add register to access DC Balance registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 43 +++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 6ed0e0dc97e7..6297108f1357 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -9,6 +9,20 @@
 #include "intel_display_reg_defs.h"
 
 /* VRR registers */
+#define _TRANS_VRR_VMAX_DCB_A			0x60414 /* lnl+ */
+#define _TRANS_VRR_VMAX_DCB_B			0x61414 /* lnl+ */
+#define TRANS_VRR_VMAX_DCB(trans)		_MMIO_TRANS((trans), \
+							    _TRANS_VRR_VMAX_DCB_A, \
+							    _TRANS_VRR_VMAX_DCB_B)
+#define VRR_VMAX_DCB_MASK			REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_FLIPLINE_DCB_A		0x60418 /* lnl+ */
+#define _TRANS_VRR_FLIPLINE_DCB_B		0x61418 /* lnl+ */
+#define TRANS_VRR_FLIPLINE_DCB(trans)		_MMIO_TRANS((trans), \
+							    _TRANS_VRR_FLIPLINE_DCB_A, \
+							    _TRANS_VRR_FLIPLINE_DCB_B)
+#define VRR_FLIPLINE_DCB_MASK			REG_GENMASK(19, 0)
+
 #define _TRANS_VRR_CTL_A			0x60420
 #define _TRANS_VRR_CTL_B			0x61420
 #define _TRANS_VRR_CTL_C			0x62420
@@ -17,6 +31,7 @@
 #define  VRR_CTL_VRR_ENABLE			REG_BIT(31)
 #define  VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
 #define  VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
+#define  VRR_CTL_DCB_ADJ_ENABLE			REG_BIT(28) /* lnl+ */
 #define  VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
 #define  VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
 #define  VRR_CTL_PIPELINE_FULL_OVERRIDE		REG_BIT(0)
@@ -93,6 +108,34 @@
 #define TRANS_VRR_STATUS2(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
 #define  VRR_STATUS2_VERT_LN_CNT_MASK		REG_GENMASK(19, 0)
 
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A		0x604c0 /* lnl+ */
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B		0x614c0 /* lnl+ */
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans)	_MMIO_TRANS((trans), \
+							    _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
+							    _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
+#define  ADAPTIVE_SYNC_COUNTER_EN			REG_BIT(31)
+#define  ADAPTIVE_SYNC_COUNTER_RESET			REG_BIT(30)
+#define  ADAPTIVE_SYNC_ODD_COUNTER_OVERFLOW		REG_BIT(15)
+#define  ADAPTIVE_SYNC_EVEN_COUNTER_OVERFLOW		REG_BIT(14)
+#define  ADAPTIVE_SYNC_ODD_LINE_COUNTER_OVERFLOW	REG_BIT(13)
+#define  ADAPTIVE_SYNC_EVEN_LINE_COUNTER_OVERFLOW	REG_BIT(12)
+
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A	0x604d4 /* lnl+ */
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B	0x614d4 /* lnl+ */
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans)	_MMIO_TRANS((trans), \
+							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
+							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
+#define  VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
+#define  VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A		0x604d8 /* lnl+ */
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B		0x614d8 /* lnl+ */
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans)	_MMIO_TRANS((trans), \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
+#define  VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
+#define  VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
+
 #define _TRANS_PUSH_A				0x60a70
 #define _TRANS_PUSH_B				0x61a70
 #define _TRANS_PUSH_C				0x62a70
-- 
2.48.1

Re: [PATCH v1 1/8] drm/i915/vrr: Add DC balance registers

[Jani Nikula]

On Wed, 16 Apr 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add register to access DC Balance registers.

Please read the comment near the top of i915_reg.h.

BR,
Jani.


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr_regs.h | 43 +++++++++++++++++++
>  1 file changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index 6ed0e0dc97e7..6297108f1357 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -9,6 +9,20 @@
>  #include "intel_display_reg_defs.h"
>  
>  /* VRR registers */
> +#define _TRANS_VRR_VMAX_DCB_A			0x60414 /* lnl+ */
> +#define _TRANS_VRR_VMAX_DCB_B			0x61414 /* lnl+ */
> +#define TRANS_VRR_VMAX_DCB(trans)		_MMIO_TRANS((trans), \
> +							    _TRANS_VRR_VMAX_DCB_A, \
> +							    _TRANS_VRR_VMAX_DCB_B)
> +#define VRR_VMAX_DCB_MASK			REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_FLIPLINE_DCB_A		0x60418 /* lnl+ */
> +#define _TRANS_VRR_FLIPLINE_DCB_B		0x61418 /* lnl+ */
> +#define TRANS_VRR_FLIPLINE_DCB(trans)		_MMIO_TRANS((trans), \
> +							    _TRANS_VRR_FLIPLINE_DCB_A, \
> +							    _TRANS_VRR_FLIPLINE_DCB_B)
> +#define VRR_FLIPLINE_DCB_MASK			REG_GENMASK(19, 0)
> +
>  #define _TRANS_VRR_CTL_A			0x60420
>  #define _TRANS_VRR_CTL_B			0x61420
>  #define _TRANS_VRR_CTL_C			0x62420
> @@ -17,6 +31,7 @@
>  #define  VRR_CTL_VRR_ENABLE			REG_BIT(31)
>  #define  VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
>  #define  VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
> +#define  VRR_CTL_DCB_ADJ_ENABLE			REG_BIT(28) /* lnl+ */
>  #define  VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
>  #define  VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
>  #define  VRR_CTL_PIPELINE_FULL_OVERRIDE		REG_BIT(0)
> @@ -93,6 +108,34 @@
>  #define TRANS_VRR_STATUS2(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
>  #define  VRR_STATUS2_VERT_LN_CNT_MASK		REG_GENMASK(19, 0)
>  
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A		0x604c0 /* lnl+ */
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B		0x614c0 /* lnl+ */
> +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans)	_MMIO_TRANS((trans), \
> +							    _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
> +							    _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
> +#define  ADAPTIVE_SYNC_COUNTER_EN			REG_BIT(31)
> +#define  ADAPTIVE_SYNC_COUNTER_RESET			REG_BIT(30)
> +#define  ADAPTIVE_SYNC_ODD_COUNTER_OVERFLOW		REG_BIT(15)
> +#define  ADAPTIVE_SYNC_EVEN_COUNTER_OVERFLOW		REG_BIT(14)
> +#define  ADAPTIVE_SYNC_ODD_LINE_COUNTER_OVERFLOW	REG_BIT(13)
> +#define  ADAPTIVE_SYNC_EVEN_LINE_COUNTER_OVERFLOW	REG_BIT(12)
> +
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A	0x604d4 /* lnl+ */
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B	0x614d4 /* lnl+ */
> +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans)	_MMIO_TRANS((trans), \
> +							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
> +							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
> +#define  VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
> +#define  VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A		0x604d8 /* lnl+ */
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B		0x614d8 /* lnl+ */
> +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans)	_MMIO_TRANS((trans), \
> +							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
> +							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
> +#define  VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
> +#define  VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
> +
>  #define _TRANS_PUSH_A				0x60a70
>  #define _TRANS_PUSH_B				0x61a70
>  #define _TRANS_PUSH_C				0x62a70

-- 
Jani Nikula, Intel

[PATCH v1 2/8] drm/i915/dmc: Add pipe DMC DC balance registers

[Mitul Golani]

Add pipe registers to access pipe DMC DC Balance registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 1bf446f96a10..5ac409fbbc4e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -103,4 +103,41 @@
 #define  DMC_WAKELOCK_CTL_REQ	 REG_BIT(31)
 #define  DMC_WAKELOCK_CTL_ACK	 REG_BIT(15)
 
+#define _PIPEDMC_DCB_CTL_A		0x5f1a0
+#define _PIPEDMC_DCB_CTL_B		0x5f5a0
+#define PIPEDMC_DCB_CTL(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A, _PIPEDMC_DCB_CTL_B)
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE	REG_BIT(31)
+
+#define _PIPEDMC_DCB_VMIN_A		0x5f1a4
+#define _PIPEDMC_DCB_VMIN_B		0x5f5a4
+#define PIPEDMC_DCB_VMIN(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A, _PIPEDMC_DCB_VMIN_B)
+
+#define _PIPEDMC_DCB_VMAX_A		0x5f1a8
+#define _PIPEDMC_DCB_VMAX_B		0x5f5a8
+#define PIPEDMC_DCB_VMAX(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A, _PIPEDMC_DCB_VMAX_B)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A	0x5f1ac
+#define _PIPEDMC_DCB_MAX_INCREASE_B	0x5f5ac
+#define PIPEDMC_DCB_MAX_INCREASE(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A, _PIPEDMC_DCB_MAX_INCREASE_B)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A	0x5f1b0
+#define _PIPEDMC_DCB_MAX_DECREASE_B	0x5f5b0
+#define PIPEDMC_DCB_MAX_DECREASE(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A, _PIPEDMC_DCB_MAX_DECREASE_B)
+
+#define _PIPEDMC_DCB_GUARDBAND_A	0x5f1b4
+#define _PIPEDMC_DCB_GUARDBAND_B	0x5f5b4
+#define PIPEDMC_DCB_GUARDBAND(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A, _PIPEDMC_DCB_GUARDBAND_B)
+
+#define _PIPEDMC_DCB_SLOPE_A		0x5f1b8
+#define _PIPEDMC_DCB_SLOPE_B		0x5f5b8
+#define PIPEDMC_DCB_SLOPE(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A, _PIPEDMC_DCB_SLOPE_B)
+
+#define _PIPEDMC_DCB_VBLANK_A		0x5f1bc
+#define _PIPEDMC_DCB_VBLANK_B		0x5f5bc
+#define PIPEDMC_DCB_VBLANK(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A, _PIPEDMC_DCB_VBLANK_B)
+
+#define _PIPEDMC_DCB_DEBUG_A		0x5f1c0
+#define _PIPEDMC_DCB_DEBUG_B		0x5f5c0
+#define PIPEDMC_DCB_DEBUG(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_DEBUG_A, _PIPEDMC_DCB_DEBUG_B)
+
 #endif /* __INTEL_DMC_REGS_H__ */
-- 
2.48.1

[PATCH v1 3/8] drm/i915/vrr: Refactor vmin/vmax stuff

[Mitul Golani]

Refactor vmin/vmax functions for better computation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 42 +++++++++++-------------
 1 file changed, 20 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c6565baf815a..afa1728837d2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -146,37 +146,42 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
 		return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
 }
 
-int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
+static int intel_vrr_vtotal(const struct intel_crtc_state *crtc_state, int vmin_vmax)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	/* Min vblank actually determined by flipline */
 	if (DISPLAY_VER(display) >= 13)
-		return intel_vrr_vmin_flipline(crtc_state);
+		return vmin_vmax;
 	else
-		return intel_vrr_vmin_flipline(crtc_state) +
-			intel_vrr_real_vblank_delay(crtc_state);
+		return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state);
 }
 
-int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
+
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+	int vmin_vmax)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
+	return intel_vrr_vtotal(crtc_state, vmin_vmax) -
+			intel_vrr_vblank_exit_length(crtc_state);
+}
 
-	if (DISPLAY_VER(display) >= 13)
-		return crtc_state->vrr.vmax;
-	else
-		return crtc_state->vrr.vmax +
-			intel_vrr_real_vblank_delay(crtc_state);
+int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
+{
+	return intel_vrr_vtotal(crtc_state, intel_vrr_vmin_flipline(crtc_state));
+}
+
+int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
+{
+	return intel_vrr_vtotal(crtc_state, crtc_state->vrr.vmax);
 }
 
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+	return intel_vrr_vblank_start(crtc_state, intel_vrr_vmin_flipline(crtc_state));
 }
 
 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+	return intel_vrr_vblank_start(crtc_state, crtc_state->vrr.vmax);
 }
 
 static bool
@@ -257,14 +262,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
 static
 int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
-	int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
-
-	if (DISPLAY_VER(display) >= 13)
-		return crtc_vtotal;
-	else
-		return crtc_vtotal -
-			intel_vrr_real_vblank_delay(crtc_state);
+	return intel_vrr_vtotal(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
 }
 
 static
-- 
2.48.1

[PATCH v1 4/8] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Mitul Golani]

Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 55 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vrr.h |  5 +++
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index afa1728837d2..03405c274b8c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -156,7 +156,6 @@ static int intel_vrr_vtotal(const struct intel_crtc_state *crtc_state, int vmin_
 		return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state);
 }
 
-
 static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
 	int vmin_vmax)
 {
@@ -747,3 +746,57 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_DCB_ADJ_VMAX_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp;
+
+	tmp = intel_de_read(display, TRANS_VRR_FLIPLINE_DCB(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp;
+
+	tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 38bf9996b883..e62b8b50aec6 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1

[PATCH v1 5/8] drm/i915: Extract vrr_vblank_start()

[Mitul Golani]

Initialise delayed vblank position for evasion logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 139fa5deba80..680013f00fc0 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -642,6 +642,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 	return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
 }
 
+static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	if (intel_vrr_is_push_sent(crtc_state))
+		return intel_vrr_vmin_vblank_start(crtc_state);
+	else
+		return intel_vrr_vmax_vblank_start(crtc_state);
+}
+
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 			     const struct intel_crtc_state *new_crtc_state,
 			     struct intel_vblank_evade_ctx *evade)
@@ -668,10 +676,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
 			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
 
-		if (intel_vrr_is_push_sent(crtc_state))
-			evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-		else
-			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+		evade->vblank_start = vrr_vblank_start(crtc_state);
 
 		vblank_delay = intel_vrr_vblank_delay(crtc_state);
 	} else {
-- 
2.48.1

[PATCH v1 6/8] drm/i915/vrr: Implement vblank evasion with DC balancing

[Mitul Golani]

Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_dsb.c      | 31 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c   | 26 ++++++++++++++--
 3 files changed, 54 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 94468a9d2e0d..0e06c71e9086 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1303,7 +1303,7 @@ struct intel_crtc_state {
 
 	/* Variable Refresh Rate state */
 	struct {
-		bool enable, in_range;
+		bool enable, in_range, dc_balance;
 		u8 pipeline_full;
 		u16 flipline, vmin, vmax, guardband;
 		u32 vsync_end, vsync_start;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 72fe390c5af2..ed27cbff44fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -577,7 +577,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 	if (crtc_state->has_psr)
 		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
 
-	if (pre_commit_is_vrr_active(state, crtc)) {
+	if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance) {
+		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
+		int vmin_vblank_start, vmax_vblank_start;
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+		if (vmin_vblank_start >= 0) {
+			end = vmin_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+		if (vmax_vblank_start >= 0) {
+			end = vmax_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+		end = vmin_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+		end = vmax_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+	} else if (pre_commit_is_vrr_active(state, crtc)) {
 		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
 
 		end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 680013f00fc0..9b63e4217881 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -644,10 +644,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 
 static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	if (intel_vrr_is_push_sent(crtc_state))
-		return intel_vrr_vmin_vblank_start(crtc_state);
+	bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+	int vblank_start;
+
+	if (!crtc_state->vrr.dc_balance) {
+		if (is_push_sent)
+			return intel_vrr_vmin_vblank_start(crtc_state);
+		else
+			return intel_vrr_vmax_vblank_start(crtc_state);
+	}
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
 	else
-		return intel_vrr_vmax_vblank_start(crtc_state);
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+	if (vblank_start >= 0)
+		return vblank_start;
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+	else
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+	return vblank_start;
 }
 
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
-- 
2.48.1

[PATCH v1 7/8] drm/i915/dsb: Add pipedmc dc balance enable/disable

[Mitul Golani]

Add function to control DC balance enable/disable bit via DSB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 16 ++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dmc.h |  5 +++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 98f80a6c63e8..17835b297f6d 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -30,6 +30,7 @@
 #include "intel_de.h"
 #include "intel_display_rpm.h"
 #include "intel_display_power_well.h"
+#include "intel_display_types.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_step.h"
@@ -1362,3 +1363,18 @@ void intel_dmc_debugfs_register(struct intel_display *display)
 	debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
 			    display, &intel_dmc_debugfs_status_fops);
 }
+
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(crtc->pipe),
+			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
+}
+
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(crtc->pipe), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index c78426eb4cd5..74dcd142f5b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -10,8 +10,10 @@
 
 enum pipe;
 struct drm_printer;
+struct intel_crtc;
 struct intel_display;
 struct intel_dmc_snapshot;
+struct intel_dsb;
 
 void intel_dmc_init(struct intel_display *display);
 void intel_dmc_load_program(struct intel_display *display);
@@ -30,4 +32,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
 
 void assert_dmc_loaded(struct intel_display *display);
 
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+
 #endif /* __INTEL_DMC_H__ */
-- 
2.48.1

[PATCH v1 8/8] drm/i915/vrr: Pause DC balancing for DSB commits

[Mitul Golani]

Pause the DMC DC balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++
 drivers/gpu/drm/i915/display/intel_vrr.c     | 43 +++++++++++++++-----
 2 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db524d01e574..7373c11e6e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7195,6 +7195,17 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	}
 
 	if (new_crtc_state->use_dsb) {
+		/*
+		 * Pause the DMC DC balancing for the remainder of the
+		 * commit so that vmin/vmax won't change after we've baked
+		 * them into the DSB vblank evasion commands.
+		 *
+		 * FIXME maybe need a small delay here to make sure DMC has
+		 * finished updating the values? Or we need a better DMC<->driver
+		 * protocol that gives is real guarantees about that...
+		 */
+		intel_pipedmc_dcb_disable(NULL, crtc);
+
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
 						 new_crtc_state);
@@ -7231,6 +7242,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
 			intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
 			intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
+			if (new_crtc_state->vrr.dc_balance)
+				intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
 			intel_dsb_interrupt(new_crtc_state->dsb_commit);
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 03405c274b8c..18c38afb9108 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_dmc.h"
 #include "intel_dp.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
@@ -576,7 +577,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 ctl;
 
 	if (!crtc_state->vrr.enable)
 		return;
@@ -587,33 +590,51 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 		       crtc_state->vrr.vmax - 1);
 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
 		       crtc_state->vrr.flipline - 1);
+	if (!intel_vrr_always_use_vrr_tg(display))
+		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
 
 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
 		       TRANS_PUSH_EN);
 
-	if (!intel_vrr_always_use_vrr_tg(display)) {
-		if (crtc_state->cmrr.enable) {
-			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-				       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
-				       trans_vrr_ctl(crtc_state));
-		} else {
-			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
-		}
+	ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
+	if (crtc_state->cmrr.enable)
+		ctl |= VRR_CTL_CMRR_ENABLE;
+	if (crtc_state->vrr.dc_balance)
+		ctl |= VRR_CTL_DCB_ADJ_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
+
+	if (crtc_state->vrr.dc_balance) {
+		/* FIXME reset counters? */
+		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
+			       ADAPTIVE_SYNC_COUNTER_EN);
+		/* FIMXE configure pipedmc DC balance parameters somewhere */
+		intel_pipedmc_dcb_enable(NULL, crtc);
 	}
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+	u32 ctl;
 
 	if (!old_crtc_state->vrr.enable)
 		return;
 
+	if (old_crtc_state->vrr.dc_balance) {
+		intel_pipedmc_dcb_disable(NULL, crtc);
+		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
+	}
+
+	ctl = trans_vrr_ctl(old_crtc_state);
+	if (intel_vrr_always_use_vrr_tg(display))
+		ctl |= VRR_CTL_VRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
+
 	if (!intel_vrr_always_use_vrr_tg(display)) {
-		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-			       trans_vrr_ctl(old_crtc_state));
 		intel_de_wait_for_clear(display,
 					TRANS_VRR_STATUS(display, cpu_transcoder),
 					VRR_STATUS_VRR_EN_LIVE, 1000);
-- 
2.48.1

✗ Fi.CI.CHECKPATCH: warning for Enable/Disable DC balance along with VRR DSB

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/147799/
State : warning

== Summary ==

Error: dim checkpatch failed
7b2e46a2d56f drm/i915/vrr: Add DC balance registers
-:80: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>'

total: 1 errors, 0 warnings, 0 checks, 61 lines checked
8ef5cb29300f drm/i915/dmc: Add pipe DMC DC balance registers
-:36: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#36: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:121:
+#define PIPEDMC_DCB_MAX_INCREASE(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A, _PIPEDMC_DCB_MAX_INCREASE_B)

-:40: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:125:
+#define PIPEDMC_DCB_MAX_DECREASE(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A, _PIPEDMC_DCB_MAX_DECREASE_B)

-:44: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:129:
+#define PIPEDMC_DCB_GUARDBAND(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A, _PIPEDMC_DCB_GUARDBAND_B)

-:48: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#48: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:133:
+#define PIPEDMC_DCB_SLOPE(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A, _PIPEDMC_DCB_SLOPE_B)

-:52: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:137:
+#define PIPEDMC_DCB_VBLANK(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A, _PIPEDMC_DCB_VBLANK_B)

-:56: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#56: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:141:
+#define PIPEDMC_DCB_DEBUG(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_DEBUG_A, _PIPEDMC_DCB_DEBUG_B)

-:58: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>'

total: 1 errors, 6 warnings, 0 checks, 41 lines checked
a478f2e5dc6e drm/i915/vrr: Refactor vmin/vmax stuff
-:37: CHECK:LINE_SPACING: Please don't use multiple blank lines
#37: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:159:
 
+

-:39: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#39: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:161:
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+	int vmin_vmax)

-:89: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>'

total: 1 errors, 0 warnings, 2 checks, 71 lines checked
1d2dc6503782 drm/i915/vrr: Add functions to read out vmin/vmax stuff
-:97: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>'

total: 1 errors, 0 warnings, 0 checks, 73 lines checked
d6066260ed78 drm/i915: Extract vrr_vblank_start()
-:43: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>'

total: 1 errors, 0 warnings, 0 checks, 25 lines checked
4e957667b701 drm/i915/vrr: Implement vblank evasion with DC balancing
-:106: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>'

total: 1 errors, 0 warnings, 0 checks, 78 lines checked
ed86467997cd drm/i915/dsb: Add pipedmc dc balance enable/disable
-:66: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>'

total: 1 errors, 0 warnings, 0 checks, 42 lines checked
30dc1e414952 drm/i915/vrr: Pause DC balancing for DSB commits
-:130: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>'

total: 1 errors, 0 warnings, 0 checks, 103 lines checked

✗ i915.CI.BAT: failure for Enable/Disable DC balance along with VRR DSB

[Patchwork]

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== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/147799/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16423 -> Patchwork_147799v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_147799v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_147799v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/index.html

Participating hosts (45 -> 45)
------------------------------

  Additional (1): bat-jsl-4 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_147799v1:

### IGT changes ###

#### Possible regressions ####

  * igt@fbdev@write:
    - bat-adls-6:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-adls-6/igt@fbdev@write.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-adls-6/igt@fbdev@write.html

  * igt@gem_close_race@basic-process:
    - bat-mtlp-9:         [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-mtlp-9/igt@gem_close_race@basic-process.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-mtlp-9/igt@gem_close_race@basic-process.html

  * igt@i915_module_load@load:
    - bat-rpls-4:         [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-rpls-4/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-rpls-4/igt@i915_module_load@load.html
    - bat-dg2-11:         [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-dg2-11/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-dg2-11/igt@i915_module_load@load.html
    - bat-dg2-14:         [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-dg2-14/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-dg2-14/igt@i915_module_load@load.html

  * igt@kms_busy@basic@modeset:
    - bat-dg2-9:          [PASS][11] -> [ABORT][12] +1 other test abort
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-dg2-9/igt@kms_busy@basic@modeset.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-dg2-9/igt@kms_busy@basic@modeset.html

  * igt@kms_chamelium_edid@dp-edid-read:
    - bat-dg2-13:         [PASS][13] -> [ABORT][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
    - bat-arls-6:         [PASS][15] -> [ABORT][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-arls-6/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-arls-6/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-plain-flip@d-dp1:
    - bat-dg2-8:          [PASS][17] -> [ABORT][18] +1 other test abort
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/bat-dg2-8/igt@kms_flip@basic-plain-flip@d-dp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/bat-dg2-8/igt@kms_flip@basic-plain-flip@d-dp1.html

  
Known issues
------------

  Here are the changes found in Patchwork_147799v1 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-bsw-nick:        [INCOMPLETE][19] ([i915#12904]) -> [PASS][20] +1 other test pass
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16423/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13950]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13950


Build changes
-------------

  * Linux: CI_DRM_16423 -> Patchwork_147799v1

  CI-20190529: 20190529
  CI_DRM_16423: b8f79cb562e983515cf827f0f336f79423b8d5a7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8320: cd3b5612be3cef838f16e074bf1bc421399d584d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_147799v1: b8f79cb562e983515cf827f0f336f79423b8d5a7 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v1/index.html

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Re: [PATCH v1 0/8] Enable/Disable DC balance along with VRR DSB

[Ville Syrjälä]

On Wed, Apr 16, 2025 at 11:57:29AM +0530, Mitul Golani wrote:
> Control DC Balance Adjustment bit to accomodate changes along
> with VRR DSB implementation.
> 
> Mitul Golani (8):
>   drm/i915/vrr: Add DC balance registers
>   drm/i915/dmc: Add pipe DMC DC balance registers
>   drm/i915/vrr: Refactor vmin/vmax stuff
>   drm/i915/vrr: Add functions to read out vmin/vmax stuff
>   drm/i915: Extract vrr_vblank_start()
>   drm/i915/vrr: Implement vblank evasion with DC balancing
>   drm/i915/dsb: Add pipedmc dc balance enable/disable
>   drm/i915/vrr: Pause DC balancing for DSB commits

Looks like you've messed up the authorship of most of these.

> 
>  drivers/gpu/drm/i915/display/intel_display.c  |  13 ++
>  .../drm/i915/display/intel_display_types.h    |   2 +-
>  drivers/gpu/drm/i915/display/intel_dmc.c      |  16 ++
>  drivers/gpu/drm/i915/display/intel_dmc.h      |   5 +
>  drivers/gpu/drm/i915/display/intel_dmc_regs.h |  37 +++++
>  drivers/gpu/drm/i915/display/intel_dsb.c      |  31 +++-
>  drivers/gpu/drm/i915/display/intel_vblank.c   |  33 ++++-
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 138 +++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_vrr.h      |   5 +
>  drivers/gpu/drm/i915/display/intel_vrr_regs.h |  43 ++++++
>  10 files changed, 284 insertions(+), 39 deletions(-)
> 
> -- 
> 2.48.1

-- 
Ville Syrjälä
Intel

Re: [PATCH v1 0/8] Enable/Disable DC balance along with VRR DSB

[Ville Syrjälä]

On Wed, Apr 16, 2025 at 06:07:00PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 16, 2025 at 11:57:29AM +0530, Mitul Golani wrote:
> > Control DC Balance Adjustment bit to accomodate changes along
> > with VRR DSB implementation.
> > 
> > Mitul Golani (8):
> >   drm/i915/vrr: Add DC balance registers
> >   drm/i915/dmc: Add pipe DMC DC balance registers
> >   drm/i915/vrr: Refactor vmin/vmax stuff
> >   drm/i915/vrr: Add functions to read out vmin/vmax stuff
> >   drm/i915: Extract vrr_vblank_start()
> >   drm/i915/vrr: Implement vblank evasion with DC balancing
> >   drm/i915/dsb: Add pipedmc dc balance enable/disable
> >   drm/i915/vrr: Pause DC balancing for DSB commits
> 
> Looks like you've messed up the authorship of most of these.

Thse in fact just look like what I had. Where is the stuff to
actually program the DC balance parameters?

> 
> > 
> >  drivers/gpu/drm/i915/display/intel_display.c  |  13 ++
> >  .../drm/i915/display/intel_display_types.h    |   2 +-
> >  drivers/gpu/drm/i915/display/intel_dmc.c      |  16 ++
> >  drivers/gpu/drm/i915/display/intel_dmc.h      |   5 +
> >  drivers/gpu/drm/i915/display/intel_dmc_regs.h |  37 +++++
> >  drivers/gpu/drm/i915/display/intel_dsb.c      |  31 +++-
> >  drivers/gpu/drm/i915/display/intel_vblank.c   |  33 ++++-
> >  drivers/gpu/drm/i915/display/intel_vrr.c      | 138 +++++++++++++-----
> >  drivers/gpu/drm/i915/display/intel_vrr.h      |   5 +
> >  drivers/gpu/drm/i915/display/intel_vrr_regs.h |  43 ++++++
> >  10 files changed, 284 insertions(+), 39 deletions(-)
> > 
> > -- 
> > 2.48.1
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

RE: [PATCH v1 0/8] Enable/Disable DC balance along with VRR DSB

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: 16 April 2025 20:43
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v1 0/8] Enable/Disable DC balance along with VRR DSB
> 
> On Wed, Apr 16, 2025 at 06:07:00PM +0300, Ville Syrjälä wrote:
> > On Wed, Apr 16, 2025 at 11:57:29AM +0530, Mitul Golani wrote:
> > > Control DC Balance Adjustment bit to accomodate changes along with
> > > VRR DSB implementation.
> > >
> > > Mitul Golani (8):
> > >   drm/i915/vrr: Add DC balance registers
> > >   drm/i915/dmc: Add pipe DMC DC balance registers
> > >   drm/i915/vrr: Refactor vmin/vmax stuff
> > >   drm/i915/vrr: Add functions to read out vmin/vmax stuff
> > >   drm/i915: Extract vrr_vblank_start()
> > >   drm/i915/vrr: Implement vblank evasion with DC balancing
> > >   drm/i915/dsb: Add pipedmc dc balance enable/disable
> > >   drm/i915/vrr: Pause DC balancing for DSB commits
> >
> > Looks like you've messed up the authorship of most of these.

Yes. I will update Author and resend along with on xe list

> 
> Thse in fact just look like what I had. Where is the stuff to actually program the
> DC balance parameters?

Actually yes, one more patch required for event trigger and one patch for few more registers. Earlier I thought of to complete your patch series review as there are some independent restructuring. But With next revision I will append my local changes as well.

Thanks,
Mitul

> 
> >
> > >
> > >  drivers/gpu/drm/i915/display/intel_display.c  |  13 ++
> > >  .../drm/i915/display/intel_display_types.h    |   2 +-
> > >  drivers/gpu/drm/i915/display/intel_dmc.c      |  16 ++
> > >  drivers/gpu/drm/i915/display/intel_dmc.h      |   5 +
> > >  drivers/gpu/drm/i915/display/intel_dmc_regs.h |  37 +++++
> > >  drivers/gpu/drm/i915/display/intel_dsb.c      |  31 +++-
> > >  drivers/gpu/drm/i915/display/intel_vblank.c   |  33 ++++-
> > >  drivers/gpu/drm/i915/display/intel_vrr.c      | 138 +++++++++++++-----
> > >  drivers/gpu/drm/i915/display/intel_vrr.h      |   5 +
> > >  drivers/gpu/drm/i915/display/intel_vrr_regs.h |  43 ++++++
> > >  10 files changed, 284 insertions(+), 39 deletions(-)
> > >
> > > --
> > > 2.48.1
> >
> > --
> > Ville Syrjälä
> > Intel
> 
> --
> Ville Syrjälä
> Intel