From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7516C678D5 for ; Wed, 8 Mar 2023 11:27:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 45C0C10E5B9; Wed, 8 Mar 2023 11:27:05 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5ADCE10E5B9; Wed, 8 Mar 2023 11:27:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678274824; x=1709810824; h=from:to:subject:in-reply-to:references:date:message-id: mime-version; bh=aaAMp5abdfHMzxR7YmZ+8IjTgKJMhdB2LBIkRQEh8V4=; b=bKhEWot+Zj6FGRZjuTz8f18yrukQkiMaRmbHk0tBKNUUHxNCUzHuwyQm guxrNaOngG9bKeem6sWbLNmN/Kb8MYBohKH2t+SGsq2FciwgCXgbN0KkU i/WwH1WZbzXbgIIWmud7kCqX7PbSb9lwysUQwxLHrFDo0AA8E54ubmwYV D4sjhOcXJCJ5oNVI6f6TGQM2kuclFbIMTqxbLinCA+DM0L8cqopKRVj0n m/8tp5kZNYRQoDf3v0nw0ixzAN21HQamKcBBj08LBBOT/UTPeZuG+9H0M EdQ9N0y9JHrigVQ5D35XkH36xhIYaZd1nsNgAt5ZZbGCOhTJF/k09kVI8 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="315790532" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="315790532" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 03:27:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="679309269" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="679309269" Received: from eharan-mobl.ger.corp.intel.com (HELO localhost) ([10.252.58.177]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 03:27:01 -0800 From: Jani Nikula To: "Shankar, Uma" , "Kandpal, Suraj" , "dri-devel@lists.freedesktop.org" , "intel-gfx@lists.freedesktop.org" In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20230222053153.3658345-1-suraj.kandpal@intel.com> <20230222053153.3658345-4-suraj.kandpal@intel.com> Date: Wed, 08 Mar 2023 13:26:58 +0200 Message-ID: <87wn3rbi0t.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 08 Mar 2023, "Shankar, Uma" wrote: >> -----Original Message----- >> From: Kandpal, Suraj >> Sent: Wednesday, February 22, 2023 11:02 AM >> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org >> Cc: Shankar, Uma ; Nautiyal, Ankit K >> ; Kandpal, Suraj ; Kulkarni, >> Vandita >> Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC > > Nit: drm/i915/dsc would be better. > > Looks Good to me. > Reviewed-by: Uma Shankar Except since c3f059483671 ("drm/i915/display: split out DSC and DSS registers") the DSC registers need to go to display/intel_vdsc_regs.h. BR, Jani. > >> Adding new DSC register which are introducted MTL onwards >> >> Signed-off-by: Suraj Kandpal >> Reviewed-by: Vandita Kulkarni >> --- >> drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 596efc940ee7..9e25e21d37e4 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -7715,6 +7715,8 @@ enum skl_power_gate { >> #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - >> PIPE_B, \ >> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ >> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) >> +#define DSC_NATIVE_422_ENABLE BIT(23) >> +#define DSC_NATIVE_420_ENABLE BIT(22) >> #define DSC_ALT_ICH_SEL (1 << 20) >> #define DSC_VBR_ENABLE (1 << 19) >> #define DSC_422_ENABLE (1 << 18) >> @@ -7959,6 +7961,32 @@ enum skl_power_gate { >> #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) >> #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) >> << 0) >> >> +/* MTL Display Stream Compression registers */ >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4 >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4 >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4 >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4 >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) >> _MMIO_PIPE((pipe) - PIPE_B, \ >> + >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \ >> + >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC) >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) >> _MMIO_PIPE((pipe) - PIPE_B, \ >> + >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \ >> + >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC) >> +#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27) >> + >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8 >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8 >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8 >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8 >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) >> _MMIO_PIPE((pipe) - PIPE_B, \ >> + >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \ >> + >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC) >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) >> _MMIO_PIPE((pipe) - PIPE_B, \ >> + >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \ >> + >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC) >> +#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16) >> +#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0) >> + >> /* Icelake Rate Control Buffer Threshold Registers */ >> #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) >> #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) >> -- >> 2.25.1 > -- Jani Nikula, Intel Open Source Graphics Center