From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read
Date: Tue, 14 Feb 2023 12:38:38 +0200 [thread overview]
Message-ID: <87wn4ksf9t.fsf@intel.com> (raw)
In-Reply-To: <20230213225258.2127-13-ville.syrjala@linux.intel.com>
On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We just wrote the EDP transcoder's VTOTAL register a few lines
> earlier, so instead of reading it back out again let's just
> generate the same value for the transocder B/C register.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4210ede5e52e..894f3098d9be 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2891,8 +2891,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
> (pipe == PIPE_B || pipe == PIPE_C))
> intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
> - intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
> -
> + VACTIVE(crtc_vdisplay - 1) |
> + VTOTAL(crtc_vtotal - 1));
> }
>
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-02-14 10:38 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 01/12] drm/i915: Rename intel_ddi_{enable, disable}_pipe_clock() Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 02/12] drm/i915: Flatten intel_ddi_{enable, disable}_transcoder_clock() Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 03/12] drm/i915: Give CPU transcoder timing registers TRANS_ prefix Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/ Ville Syrjala
2023-02-14 10:05 ` Jani Nikula
2023-02-14 10:32 ` Ville Syrjälä
2023-02-14 10:52 ` Jani Nikula
2023-02-14 10:59 ` Ville Syrjälä
2023-02-13 22:52 ` [Intel-gfx] [PATCH 05/12] drm/i915: Dump blanking start/end Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define the "unmodified vblank" interrupt bit Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 07/12] drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 08/12] drm/i915: Add local adjusted_mode variable Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks Ville Syrjala
2023-02-14 10:32 ` Jani Nikula
2023-02-14 10:34 ` Jani Nikula
2023-02-14 10:57 ` Ville Syrjälä
2023-02-13 22:52 ` [Intel-gfx] [PATCH 10/12] drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+ Ville Syrjala
2023-02-16 14:28 ` Jani Nikula
2023-02-13 22:52 ` [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess Ville Syrjala
2023-02-14 10:35 ` Jani Nikula
2023-02-20 21:29 ` Ville Syrjälä
2023-02-13 22:52 ` [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read Ville Syrjala
2023-02-14 10:38 ` Jani Nikula [this message]
2023-02-13 23:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Transcoder timing stuff Patchwork
2023-02-13 23:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-14 2:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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