From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 164E2C433FE for ; Fri, 11 Nov 2022 15:16:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0726410E849; Fri, 11 Nov 2022 15:16:17 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3955E10E83E for ; Fri, 11 Nov 2022 15:16:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668179765; x=1699715765; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=pRM2jRQ81HU7dM9xJYUhOwot8WBB1xJtr1FV/Kc0MpQ=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH v2 04/18] drm/i915: Clean up chv CGM (de)gamma defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 10 Nov 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Add the missing ldw vs. udw information to the CGM (de)gamma > bit definitions to make it a bit easier to see which should > be used where. > > Also use the these appropriately in the LUT entry pack/unpack > functions. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_color.c | 18 +++++++++--------- > drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++------ > 2 files changed, 19 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm= /i915/display/intel_color.c > index 758869971e45..8e92eb61abac 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -1077,13 +1077,13 @@ static void icl_load_luts(const struct intel_crtc= _state *crtc_state) >=20=20 > static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) > { > - return drm_color_lut_extract(color->green, 14) << 16 | > - drm_color_lut_extract(color->blue, 14); > + return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_ex= tract(color->green, 14)) | > + REG_FIELD_PREP(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, drm_color_lut_extract(c= olor->blue, 14)); > } >=20=20 > static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) > { > - return drm_color_lut_extract(color->red, 14); > + return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_RED_UDW_MASK, drm_color_lut_extr= act(color->red, 14)); > } >=20=20 > static void chv_load_cgm_degamma(struct intel_crtc *crtc, > @@ -1104,20 +1104,20 @@ static void chv_load_cgm_degamma(struct intel_crt= c *crtc, >=20=20 > static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color) > { > - return drm_color_lut_extract(color->green, 10) << 16 | > - drm_color_lut_extract(color->blue, 10); > + return REG_FIELD_PREP(CGM_PIPE_GAMMA_GREEN_LDW_MASK, drm_color_lut_extr= act(color->green, 10)) | > + REG_FIELD_PREP(CGM_PIPE_GAMMA_BLUE_LDW_MASK, drm_color_lut_extract(col= or->blue, 10)); > } >=20=20 > static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color) > { > - return drm_color_lut_extract(color->red, 10); > + return REG_FIELD_PREP(CGM_PIPE_GAMMA_RED_UDW_MASK, drm_color_lut_extrac= t(color->red, 10)); > } >=20=20 > static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32= udw) > { > - entry->green =3D intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREE= N_MASK, ldw), 10); > - entry->blue =3D intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_= MASK, ldw), 10); > - entry->red =3D intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MA= SK, udw), 10); > + entry->green =3D intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREE= N_LDW_MASK, ldw), 10); > + entry->blue =3D intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_= LDW_MASK, ldw), 10); > + entry->red =3D intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_UD= W_MASK, udw), 10); > } >=20=20 > static void chv_load_cgm_gamma(struct intel_crtc *crtc, > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index ecb34f133980..f4c08509e629 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7725,13 +7725,17 @@ enum skl_power_gate { > #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) > #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) > #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) > -#define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0) > -#define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16) > -#define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0) > +/* cgm degamma ldw */ > +#define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16) > +#define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0) > +/* cgm degamma udw */ > +#define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0) > #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) > -#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) > -#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) > -#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) > +/* cgm gamma ldw */ > +#define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16) > +#define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0) > +/* cgm gamma udw */ > +#define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0) > #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) > #define CGM_PIPE_MODE_GAMMA (1 << 2) > #define CGM_PIPE_MODE_CSC (1 << 1) --=20 Jani Nikula, Intel Open Source Graphics Center