From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E97EC4332F for ; Fri, 4 Nov 2022 05:10:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0FFD410E02C; Fri, 4 Nov 2022 05:10:20 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 30D1A10E02C for ; Fri, 4 Nov 2022 05:10:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667538616; x=1699074616; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=NXhDLC9w9gFihF8EEyvcnu4TC1ats4YT/czA/aqfGXA=; b=Kd4zFCIka/98whL3DD2sTBhPmHMyTAvZnJvAhm9B/pQSty4piZokPbFU 8oIWiZZQKIwR+wQuB4UsluidDAM/jx4AO7/A4bYg6BkFIXGgNPJ+uENHU 2z+hO7ZWwIzQU2j9BKdP1nMMgJ7i9t/TuAbu5eyny1Sdryp1UMPObqUrL AoroO+NjizDSebrcXbMtwdQMKR2lSrZlznMfaITiEST7FLkixToo2q7tB m3gMMrOFQlOuMenF+5jYIwIjgoJ261sqaog9799TydZBUBSe/5Wkb2jMO GKZKdeIU9gnQbWy/E368ia+v1KZvgvS2bYFv6xxikkxXDzqp3rdB+N5QY w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308595754" X-IronPort-AV: E=Sophos;i="5.96,136,1665471600"; d="scan'208";a="308595754" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 22:10:15 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="668236054" X-IronPort-AV: E=Sophos;i="5.96,136,1665471600"; d="scan'208";a="668236054" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.164.187]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 22:10:15 -0700 Date: Thu, 03 Nov 2022 22:10:14 -0700 Message-ID: <87wn8bl2yx.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20221103180705.1315142-1-umesh.nerlige.ramappa@intel.com> References: <20221103180705.1315142-1-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH] i915/pmu: Use a faster read for 2x32 mmio reads X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 03 Nov 2022 11:07:05 -0700, Umesh Nerlige Ramappa wrote: > Hi Umesh, > PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower > 32 bit registers are read in a loop, there is a latency involved in > getting the GT timestamp. To reduce the latency, define another version > of the helper that requires caller to acquire uncore->spinlock and > necessary forcewakes. Why does this reduces the latency compared to intel_uncore_read64_2x32? Thanks. -- Ashutosh > Signed-off-by: Umesh Nerlige Ramappa > --- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 ++++++++++++++++--- > drivers/gpu/drm/i915/intel_uncore.h | 24 +++++++++++++++++ > 2 files changed, 47 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index 693b07a97789..64b0193c9ee4 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1252,6 +1252,28 @@ static u32 gpm_timestamp_shift(struct intel_gt *gt) > return 3 - shift; > } > > +static u64 gpm_timestamp(struct intel_uncore *uncore, ktime_t *now) > +{ > + enum forcewake_domains fw_domains; > + u64 reg; > + > + /* Assume MISC_STATUS0 and MISC_STATUS1 are in the same fw_domain */ > + fw_domains = intel_uncore_forcewake_for_reg(uncore, > + MISC_STATUS0, > + FW_REG_READ); > + > + spin_lock_irq(&uncore->lock); > + intel_uncore_forcewake_get__locked(uncore, fw_domains); > + > + reg = intel_uncore_read64_2x32_fw(uncore, MISC_STATUS0, MISC_STATUS1); > + *now = ktime_get(); > + > + intel_uncore_forcewake_put__locked(uncore, fw_domains); > + spin_unlock_irq(&uncore->lock); > + > + return reg; > +} > + > static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now) > { > struct intel_gt *gt = guc_to_gt(guc); > @@ -1261,10 +1283,8 @@ static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now) > lockdep_assert_held(&guc->timestamp.lock); > > gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp); > - gpm_ts = intel_uncore_read64_2x32(gt->uncore, MISC_STATUS0, > - MISC_STATUS1) >> guc->timestamp.shift; > + gpm_ts = gpm_timestamp(gt->uncore, now) >> guc->timestamp.shift; > gt_stamp_lo = lower_32_bits(gpm_ts); > - *now = ktime_get(); > > if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp)) > gt_stamp_hi++; > diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h > index 5449146a0624..dd0cf7d4ce6c 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.h > +++ b/drivers/gpu/drm/i915/intel_uncore.h > @@ -455,6 +455,30 @@ static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore, > intel_uncore_write_fw(uncore, reg, val); > } > > +/* > + * Introduce a _fw version of intel_uncore_read64_2x32 so that the 64 bit > + * register read is as quick as possible. > + * > + * NOTE: > + * Prior to calling this function, the caller must > + * 1. obtain the uncore->lock > + * 2. acquire forcewakes for the upper and lower register > + */ > +static inline u64 > +intel_uncore_read64_2x32_fw(struct intel_uncore *uncore, > + i915_reg_t lower_reg, i915_reg_t upper_reg) > +{ > + u32 upper, lower, old_upper, loop = 0; > + > + upper = intel_uncore_read_fw(uncore, upper_reg); > + do { > + old_upper = upper; > + lower = intel_uncore_read_fw(uncore, lower_reg); > + upper = intel_uncore_read_fw(uncore, upper_reg); > + } while (upper != old_upper && loop++ < 2); > + return (u64)upper << 32 | lower; > +} > + > static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore, > i915_reg_t reg, u32 val, > u32 mask, u32 expected_val) > -- > 2.36.1 >