From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9229C433FE for ; Sat, 15 Oct 2022 03:34:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8BEC210E350; Sat, 15 Oct 2022 03:34:57 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id E400C10E34B; Sat, 15 Oct 2022 03:34:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665804893; x=1697340893; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=/4uABFflNwpfgUD6/DSSV8rb/bbLgVN9yw+vj8dpmFU=; b=hPDJuezoZu1jnLVfHC0ELXmFckFsuQo/htVBbNllEmrC/84bnvkPvXOu 5AZz8K2hfPu6XCdTMVZEA5HREAGpjTXm5OegSO9sD41VaG3MATESSjOLn jVMvUU+eTKUACoewRSi7ZJUam5riLY0oFMWtCm2CflfcDwjFWOxPmaE7r q3MV21cS7ve7PgPBdB1aTApnfLb31uU8LqpgJ0HX2KhnnibwToyC/4eNb yUpzUEv9EMtC630sF6qZlZlpfyNbUYIMWMt9B0HXOwoYEpRMO5AQDS07R 4z3MguuVJV/ny6UH+iBAPmG4Fxa9cxh7y2zcTjo7BLANlXfnMlZfBz247 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10500"; a="304253235" X-IronPort-AV: E=Sophos;i="5.95,186,1661842800"; d="scan'208";a="304253235" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2022 20:34:53 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10500"; a="605576158" X-IronPort-AV: E=Sophos;i="5.95,186,1661842800"; d="scan'208";a="605576158" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.12.38]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2022 20:34:52 -0700 Date: Fri, 14 Oct 2022 20:34:52 -0700 Message-ID: <87wn91ep43.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Andi Shyti In-Reply-To: References: <20220919115906.1264041-1-badal.nilawar@intel.com> <20220919115906.1264041-2-badal.nilawar@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Modify CAGF functions for MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rodrigo.vivi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 19 Sep 2022 09:49:07 -0700, Andi Shyti wrote: > > Hi Badal, Hi Andi, Badal is out for a bit so I am sending out this version. > On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote: > > Updated the CAGF functions to get actual resolved frequency of > > 3D and SAMedia > > can you please use the imperative form? "Update" and not > "Updated". > Besides I don't really understand what you did from the > commit, can you please bea bit more descriptive? Done in series version v5. Please take a look. > > Bspec: 66300 > > > > Cc: Vinay Belgaumkar > > Cc: Ashutosh Dixit > > Signed-off-by: Badal Nilawar > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++++++ > > drivers/gpu/drm/i915/gt/intel_rps.c | 6 +++++- > > 2 files changed, 13 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 2275ee47da95..7819d32db956 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -1510,6 +1510,14 @@ > > #define VLV_RENDER_C0_COUNT _MMIO(0x138118) > > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c) > > > > +/* > > + * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/ > > + * 3D - 0x0C60 , SAMedia - 0x380C60 > > + * Intel uncore handler redirects transactions for SAMedia to MTL_MEDIA_GSI_BASE > > + */ > > This comment is not understandable... we don't have limits in > space, you can be a bit more explicit :) Based on Matt R's comment the comment has been deleted (except for the first line). There is an explanation at the bottom of gt/intel_gt_regs.h. Thanks. -- Ashutosh