From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>,
Zhi Wang <zhi.wang.linux@gmail.com>
Subject: Re: [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers
Date: Mon, 13 May 2024 13:13:18 +0300 [thread overview]
Message-ID: <87y18ef29t.fsf@intel.com> (raw)
In-Reply-To: <20240510152329.24098-5-ville.syrjala@linux.intel.com>
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On SKL+ the watermark/DDB registers are proper per-plane
> registers. Move the definitons to their respective files.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_cursor_regs.h | 20 +++++
> .../i915/display/skl_universal_plane_regs.h | 64 ++++++++++++++
> drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
> .../gpu/drm/i915/display/skl_watermark_regs.h | 83 -------------------
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> 5 files changed, 86 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> index 62f7fb5c3f10..a478ef5787c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -75,4 +75,24 @@
> #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
> #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
>
> +/* skl+ */
> +#define _CUR_WM_A_0 0x70140
> +#define _CUR_WM_B_0 0x71140
> +#define _CUR_WM_SAGV_A 0x70158
> +#define _CUR_WM_SAGV_B 0x71158
> +#define _CUR_WM_SAGV_TRANS_A 0x7015C
> +#define _CUR_WM_SAGV_TRANS_B 0x7115C
> +#define _CUR_WM_TRANS_A 0x70168
> +#define _CUR_WM_TRANS_B 0x71168
> +#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> +#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
> +#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> +#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
> +
> +/* skl+ */
> +#define _CUR_BUF_CFG_A 0x7017c
> +#define _CUR_BUF_CFG_B 0x7117c
> +#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> +
> #endif /* __INTEL_CURSOR_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 7e34470beb74..2222d0c760e8 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -402,4 +402,68 @@
> (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> (index) * 4)
>
> +#define _PLANE_WM_1_A_0 0x70240
> +#define _PLANE_WM_1_B_0 0x71240
> +#define _PLANE_WM_2_A_0 0x70340
> +#define _PLANE_WM_2_B_0 0x71340
> +#define _PLANE_WM_SAGV_1_A 0x70258
> +#define _PLANE_WM_SAGV_1_B 0x71258
> +#define _PLANE_WM_SAGV_2_A 0x70358
> +#define _PLANE_WM_SAGV_2_B 0x71358
> +#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
> +#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
> +#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
> +#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
> +#define _PLANE_WM_TRANS_1_A 0x70268
> +#define _PLANE_WM_TRANS_1_B 0x71268
> +#define _PLANE_WM_TRANS_2_A 0x70368
> +#define _PLANE_WM_TRANS_2_B 0x71368
> +#define PLANE_WM_EN (1 << 31)
> +#define PLANE_WM_IGNORE_LINES (1 << 30)
> +#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
> +
> +#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> +#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> +#define _PLANE_WM_BASE(pipe, plane) \
> + _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> +#define PLANE_WM(pipe, plane, level) \
> + _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> +#define _PLANE_WM_SAGV_1(pipe) \
> + _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> +#define _PLANE_WM_SAGV_2(pipe) \
> + _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> +#define PLANE_WM_SAGV(pipe, plane) \
> + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
> +#define _PLANE_WM_SAGV_TRANS_1(pipe) \
> + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> +#define _PLANE_WM_SAGV_TRANS_2(pipe) \
> + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> +#define PLANE_WM_SAGV_TRANS(pipe, plane) \
> + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
> +#define _PLANE_WM_TRANS_1(pipe) \
> + _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> +#define _PLANE_WM_TRANS_2(pipe) \
> + _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> +#define PLANE_WM_TRANS(pipe, plane) \
> + _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> +
> +#define _PLANE_BUF_CFG_1_B 0x7127c
> +#define _PLANE_BUF_CFG_2_B 0x7137c
> +#define _PLANE_BUF_CFG_1(pipe) \
> + _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> +#define _PLANE_BUF_CFG_2(pipe) \
> + _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> +#define PLANE_BUF_CFG(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> +
> +#define _PLANE_NV12_BUF_CFG_1_B 0x71278
> +#define _PLANE_NV12_BUF_CFG_2_B 0x71378
> +#define _PLANE_NV12_BUF_CFG_1(pipe) \
> + _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> +#define _PLANE_NV12_BUF_CFG_2(pipe) \
> + _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> +#define PLANE_NV12_BUF_CFG(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> +
> #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 53a565c673e2..2a2073bf3aca 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -13,6 +13,7 @@
> #include "intel_bw.h"
> #include "intel_cdclk.h"
> #include "intel_crtc.h"
> +#include "intel_cursor_regs.h"
> #include "intel_de.h"
> #include "intel_display.h"
> #include "intel_display_power.h"
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> index 269163fa3350..c5572fc0e847 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> @@ -43,89 +43,6 @@
> #define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
> #define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
>
> -/* Watermark register definitions for SKL */
> -#define _CUR_WM_A_0 0x70140
> -#define _CUR_WM_B_0 0x71140
> -#define _CUR_WM_SAGV_A 0x70158
> -#define _CUR_WM_SAGV_B 0x71158
> -#define _CUR_WM_SAGV_TRANS_A 0x7015C
> -#define _CUR_WM_SAGV_TRANS_B 0x7115C
> -#define _CUR_WM_TRANS_A 0x70168
> -#define _CUR_WM_TRANS_B 0x71168
> -#define _PLANE_WM_1_A_0 0x70240
> -#define _PLANE_WM_1_B_0 0x71240
> -#define _PLANE_WM_2_A_0 0x70340
> -#define _PLANE_WM_2_B_0 0x71340
> -#define _PLANE_WM_SAGV_1_A 0x70258
> -#define _PLANE_WM_SAGV_1_B 0x71258
> -#define _PLANE_WM_SAGV_2_A 0x70358
> -#define _PLANE_WM_SAGV_2_B 0x71358
> -#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
> -#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
> -#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
> -#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
> -#define _PLANE_WM_TRANS_1_A 0x70268
> -#define _PLANE_WM_TRANS_1_B 0x71268
> -#define _PLANE_WM_TRANS_2_A 0x70368
> -#define _PLANE_WM_TRANS_2_B 0x71368
> -#define PLANE_WM_EN (1 << 31)
> -#define PLANE_WM_IGNORE_LINES (1 << 30)
> -#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> -#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
> -
> -#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> -#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
> -#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> -#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> -#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
> -#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> -#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> -#define _PLANE_WM_BASE(pipe, plane) \
> - _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> -#define PLANE_WM(pipe, plane, level) \
> - _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> -#define _PLANE_WM_SAGV_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> -#define _PLANE_WM_SAGV_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> -#define PLANE_WM_SAGV(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
> -#define _PLANE_WM_SAGV_TRANS_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> -#define _PLANE_WM_SAGV_TRANS_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> -#define PLANE_WM_SAGV_TRANS(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
> -#define _PLANE_WM_TRANS_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> -#define _PLANE_WM_TRANS_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> -#define PLANE_WM_TRANS(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> -
> -#define _PLANE_BUF_CFG_1_B 0x7127c
> -#define _PLANE_BUF_CFG_2_B 0x7137c
> -#define _PLANE_BUF_CFG_1(pipe) \
> - _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> -#define _PLANE_BUF_CFG_2(pipe) \
> - _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> -#define PLANE_BUF_CFG(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> -
> -#define _PLANE_NV12_BUF_CFG_1_B 0x71278
> -#define _PLANE_NV12_BUF_CFG_2_B 0x71378
> -#define _PLANE_NV12_BUF_CFG_1(pipe) \
> - _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> -#define _PLANE_NV12_BUF_CFG_2(pipe) \
> - _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> -#define PLANE_NV12_BUF_CFG(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> -
> -/* SKL new cursor registers */
> -#define _CUR_BUF_CFG_A 0x7017c
> -#define _CUR_BUF_CFG_B 0x7117c
> -#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> -
> /*
> * The below are numbered starting from "S1" on gen11/gen12, but starting
> * with display 13, the bspec switches to a 0-based numbering scheme
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index aae0443015f0..6c857beb5083 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -42,6 +42,7 @@
> #include "i915_pvinfo.h"
> #include "intel_mchbar_regs.h"
> #include "display/bxt_dpio_phy_regs.h"
> +#include "display/intel_cursor_regs.h"
> #include "display/intel_display_types.h"
> #include "display/intel_dmc_regs.h"
> #include "display/intel_dp_aux_regs.h"
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-05-13 10:13 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
2024-05-10 15:23 ` [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC() Ville Syrjala
2024-05-13 9:50 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h Ville Syrjala
2024-05-13 10:07 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h Ville Syrjala
2024-05-13 10:10 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers Ville Syrjala
2024-05-13 10:13 ` Jani Nikula [this message]
2024-05-10 15:23 ` [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define Ville Syrjala
2024-05-13 10:21 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define Ville Syrjala
2024-05-13 10:23 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines Ville Syrjala
2024-05-13 10:25 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines Ville Syrjala
2024-05-13 10:30 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines Ville Syrjala
2024-05-13 10:32 ` Jani Nikula
2024-05-13 16:58 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions Ville Syrjala
2024-05-13 11:28 ` Jani Nikula
2024-05-13 16:13 ` Ville Syrjälä
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
2024-05-13 20:30 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits Ville Syrjala
2024-05-13 10:38 ` Jani Nikula
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines Ville Syrjala
2024-05-13 10:40 ` Jani Nikula
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations Ville Syrjala
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
2024-05-13 20:41 ` Jani Nikula
2024-05-13 20:43 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val() Ville Syrjala
2024-05-13 20:43 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write() Ville Syrjala
2024-05-13 20:46 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers Ville Syrjala
2024-05-13 20:52 ` Jani Nikula
2024-05-15 11:17 ` Ville Syrjälä
2024-05-10 16:28 ` ✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff Patchwork
2024-05-11 20:02 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-05-13 18:39 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: skl+ plane register stuff (rev6) Patchwork
2024-05-13 18:39 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-13 18:55 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-14 2:01 ` ✗ Fi.CI.IGT: failure " Patchwork
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