From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92F34C54EE9 for ; Mon, 19 Sep 2022 09:26:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 613A310E5E2; Mon, 19 Sep 2022 09:26:44 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8A85910E5E2 for ; Mon, 19 Sep 2022 09:26:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663579602; x=1695115602; h=from:to:subject:in-reply-to:references:date:message-id: mime-version; bh=z6f3KzpQmooBKLmx5xMc3InY9Gbl2t7OYId5KYkfmf8=; b=LeZ1FLJE+nMX05SRn/6QBNNfoo3lM/zgR+gB/6F41YiU/JfBAF8a2rbl EPsIomRfq4U5tmsrNdC4WmEv8RJzIapiScDPv2Ky1CY6omZQGwB16kE20 UZgtZ1MxKuBp4ccS+oHGxAyvkr6qcKjQl7hhp+Zb8Dhx4SBS0Dv4Ng7ii 5H5uZZkv3X9/f++LlXh1NFuV4edxZLEs7B2KzdoWlMEGRjnhnygIZs7b4 Bo+drZBmsEmVh920hkrBxzxjW6FNLWKN18k5EXamwkB9w6LJkDRdlSZJW aynn0RYNx7bwlIQRYHmudmEEiak7QBpom3tXFYiRmSYr0h+SKXTpflurI Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10474"; a="385640857" X-IronPort-AV: E=Sophos;i="5.93,327,1654585200"; d="scan'208";a="385640857" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2022 02:26:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,327,1654585200"; d="scan'208";a="618418543" Received: from jjohns2-mobl2.amr.corp.intel.com (HELO localhost) ([10.252.57.205]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2022 02:26:35 -0700 From: Jani Nikula To: Anusha Srivatsa , intel-gfx@lists.freedesktop.org In-Reply-To: <20220917004404.414981-3-anusha.srivatsa@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20220917004404.414981-1-anusha.srivatsa@intel.com> <20220917004404.414981-3-anusha.srivatsa@intel.com> Date: Mon, 19 Sep 2022 12:26:19 +0300 Message-ID: <87y1ufpves.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Subject: Re: [Intel-gfx] [PATCH 2/6] drm/i915/display: add cdclk action struct to cdclk_config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 16 Sep 2022, Anusha Srivatsa wrote: > The struct has the action to be performed - squash, crawl > or modeset and the corresponding cdclk which is the desired > cdclk. This is the structure that gets populated during > atomic check once it is determined what the cdclk change looks > like > > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/display/intel_cdclk.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h > index c674879a84a5..3869f93e8ad2 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h > @@ -11,13 +11,27 @@ > #include "intel_display.h" > #include "intel_global_state.h" > > +#define MAX_CDCLK_ACTIONS 1 Okay, this review is just nitpicks, but they'll need to get fixed eventually so here goes. No tab after #define. > + > struct drm_i915_private; > struct intel_atomic_state; > struct intel_crtc_state; > > +enum cdclk_sequence { Needs to be named intel_ something. > + CDCLK_INVALID_ACTION = -1, > + > + CDCLK_SQUASH_ONLY = 0, > + CDCLK_CRAWL_ONLY, > + CDCLK_LEGACY, > +}; > + > struct intel_cdclk_config { > unsigned int cdclk, vco, ref, bypass; > u8 voltage_level; > + struct cdclk_step { Needs to be named intel_ something. Since this is used independently, I'd prefer it to be defined outside of struct intel_cdclk_config. > + enum cdclk_sequence action; > + u32 cdclk; > + } steps[MAX_CDCLK_ACTIONS]; > }; > > struct intel_cdclk_state { -- Jani Nikula, Intel Open Source Graphics Center