From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E237C433EF for ; Wed, 9 Mar 2022 09:34:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD31810E11B; Wed, 9 Mar 2022 09:34:27 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B1BC10E11B for ; Wed, 9 Mar 2022 09:34:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646818466; x=1678354466; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=FPAtWmZHNjgO2INZs2NEJOMMJ5Frwe0Pk9oYkKOGjqE=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 08 Mar 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > struct dp_link_dpll is a pointless wrapper around struct dpll. > Just store the desired link rate into struct dpll::dot and > we're done. > > v2: Document the full divider as a proper decimal number on chv > Nuke bogus eDP 1.4 comments for chv while at it > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/g4x_dp.c | 55 +++++++++------------------ > 1 file changed, 17 insertions(+), 38 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915= /display/g4x_dp.c > index 22345051e667..8e1338678d91 100644 > --- a/drivers/gpu/drm/i915/display/g4x_dp.c > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c > @@ -24,58 +24,37 @@ > #include "intel_pps.h" > #include "vlv_sideband.h" >=20=20 > -struct dp_link_dpll { > - int clock; > - struct dpll dpll; > +static const struct dpll g4x_dpll[] =3D { > + { .dot =3D 162000, .p1 =3D 2, .p2 =3D 10, .n =3D 2, .m1 =3D 23, .m2 =3D= 8, }, > + { .dot =3D 270000, .p1 =3D 1, .p2 =3D 10, .n =3D 1, .m1 =3D 14, .m2 =3D= 2, }, > }; >=20=20 > -static const struct dp_link_dpll g4x_dpll[] =3D { > - { 162000, > - { .p1 =3D 2, .p2 =3D 10, .n =3D 2, .m1 =3D 23, .m2 =3D 8 } }, > - { 270000, > - { .p1 =3D 1, .p2 =3D 10, .n =3D 1, .m1 =3D 14, .m2 =3D 2 } } > +static const struct dpll pch_dpll[] =3D { > + { .dot =3D 162000, .p1 =3D 2, .p2 =3D 10, .n =3D 1, .m1 =3D 12, .m2 =3D= 9, }, > + { .dot =3D 270000, .p1 =3D 1, .p2 =3D 10, .n =3D 2, .m1 =3D 14, .m2 =3D= 8, }, > }; >=20=20 > -static const struct dp_link_dpll pch_dpll[] =3D { > - { 162000, > - { .p1 =3D 2, .p2 =3D 10, .n =3D 1, .m1 =3D 12, .m2 =3D 9 } }, > - { 270000, > - { .p1 =3D 1, .p2 =3D 10, .n =3D 2, .m1 =3D 14, .m2 =3D 8 } } > +static const struct dpll vlv_dpll[] =3D { > + { .dot =3D 162000, .p1 =3D 3, .p2 =3D 2, .n =3D 5, .m1 =3D 3, .m2 =3D 8= 1, }, > + { .dot =3D 270000, .p1 =3D 2, .p2 =3D 2, .n =3D 1, .m1 =3D 2, .m2 =3D 2= 7, }, > }; >=20=20 > -static const struct dp_link_dpll vlv_dpll[] =3D { > - { 162000, > - { .p1 =3D 3, .p2 =3D 2, .n =3D 5, .m1 =3D 3, .m2 =3D 81 } }, > - { 270000, > - { .p1 =3D 2, .p2 =3D 2, .n =3D 1, .m1 =3D 2, .m2 =3D 27 } } > -}; > - > -/* > - * CHV supports eDP 1.4 that have more link rates. > - * Below only provides the fixed rate but exclude variable rate. > - */ > -static const struct dp_link_dpll chv_dpll[] =3D { > - /* > - * CHV requires to program fractional division for m2. > - * m2 is stored in fixed point format using formula below > - * (m2_int << 22) | m2_fraction > - */ > - { 162000, /* m2_int =3D 32, m2_fraction =3D 1677722 */ > - { .p1 =3D 4, .p2 =3D 2, .n =3D 1, .m1 =3D 2, .m2 =3D 0x819999a } }, > - { 270000, /* m2_int =3D 27, m2_fraction =3D 0 */ > - { .p1 =3D 4, .p2 =3D 1, .n =3D 1, .m1 =3D 2, .m2 =3D 0x6c00000 } }, > +static const struct dpll chv_dpll[] =3D { > + /* m2 is .22 binary fixed point */ > + { .dot =3D 162000, .p1 =3D 4, .p2 =3D 2, .n =3D 1, .m1 =3D 2, .m2 =3D 0= x819999a /* 32.4 */ }, > + { .dot =3D 270000, .p1 =3D 4, .p2 =3D 1, .n =3D 1, .m1 =3D 2, .m2 =3D 0= x6c00000 /* 27.0 */ }, > }; >=20=20 > const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) > { > - return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll; > + return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0]; > } >=20=20 > void g4x_dp_set_clock(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv =3D to_i915(encoder->base.dev); > - const struct dp_link_dpll *divisor =3D NULL; > + const struct dpll *divisor =3D NULL; > int i, count =3D 0; >=20=20 > if (IS_G4X(dev_priv)) { > @@ -94,8 +73,8 @@ void g4x_dp_set_clock(struct intel_encoder *encoder, >=20=20 > if (divisor && count) { > for (i =3D 0; i < count; i++) { > - if (pipe_config->port_clock =3D=3D divisor[i].clock) { > - pipe_config->dpll =3D divisor[i].dpll; > + if (pipe_config->port_clock =3D=3D divisor[i].dot) { > + pipe_config->dpll =3D divisor[i]; > pipe_config->clock_set =3D true; > break; > } --=20 Jani Nikula, Intel Open Source Graphics Center