[PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio

[PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio

[Dhinakaran Pandiyan]

According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.

From BSpec:
"Display» BDW-SKL» dpr» [Register] DP_TP_CTL [BDW+,EXCLUDE(CHV)]
Workaround : Do not use DisplayPort with CDCLK less than 432 MHz, audio
enabled, port width x4, and link rate HBR2 (5.4 GHz), or else there may
be audio corruption or screen corruption."

Since, some DP configurations (e.g., MST) use port width x4 and HBR2
link rate, let's increase the cdclk to >= 432 MHz to enable audio for those
cases.

v4: Changed commit message
v3: Combine BDW pixel rate adjustments into a function (Jani)
v2: Restrict fix to BDW
    Retain the set cdclk across modesets (Ville)
Cc: stable@vger.kernel.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 895b3dc..37483ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10261,6 +10261,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
 	bxt_set_cdclk(to_i915(dev), req_cdclk);
 }
 
+static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
+					  int pixel_rate)
+{
+	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+	if (crtc_state->ips_enabled)
+		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
+
+	/* BSpec says "Do not use DisplayPort with CDCLK less than
+	 * 432 MHz, audio enabled, port width x4, and link rate
+	 * HBR2 (5.4 GHz), or else there may be audio corruption or
+	 * screen corruption."
+	 */
+	if (intel_crtc_has_dp_encoder(crtc_state) &&
+	    crtc_state->has_audio &&
+	    crtc_state->port_clock >= 540000 &&
+	    crtc_state->lane_count == 4)
+		pixel_rate = max(432000, pixel_rate);
+
+	return pixel_rate;
+}
+
 /* compute the max rate for new configuration */
 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
 {
@@ -10286,9 +10307,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
 
 		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
 
-		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-		if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
-			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
+		if (IS_BROADWELL(dev_priv))
+			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
+								    pixel_rate);
 
 		intel_state->min_pixclk[i] = pixel_rate;
 	}
-- 
2.7.4

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[PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms

[Dhinakaran Pandiyan]

According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.

Let's apply this work around to GEN9 platforms too, as it fixes the same
issue.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
Cc: stable@vger.kernel.org
Cc: Libin Yang <libin.yang@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 37483ee..c0ae147 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
 					  int pixel_rate)
 {
+	struct drm_device *dev = crtc_state->base.crtc->dev;
+
 	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-	if (crtc_state->ips_enabled)
+	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
 		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
 
 	/* BSpec says "Do not use DisplayPort with CDCLK less than
@@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
 
 		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
 
-		if (IS_BROADWELL(dev_priv))
+		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
 			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
 								    pixel_rate);
 
-- 
2.7.4

✗ Fi.CI.BAT: warning for series starting with [v4,1/2] drm/i915/dp: BDW cdclk fix for DP audio

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/2] drm/i915/dp: BDW cdclk fix for DP audio
URL   : https://patchwork.freedesktop.org/series/14688/
State : warning

== Summary ==

Series 14688v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/14688/revisions/1/mbox/

Test kms_busy:
        Subgroup basic-flip-default-b:
                pass       -> DMESG-WARN (fi-ilk-650)
Test kms_cursor_legacy:
        Subgroup basic-flip-after-cursor-varying-size:
                pass       -> DMESG-WARN (fi-ilk-650)
Test kms_pipe_crc_basic:
        Subgroup bad-source:
                dmesg-warn -> PASS       (fi-ilk-650)
        Subgroup nonblocking-crc-pipe-a-frame-sequence:
                dmesg-warn -> PASS       (fi-ilk-650)
        Subgroup read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-ilk-650)

fi-bdw-5557u     total:241  pass:226  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:241  pass:201  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:241  pass:209  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:241  pass:221  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:241  pass:220  dwarn:0   dfail:0   fail:0   skip:21 
fi-ilk-650       total:241  pass:181  dwarn:6   dfail:0   fail:0   skip:54 
fi-ivb-3520m     total:241  pass:218  dwarn:0   dfail:0   fail:0   skip:23 
fi-ivb-3770      total:241  pass:218  dwarn:0   dfail:0   fail:0   skip:23 
fi-kbl-7200u     total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:241  pass:227  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:241  pass:220  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:241  pass:219  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:241  pass:227  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:241  pass:208  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600      total:241  pass:207  dwarn:0   dfail:0   fail:0   skip:34 

c5ad9c11e819eebcad5b9be5aa5e991e89b26965 drm-intel-nightly: 2016y-11m-01d-16h-36m-25s UTC integration manifest
219db73 drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
d674c15 drm/i915/dp: BDW cdclk fix for DP audio

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2881/
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Re: [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio

[Jani Nikula]

On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> cycling on/off.
>
> From BSpec:
> "Display» BDW-SKL» dpr» [Register] DP_TP_CTL [BDW+,EXCLUDE(CHV)]
> Workaround : Do not use DisplayPort with CDCLK less than 432 MHz, audio
> enabled, port width x4, and link rate HBR2 (5.4 GHz), or else there may
> be audio corruption or screen corruption."
>
> Since, some DP configurations (e.g., MST) use port width x4 and HBR2
> link rate, let's increase the cdclk to >= 432 MHz to enable audio for those
> cases.
>
> v4: Changed commit message
> v3: Combine BDW pixel rate adjustments into a function (Jani)
> v2: Restrict fix to BDW
>     Retain the set cdclk across modesets (Ville)
> Cc: stable@vger.kernel.org
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yup.

> ---
>  drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++---
>  1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 895b3dc..37483ee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10261,6 +10261,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>  	bxt_set_cdclk(to_i915(dev), req_cdclk);
>  }
>  
> +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> +					  int pixel_rate)
> +{
> +	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> +	if (crtc_state->ips_enabled)
> +		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> +
> +	/* BSpec says "Do not use DisplayPort with CDCLK less than
> +	 * 432 MHz, audio enabled, port width x4, and link rate
> +	 * HBR2 (5.4 GHz), or else there may be audio corruption or
> +	 * screen corruption."
> +	 */
> +	if (intel_crtc_has_dp_encoder(crtc_state) &&
> +	    crtc_state->has_audio &&
> +	    crtc_state->port_clock >= 540000 &&
> +	    crtc_state->lane_count == 4)
> +		pixel_rate = max(432000, pixel_rate);
> +
> +	return pixel_rate;
> +}
> +
>  /* compute the max rate for new configuration */
>  static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>  {
> @@ -10286,9 +10307,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>  
>  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>  
> -		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> -		if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
> -			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> +		if (IS_BROADWELL(dev_priv))
> +			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
> +								    pixel_rate);
>  
>  		intel_state->min_pixclk[i] = pixel_rate;
>  	}

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms

[Jani Nikula]

On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> cycling on/off.
>
> Let's apply this work around to GEN9 platforms too, as it fixes the same
> issue.

I'm too tired to read bspec now, but is gen9 really the answer, or just
Skylake?


>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
> Cc: stable@vger.kernel.org
> Cc: Libin Yang <libin.yang@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 37483ee..c0ae147 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>  static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>  					  int pixel_rate)
>  {
> +	struct drm_device *dev = crtc_state->base.crtc->dev;

Nitpick, I guess I'd make that

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

but no big deal.

> +
>  	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> -	if (crtc_state->ips_enabled)
> +	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
>  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
>  
>  	/* BSpec says "Do not use DisplayPort with CDCLK less than
> @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>  
>  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>  
> -		if (IS_BROADWELL(dev_priv))
> +		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
>  			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
>  								    pixel_rate);

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms

[Pandiyan, Dhinakaran]

On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:
> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> > cycling on/off.
> >
> > Let's apply this work around to GEN9 platforms too, as it fixes the same
> > issue.
> 
> I'm too tired to read bspec now, but is gen9 really the answer, or just
> Skylake?
> 
> 

Gen9, applies to BXT and KBL as well. 

-DK

> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
> > Cc: stable@vger.kernel.org
> > Cc: Libin Yang <libin.yang@linux.intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 37483ee..c0ae147 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> >  static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >  					  int pixel_rate)
> >  {
> > +	struct drm_device *dev = crtc_state->base.crtc->dev;
> 
> Nitpick, I guess I'd make that
> 
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> 
> but no big deal.
> 
> > +
> >  	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > -	if (crtc_state->ips_enabled)
> > +	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
> >  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> >  
> >  	/* BSpec says "Do not use DisplayPort with CDCLK less than
> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> >  
> >  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
> >  
> > -		if (IS_BROADWELL(dev_priv))
> > +		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
> >  			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
> >  								    pixel_rate);
> 

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Re: [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms

[Jani Nikula]

On Tue, 01 Nov 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:
>> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
>> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
>> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
>> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
>> > cycling on/off.
>> >
>> > Let's apply this work around to GEN9 platforms too, as it fixes the same
>> > issue.
>> 
>> I'm too tired to read bspec now, but is gen9 really the answer, or just
>> Skylake?
>> 
>> 
>
> Gen9, applies to BXT and KBL as well.

I'll take your word for it, and with that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



>
> -DK
>
>> >
>> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
>> > Cc: stable@vger.kernel.org
>> > Cc: Libin Yang <libin.yang@linux.intel.com>
>> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_display.c | 6 ++++--
>> >  1 file changed, 4 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> > index 37483ee..c0ae147 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> >  static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>> >  					  int pixel_rate)
>> >  {
>> > +	struct drm_device *dev = crtc_state->base.crtc->dev;
>> 
>> Nitpick, I guess I'd make that
>> 
>> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> 
>> but no big deal.
>> 
>> > +
>> >  	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
>> > -	if (crtc_state->ips_enabled)
>> > +	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
>> >  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
>> >  
>> >  	/* BSpec says "Do not use DisplayPort with CDCLK less than
>> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>> >  
>> >  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>> >  
>> > -		if (IS_BROADWELL(dev_priv))
>> > +		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
>> >  			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
>> >  								    pixel_rate);
>> 
>

-- 
Jani Nikula, Intel Open Source Technology Center

[PATCH v5 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms

[Dhinakaran Pandiyan]

According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.

Let's apply this work around to GEN9 platforms too, as it fixes the same
issue.

v2: Move drm_device to drm_i915_private conversion

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
Cc: stable@vger.kernel.org
Cc: Libin Yang <libin.yang@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 37483ee..0d95a2e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
 					  int pixel_rate)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
 	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-	if (crtc_state->ips_enabled)
+	if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
 		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
 
 	/* BSpec says "Do not use DisplayPort with CDCLK less than
@@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
 
 		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
 
-		if (IS_BROADWELL(dev_priv))
+		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
 			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
 								    pixel_rate);
 
-- 
2.7.4

Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms

[Pandiyan, Dhinakaran]

On Tue, 2016-11-01 at 21:50 +0200, Jani Nikula wrote:
> On Tue, 01 Nov 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> > On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:
> >> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> >> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> >> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> >> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> >> > cycling on/off.
> >> >
> >> > Let's apply this work around to GEN9 platforms too, as it fixes the same
> >> > issue.
> >> 
> >> I'm too tired to read bspec now, but is gen9 really the answer, or just
> >> Skylake?
> >> 
> >> 
> >
> > Gen9, applies to BXT and KBL as well.
> 
> I'll take your word for it, and with that,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> 

Thanks for the review. 
> >
> > -DK
> >
> >> >
> >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
> >> > Cc: stable@vger.kernel.org
> >> > Cc: Libin Yang <libin.yang@linux.intel.com>
> >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> >> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> > index 37483ee..c0ae147 100644
> >> > --- a/drivers/gpu/drm/i915/intel_display.c
> >> > +++ b/drivers/gpu/drm/i915/intel_display.c
> >> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> >> >  static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >> >  					  int pixel_rate)
> >> >  {
> >> > +	struct drm_device *dev = crtc_state->base.crtc->dev;
> >> 
> >> Nitpick, I guess I'd make that
> >> 
> >> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >> 
> >> but no big deal.
> >> 
> >> > +
> >> >  	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> >> > -	if (crtc_state->ips_enabled)
> >> > +	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
> >> >  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> >> >  
> >> >  	/* BSpec says "Do not use DisplayPort with CDCLK less than
> >> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> >> >  
> >> >  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
> >> >  
> >> > -		if (IS_BROADWELL(dev_priv))
> >> > +		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
> >> >  			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
> >> >  								    pixel_rate);
> >> 
> >
> 

✗ Fi.CI.BAT: warning for series starting with [v4,1/2] drm/i915/dp: BDW cdclk fix for DP audio (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/2] drm/i915/dp: BDW cdclk fix for DP audio (rev2)
URL   : https://patchwork.freedesktop.org/series/14688/
State : warning

== Summary ==

Series 14688v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/14688/revisions/2/mbox/

Test drv_module_reload_basic:
                pass       -> DMESG-WARN (fi-skl-6770hq)

fi-bdw-5557u     total:241  pass:226  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:241  pass:201  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:241  pass:209  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:241  pass:221  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:241  pass:220  dwarn:0   dfail:0   fail:0   skip:21 
fi-ilk-650       total:241  pass:187  dwarn:0   dfail:0   fail:0   skip:54 
fi-ivb-3520m     total:241  pass:218  dwarn:0   dfail:0   fail:0   skip:23 
fi-ivb-3770      total:241  pass:218  dwarn:0   dfail:0   fail:0   skip:23 
fi-kbl-7200u     total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:241  pass:227  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:241  pass:220  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:241  pass:219  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:241  pass:226  dwarn:1   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:241  pass:208  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600      total:241  pass:207  dwarn:0   dfail:0   fail:0   skip:34 

bf6b989af8b0fde56a352d9005c97b2d8e3bbbe3 drm-intel-nightly: 2016y-11m-02d-15h-44m-03s UTC integration manifest
6346fda drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
884d02ce drm/i915/dp: BDW cdclk fix for DP audio

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2895/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Fi.CI.BAT: warning for series starting with [v4,1/2] drm/i915/dp: BDW cdclk fix for DP audio (rev2)

[Jani Nikula]

On Wed, 02 Nov 2016, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: series starting with [v4,1/2] drm/i915/dp: BDW cdclk fix for DP audio (rev2)
> URL   : https://patchwork.freedesktop.org/series/14688/
> State : warning
>
> == Summary ==
>
> Series 14688v2 Series without cover letter
> https://patchwork.freedesktop.org/api/1.0/series/14688/revisions/2/mbox/
>
> Test drv_module_reload_basic:
>                 pass       -> DMESG-WARN (fi-skl-6770hq)

LSPCON being cranky.

Pushed both to drm-intel-next-queued, thanks for the patches.

BR,
Jani.

>
> fi-bdw-5557u     total:241  pass:226  dwarn:0   dfail:0   fail:0   skip:15 
> fi-bsw-n3050     total:241  pass:201  dwarn:0   dfail:0   fail:0   skip:40 
> fi-bxt-t5700     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
> fi-byt-j1900     total:241  pass:213  dwarn:0   dfail:0   fail:0   skip:28 
> fi-byt-n2820     total:241  pass:209  dwarn:0   dfail:0   fail:0   skip:32 
> fi-hsw-4770      total:241  pass:221  dwarn:0   dfail:0   fail:0   skip:20 
> fi-hsw-4770r     total:241  pass:220  dwarn:0   dfail:0   fail:0   skip:21 
> fi-ilk-650       total:241  pass:187  dwarn:0   dfail:0   fail:0   skip:54 
> fi-ivb-3520m     total:241  pass:218  dwarn:0   dfail:0   fail:0   skip:23 
> fi-ivb-3770      total:241  pass:218  dwarn:0   dfail:0   fail:0   skip:23 
> fi-kbl-7200u     total:241  pass:219  dwarn:0   dfail:0   fail:0   skip:22 
> fi-skl-6260u     total:241  pass:227  dwarn:0   dfail:0   fail:0   skip:14 
> fi-skl-6700hq    total:241  pass:220  dwarn:0   dfail:0   fail:0   skip:21 
> fi-skl-6700k     total:241  pass:219  dwarn:1   dfail:0   fail:0   skip:21 
> fi-skl-6770hq    total:241  pass:226  dwarn:1   dfail:0   fail:0   skip:14 
> fi-snb-2520m     total:241  pass:208  dwarn:0   dfail:0   fail:0   skip:33 
> fi-snb-2600      total:241  pass:207  dwarn:0   dfail:0   fail:0   skip:34 
>
> bf6b989af8b0fde56a352d9005c97b2d8e3bbbe3 drm-intel-nightly: 2016y-11m-02d-15h-44m-03s UTC integration manifest
> 6346fda drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
> 884d02ce drm/i915/dp: BDW cdclk fix for DP audio
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2895/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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