From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 01/18] drm/i915: Comments for semaphore clarification Date: Wed, 07 Nov 2012 15:30:41 +0200 Message-ID: <87y5idlev2.fsf@intel.com> References: <1352219142-1395-1-git-send-email-ben@bwidawsk.net> <1352219142-1395-2-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id A8FAC9E77C for ; Wed, 7 Nov 2012 05:25:12 -0800 (PST) In-Reply-To: <1352219142-1395-2-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Tue, 06 Nov 2012, Ben Widawsky wrote: > Semaphores are tied very closely to the rings in the GPU. Trivial patch > adds comments to the existing code so that when we add new rings we can > include comments there as well. It also helps distinguish the ring to > semaphore mailbox interactions by using the ringname in the semaphore > data structures. > > This patch should have no functional impact. Reviewed-by: Jani Nikula > > A subset of this patch was: > Reviewed-by: Chris Wilson > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------ > drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++--------- > drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- > 3 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9118bd1..f82755e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -252,12 +252,12 @@ > #define MI_SEMAPHORE_UPDATE (1<<21) > #define MI_SEMAPHORE_COMPARE (1<<20) > #define MI_SEMAPHORE_REGISTER (1<<18) > -#define MI_SEMAPHORE_SYNC_RV (2<<16) > -#define MI_SEMAPHORE_SYNC_RB (0<<16) > -#define MI_SEMAPHORE_SYNC_VR (0<<16) > -#define MI_SEMAPHORE_SYNC_VB (2<<16) > -#define MI_SEMAPHORE_SYNC_BR (2<<16) > -#define MI_SEMAPHORE_SYNC_BV (0<<16) > +#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */ > +#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */ > +#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */ > +#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */ > +#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */ > +#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */ > #define MI_SEMAPHORE_SYNC_INVALID (1<<0) > /* > * 3D instructions used by the kernel > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index a035ac2..423948f 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1503,9 +1503,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > ring->irq_enable_mask = GT_USER_INTERRUPT; > ring->get_seqno = gen6_ring_get_seqno; > ring->sync_to = gen6_ring_sync; > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; > ring->signal_mbox[0] = GEN6_VRSYNC; > ring->signal_mbox[1] = GEN6_BRSYNC; > } else if (IS_GEN5(dev)) { > @@ -1639,9 +1639,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) > ring->irq_put = gen6_ring_put_irq; > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; > ring->sync_to = gen6_ring_sync; > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; > ring->signal_mbox[0] = GEN6_RVSYNC; > ring->signal_mbox[1] = GEN6_BVSYNC; > } else { > @@ -1684,9 +1684,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) > ring->irq_put = gen6_ring_put_irq; > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; > ring->sync_to = gen6_ring_sync; > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; > ring->signal_mbox[0] = GEN6_RBSYNC; > ring->signal_mbox[1] = GEN6_VBSYNC; > ring->init = init_ring_common; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 5af65b8..df1a0a2 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -89,7 +89,7 @@ struct intel_ring_buffer { > struct intel_ring_buffer *to, > u32 seqno); > > - u32 semaphore_register[3]; /*our mbox written by others */ > + u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */ > u32 signal_mbox[2]; /* mboxes this ring signals to */ > /** > * List of objects currently involved in rendering from the > -- > 1.8.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx