From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Subject: Re: [Intel-gfx] [PATCH v7 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
Date: Tue, 02 Jul 2019 15:16:17 +0300
Message-ID: <87zhlw3a3y.fsf@gaia.fi.intel.com>
References: <20190628120720.21682-1-lionel.g.landwerlin@intel.com> <20190628120720.21682-3-lionel.g.landwerlin@intel.com> <156206601183.2466.7357010939425742878@skylake-alporthouse-com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, Lionel Landwerlin <lionel.g.landwerlin@intel.com>, intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
List-Id: intel-gfx@lists.freedesktop.org

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Lionel Landwerlin (2019-06-28 13:07:19)
>> CFL:C0+ changed the status of those registers which are now
>> blacklisted by default.
>> 
>> This is breaking a number of CTS tests on GL & Vulkan :
>> 
>>   KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)
>> 
>>   dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)
>> 
>> v2: Only use one whitelist entry (Lionel)
>
> Bspec: 14091

Sometimes we have optionally used References: BSID#0934 to
mark the workaround. But it feels a tad redudant now.

>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Cc: stable@vger.kernel.org
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>