From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB
Date: Fri, 30 Oct 2015 14:31:23 +0200 [thread overview]
Message-ID: <87ziz0pmg4.fsf@intel.com> (raw)
In-Reply-To: <20151030120851.GD4437@intel.com>
On Fri, 30 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Oct 30, 2015 at 12:06:09PM +0200, Jani Nikula wrote:
>> On Thu, 29 Oct 2015, ville.syrjala@linux.intel.com wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > We get spurious PCH FIFO underruns if we enable the reporting too soon
>> > after enabling the crtc. Move it to be the last step, after the encoder
>> > enable. Additionally we need an extra vblank wait, otherwise we still
>> > get the underruns. Presumably the pipe/fdi isn't yet fully up and running
>> > otherwise.
>> >
>> > For symmetry, disable the PCH underrun reporting as the first thing,
>> > just before encoder disable, when shutting down the crtc.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++----
>> > 1 file changed, 9 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> > index 99fb33f..d5cb899 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -4874,7 +4874,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>> > intel_crtc->active = true;
>> >
>> > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>> > - intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
>> >
>> > for_each_encoder_on_crtc(dev, crtc, encoder)
>> > if (encoder->pre_enable)
>> > @@ -4912,6 +4911,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>> >
>> > if (HAS_PCH_CPT(dev))
>> > cpt_verify_modeset(dev, intel_crtc->pipe);
>> > +
>> > + if (intel_crtc->config->has_pch_encoder) {
>> > + /* Must wait for vblank to avoid spurious PCH FIFO underruns */
>> > + intel_wait_for_vblank(dev, pipe);
>> > + intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
>>
>> Nitpick, moving this within the if (has_pch_encoder) isn't documented in
>> the commit message. Does that change have an impact?
>
> I don't much of a real concern here. I think the following might
> happen (all on the same pipe):
>
> 1. enable PCH port
> 2. disable PCH port
> 3. PCH FIFO underrun just after we've re-enabled the PCH
> underrun reporting
> 4. enable port A
> 5. PCH FIFO underrun reporting isn't enabled anymore for this pipe
>
> But since it's driving a non-PCH port anyway, that doesn't seem like
> a huge worry. But I suppose I could change it to always enable PCH
> FIFO underrun reporting even for port A. It should do no harm at least.
Mostly I just wanted this change documented in the commit message.
Jani.
>
>>
>> BR,
>> Jani.
>>
>> > + }
>> > }
>> >
>> > /* IPS only exists on ULT machines and is tied to pipe A. */
>> > @@ -5040,15 +5045,15 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>> > int pipe = intel_crtc->pipe;
>> > u32 reg, temp;
>> >
>> > + if (intel_crtc->config->has_pch_encoder)
>> > + intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>> > +
>> > for_each_encoder_on_crtc(dev, crtc, encoder)
>> > encoder->disable(encoder);
>> >
>> > drm_crtc_vblank_off(crtc);
>> > assert_vblank_disabled(crtc);
>> >
>> > - if (intel_crtc->config->has_pch_encoder)
>> > - intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>> > -
>> > intel_disable_pipe(intel_crtc);
>> >
>> > ironlake_pfit_disable(intel_crtc, false);
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-10-30 12:27 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-29 19:25 [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms ville.syrjala
2015-10-29 19:25 ` [PATCH 01/14] drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config around ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 02/14] drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL ville.syrjala
2015-10-29 19:33 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:57 ` Paulo Zanoni
2015-10-29 21:21 ` Ville Syrjälä
2015-10-30 15:42 ` Daniel Vetter
2015-10-30 10:06 ` Jani Nikula
2015-10-30 12:08 ` Ville Syrjälä
2015-10-30 12:31 ` Jani Nikula [this message]
2015-10-30 15:41 ` Daniel Vetter
2015-10-30 17:20 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+ ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 05/14] drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled ville.syrjala
2015-10-29 19:36 ` Jesse Barnes
2015-10-29 21:39 ` Ville Syrjälä
2015-10-30 17:21 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 06/14] drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPT ville.syrjala
2015-10-30 15:45 ` Daniel Vetter
2015-10-30 17:22 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 07/14] drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder() ville.syrjala
2015-10-29 19:37 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 08/14] drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround ville.syrjala
2015-10-29 19:38 ` Jesse Barnes
2015-10-30 10:11 ` Jani Nikula
2015-10-30 12:15 ` Ville Syrjälä
2015-10-30 17:23 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 09/14] drm/i915: Hide underruns from eDP PLL and port enable on ILK ville.syrjala
2015-10-29 19:39 ` Jesse Barnes
2015-10-29 21:33 ` Ville Syrjälä
2015-10-29 19:25 ` [PATCH 10/14] drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/ ville.syrjala
2015-10-30 15:49 ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 11/14] drm/i915: Remove ILK-A eDP PLL workaround notes ville.syrjala
2015-10-29 19:40 ` Jesse Barnes
2015-10-29 19:26 ` [PATCH 12/14] drm/i915: Clean up eDP PLL state asserts ville.syrjala
2015-10-30 15:53 ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 13/14] drm/i915: Use intel_dp->DP in eDP PLL setup ville.syrjala
2015-10-30 16:00 ` Daniel Vetter
2015-10-30 16:36 ` Ville Syrjälä
2015-11-10 14:37 ` Jani Nikula
2015-11-10 14:16 ` [PATCH v2 " ville.syrjala
2015-11-10 14:43 ` Jani Nikula
2015-10-29 19:26 ` [PATCH 14/14] drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on() ville.syrjala
2015-10-30 16:01 ` Daniel Vetter
2015-10-30 13:30 ` [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms Jani Nikula
2015-11-10 15:04 ` Ville Syrjälä
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87ziz0pmg4.fsf@intel.com \
--to=jani.nikula@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox